Cirrus Logic CS5351-KZ, CS5351-KS, CS5351-BZ, CS5351-BS Datasheet

CS5351

108 dB, 192 kHz, Multi-Bit Audio A/D Converter

Features



Advanced Multi-bit Delta-Sigma Architecture



24-Bit Conversion



108 dB Dynamic Range



-98 dB THD+N



System Sampling Rates up to 192 kHz



Single-Ended Analog Inputs



Less than 150 mW Power Consumption



High Pass Filter or DC Offset Calibration



Supports Logic Levels Between 5 and 2.5V



Linear Phase Digital Anti-Alias Filtering



Overflow Detection



Functionally Compatible with the CS5361

General Description

The CS5351 is a complete analog-to-digital converter for
digital audio systems. It performs sampling, analog-to­digital conversion and anti-alias filtering, generating 24­bit values for both left and right inputs in serial form at
sample rates up to 192 kHz per channel.

The CS5351 uses a 5th-order, multi-bit delta-sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.

The CS5351 is ideal for audio systems requiring wide dy­namic range, negligible distortion and low noise, such as
A/V receivers, DVD-R, CD-R, digital mixing consoles,
and effects processors.

ORDERING INFORMATION

CS5351-KS -10° to 70° C 24-pin SOIC
CS5351-BS -40° to 85° C 24-pin SOIC
CS5351-KZ -10° to 70° C 24-pin TSSOP
CS5351-BZ -40° to 85° C 24-pin TSSOP
CDB5351 Evaluation Board

FILT+

AINL

AINR

VQ LRCK

Voltage Reference

S/H

S/H

REFGND

+

-

+

-

Preliminary Product Information

http://www.cirrus.com

SCLK

V

L

Serial Audio Interface

LP Filter

DAC

LP Filter

DAC

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

∆Σ

∆Σ

CopyrightCirrus Logic, Inc. 2002

Digital

Decimation

Filter

Digital

Decimation

Filter

(All Rights Reserved)

SDOUT MCLK

High
Pass
Filter

High
Pass
Filter

RST

I2S/LJ

M/S

HPF

MDIV

MODE0

MODE1

SEPT ‘02

DS565PP2

1

TABLE OF CONTENTS

1 PIN DESCRIPTIONS .................................................................................................................4

2 TYPICAL CONNECTION DIAGRAM ......................................................................................... 5

3 APPLICATIONS ......................................................................................................................... 6

3.1 Operational Mode/Sample Rate Range Select ..................................................................6

3.2 System Clocking ................................................................................................................ 6

3.2.1 Master Mode .........................................................................................................7

3.2.2 Slave Mode ........................................................................................................... 8

3.3 Power-up Sequence .......................................................................................................... 8

3.4 Analog Connections ........................................................................................................... 8

3.5 High Pass Filter and DC Offset Calibration ....................................................................... 9

3.6 Overflow Detection ............................................................................................................. 9

3.6.1 OVFL Output Timing ........................................................................................... 10

3.7 Grounding and Power Supply Decoupling ....................................................................... 10

3.8 Synchronization of Multiple Devices ................................................................................ 10

4 CHARACTERISTICS AND SPECIFICATIONS .......................................................................11

ANALOG CHARACTERISTICS (CS5351-KS/KZ) ..................................................................11

ANALOG CHARACTERISTICS (CS5351-BS/BZ) ..................................................................12

DIGITAL DECIMATION FILTER CHARACTERISTICS.......................................................... 13

DC ELECTRICAL CHARACTERISTICS................................................................................. 16

DIGITAL CHARACTERISTICS............................................................................................... 16

THERMAL CHARACTERISTICS............................................................................................ 16

ABSOLUTE MAXIMUM RATINGS ......................................................................................... 17

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 18

5 PARAMETER DEFINITIONS ................................................................................................... 21

6 PACKAGE DIMENSIONS .....................................................................................................22

7 ADDENDUM ............................................................................................................................ 24

CS5351

LIST OF FIGURES

Figure 1. Typical Connection Diagram ............................................................................................5

Figure 2. CS5351 Master Mode Clocking ....................................................................................... 7

Figure 3. CS5351 Recommended Analog Input Buffer ................................................................... 9

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to <http://www.cirrus.com/corporate/contacts/sales.cfm>

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product inf or­mation describes products that are in development and subject to development changes. Cirrus Logic, I nc. and its subsidiari es ("Cirrus") believe that the inf or­mation contained in this document is accurate and reliable. However, the informati on is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant i nformation to verify, before pl acing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infrin gement, and l imitation of liabil ity. No responsibility is assumed by Cirrus for the use of thi s information, including use of this
information as the basis for manufacture or sale of any items, or for i nfringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishi ng this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
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An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thisma­terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies describ ed in this material is subject to the PRC Foreign
Trade Law and i s to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT­ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

Cirrus Logic, Cirrus, and the Cirrus Logi c logo designs are trademarks of Cirrus Logic, Inc. All other br and and pr oduct names in this document may be trade­marks or service marks of their r especti ve owners.

2 DS565PP2

CS5351

Figure 4. Single Speed Mode Stopband Rejection ....................................................................... 14

Figure 5. Single Speed Mode Transition Band ............................................................................. 14

Figure 6. Single Speed Mode Transition Band (Detail)................................................................. 14

Figure 7. Single Speed Mode Passband Ripple ........................................................................... 14

Figure 8. Double Speed Mode Stopband Rejection...................................................................... 14

Figure 9. Double Speed Mode Transition Band ............................................................................ 14

Figure 10. Double Speed Mode Transition Band (Detail) ............................................................. 15

Figure 11. Double Speed Mode Passband Ripple ........................................................................ 15

Figure 12. Quad Speed Mode Stopband Rejection ...................................................................... 15

Figure 13. Quad Speed Mode Transition Band............................................................................. 15

Figure 14. Quad Speed Mode Transition Band (Detail)................................................................ 15

Figure 15. Quad Speed Mode Passband Ripple........................................................................... 15

Figure 16. Master Mode, Left Justified SAI................................................................................... 19

Figure 17. Slave Mode, Left Justified SAI..................................................................................... 19

Figure 18. Master Mode, I
Figure 19. Slave Mode, I

Figure 20. OVFL Output Timing.................................................................................................... 19

Figure 21. Left-Justified Serial Audio Interface ............................................................................. 20

Figure 22. I

Figure 23. OVFL Output Timing, I2S Format ................................................................................ 20

Figure 24. OVFL Output Timing, Left-Justified Format ................................................................. 20

Figure 25. CS5351/CS5361 Analog Input Buffer .......................................................................... 24

2

S Serial Audio Interface............................................................................................. 20

2

S SAI .................................................................................................. 19

2

S SAI .................................................................................................... 19

LIST OF TABLES

Table 1. CS5351 Mode Control ............................................................................................................. 6

Table 2. CS5351 Common Master Clock Frequencies ........................................................................ 7

Table 3. CS5351 Slave Mode Clock Ratios .......................................................................................... 8

DS565PP2 3

1 PIN DESCRIPTIONS

Pin Name # Pin Description

RST

M/S

LRCK

SCLK

MCLK

VD

GND

VL

SDOUT

MDIV

HPF

2

I

S/LJ

M0
M1

OVFL

AINR
AINL

VQ1
VQ2
VQ3

VA

REF_GND

FILT+

Reset (Input) - The device enters a low power mode when low.

1

Master/Slave Mode (Input) - Selects operation as either clock master or slave.

2

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

3

serial audio data line.

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

4

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

5

6 Digital Power (Input) - Positive power supply for the digital section.

Ground (Input) - Ground reference. Must be connected to analog ground.

7,18

Logic Power (Input) - Positive power for the digital input/output.

8

Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

9

MCLK Divider (Input)-Enables a master clock divide by two function.

10

High Pass Filter Enable (Input)-Enables the Digital High-Pass Filter.

11

Serial Audio Interface Format Select (Input) -Selects either the left-justified or I2S format for the SAI.

12

13,

Mode Selection (Input) - Determines the operational mode of the device.

14

Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.

15

Analog Input (Input) - The full scale analog input level is specified in the Analog Characteristics specifi-

16,

cation table.

21

Quiescent Voltage (Input/Output) - Filter connection for the internal quiescent reference voltage.

17,
20,

22

19 Analog Power (Input) - Positive power supply for the analog section.

Reference Ground (Input) - Ground reference for the internal sampling circuits.

23

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

24

RST 124FILT+

M/S 223REFGND

LRCK 322VQ3

SCLK 421AINR

MCLK 520VQ2

VD 619VA

GND 718GND

VL 817VQ1

SDOUT 916AINL

MDIV 10 15 OVFL

HPF 11 14 M1

2

I

S/LJ 12 13 M0

CS5351

4 DS565PP2

2 TYPICAL CONNECTION DIAGRAM

CS5351

+5V

47µF

+

+5 V to 3.3 V

+

+

1µF

Analog

Input

Buffer

(Figure 3 )

1µF

0.1

+

1µF 0.1µF

0.1

FILT+

0.1µF

REFGND

µ

F

VQ

VQ 2

VQ 1

AINL

AINR

µ

F

VA V L

3

Ω

5.1

CS5351

A/D CONVERTER

0.1 µF

VD

0.1µF

OVFL

RST

2

I

S/LJ

M/S

HPF

M0

M1

MDIV

SDOUT

LRCK

SCLK

MCLK

+

VL

1

10 k

µ

F

Ω

+5V to 2.5V

Power Down

and Mode

Se tting s

Audio Data

Processor

Timing Logic

and Clock

GND

GND

Figure 1. Typical Connection Diagram

DS565PP2 5

CS5351

3 APPLICATIONS

3.1 Operational Mode/Sample Rate Range Select

The output sample rate, Fs, can be adjusted from 2kHz to 192kHz. The CS5351 must be set to the proper
speed mode via the mode pins, M1 and M0. Refer to Table 1.

M1 (Pin 14) M0 (Pin 13) MODE Output Sample Rate (Fs)

0 0 Single Speed Mode 2kHz - 50kHz
0 1 Double Speed Mode 50kHz - 100kHz
1 0 Quad Speed Mode 100kHz - 192kHz
11Reserved

Table 1. CS5351 Mode Control

3.2 System Clocking

The device supports operation in either Master Mode, where the left/right and serial clocks are synchro­nously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial
clocks. The device also includes a master clock divider in Master Mode where the master clock will be
internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode
the MDIV pin needs to be disabled, set to logic 0.

6 DS565PP2

CS5351

3.2.1 Master Mode

In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived
from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown
in Figure 2. Refer to Table 2 for common master clock frequencies

MCLK

÷ 1

÷ 2

SAMPLE RATE (kHz)

32 8.192 16.384

44.1 11.2896 22.5792
48 12.288 24.576
64 8.192 16.384

88.2 11.2896 22.5792
96 12.288 24.576

176.4 11.2896 22.5792
192 12.288 24.576

Table 2. CS5351 Common Master Clock Frequencies

÷ 256

÷ 128

÷ 64

Single
Speed

Double

Speed

Speed

0

1

÷ 4

MDIV

÷ 2

÷ 1

Figure 2. CS5351 Master Mode Clocking

MDIV = 0

MCLK (MHz)

Single

Speed

Double

Speed

Speed

Quad

Quad

00

01

10

M0M1

00

01

10

MDIV = 1

MCLK (MHz)

LRCK Output

(Equal to Fs)

SCLK Output

DS565PP2 7

CS5351

3.2.2 Slave Mode

LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived
from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously
derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 3
for required clock ratios.

Single Speed Mode
Fs = 2kHz to 50kHz

MCLK/LRCK Ratio 256x (512x)* 128x (256x)* 128x (256x)*

SCLK/LRCK Ratio 32x, 64x, 128x 32x, 64x 64x

Double Speed Mode

Fs = 50kHz to 100kHz

Quad Speed Mode

Fs = 100kHz to 192kHz

*Available when MDIV = 1 (for Master Mode)

Table 3. CS5351 Slave Mode Clock Ratios

3.3 Power-up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power glitch related issues.

The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de­lay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance.

3.4 Analog Connections

The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject
signals within the stopband of the filter. However, there is no rejection for input signals which are

× 6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to Figure 3 which shows the sug-

(n
gested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum
source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such
as general purpose ceramics) must be avoided since these can degrade signal linearity.

Please see the Addendum at the end of the datasheet for an analog input buffer that can be used with both
the CS5351 as well as the CS5361 with a simple change in the bill of materials.

8 DS565PP2

634Ω

CS5351

470 pF

COG

AIN L

AINR

100 uF

100 uF

10kΩ

10kΩ

-

+

+

-

634

VQ

470 pF

COG

Ω

91Ω

CS5351 AINL

COG

2700 pF

91Ω

CS5351 AINR

COG

2700 pF

Figure 3. CS5351 Recommended Analog Input Buffer

3.5 High Pass Filter and DC Offset Calibration

The operational amplifiers in the input circuitry driving the CS5351 may generate a small DC offset into
the A/D converter. The CS5351 includes a high pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding "clicks" when switching between devices in
a multichannel system.

The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPF

pin is taken high during normal operation, the current value of the DC offset register is
frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it
possible to perform a system DC offset calibration by:

1) Running the CS5351 with the high pass filter enabled until the filter settles.See the Digital Filter Char-

acteristics for filter settling time.

2) Disabling the high pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5351.

3.6 Overflow Detection

The CS5361 includes overflow detection on both the left and right channels. This time multiplexed infor­mation is presented as open drain, active low on pin 15, OVFL
to a logical low as soon as an overrange condition in either channel is detected. The data will remain low

DS565PP2 9

. The OVFL_L and OVFL_R data will go

CS5351

as specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to
detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R
data will return to a logical high if there has not been any other overrange condition detected. Please note
that an overrange condition on either channel will restart the timeout period for both channels.

3.6.1 OVFL Output Timing

In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I2S format,
the OVFL
cases the OVFL
format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of
LRCK would latch the left channel overflow status. In I
the right channel overflow status and the rising edge of LRCK would latch the left channel overflow status.

3.7 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS5351 requires careful attention to power supply and ground­ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power
arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be
run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no
additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The
FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electri­cal path from FILT+ and REFGND. The CDB5351 evaluation board demonstrates the optimum layout and
power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS
inputs.

pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23 and 24. In both

data can be easily demultiplexed by using the LRCK to latch the data. In left-justified

2

S format, the falling edge of LRCK would latch

3.8 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5351’s in the sys­tem. If only one master clock source is needed, one solution is to place one CS5351 in Master mode, and
slave all of the other CS5351’s to the one master. If multiple master clock sources are needed, a possible
solution would be to supply all clocks from the same external source and time the CS5351 reset with the
inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.

10 DS565PP2

CS5351

4 CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (CS5351-KS/KZ) (Test conditions (unless otherwise speci-

fied): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Typical performance char­acteristics are derived from measurements taken at T
performance characteristics are guaranteed over the specified operating temperature and voltages.)

Parameter Symbol Min Typ Max Unit

Single Speed Mode Fs = 48kHz

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 1)

-1 dB

-20 dB

-60 dB

Double Speed Mode Fs = 96kHz

Dynamic Range A-weighted

unweighted

40kHz bandwidth unweighted

Total Harmonic Distortion + Noise (Note 1)

-1 dB

-20 dB

-60 dB

40kHz bandwidth -1dB

Quad Speed Mode Fs = 192kHz

Dynamic Range A-weighted

unweighted

40kHz bandwidth unweighted

Total Harmonic Distortion + Noise (Note 1)

-1 dB

-20 dB

-60 dB

40kHz bandwidth -1dB

Dynamic Performance for All Modes

Interchannel Isolation - 95 - dB
Interchannel Phase Deviation - 0.0001 - Degree

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB
Gain Error -

Gain Drift ­Offset Error HPF enabled

HPF disabled

Analog Input Characteristics

Full-scale Input Voltage 0.95 1.0 1.05 Vrms
Input Impedance 18 - - k

=25°C, VL = VD = 3.3V and VA = 5.0V. Min/Max

A

102

99

THD+N

-

-

-

102

99

-

THD+N

-

-

-

-

102

99

-

THD+N

-

-

-

-

108
105

-98

-85

-45

108
105
102

-98

-85

-45

-95

108
105
102

-98

-85

-45

-95

-

-

-92

-

-

-

-

-

-92

-

-

-

-

-

-

-92

-

-

-

±5

±100 - ppm/°C

-

-

0

100

-

-

dB
dB

dB
dB
dB

dB
dB
dB

dB
dB
dB
dB

dB
dB
dB

dB
dB
dB
dB

%

LSB
LSB

Ω

Note: 1. Referred to the typical full-scale input voltage

DS565PP2 11

CS5351

ANALOG CHARACTERISTICS (CS5351-BS/BZ) (Test conditions (unless otherwise speci-

fied): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Typical performance char­acteristics are derived from measurements taken at T

performance characteristics are guaranteed over the specified operating temperature and voltages.)

Parameter Symbol Min Typ Max Unit

Single Speed Mode Fs = 48kHz

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 1)

-1 dB

-20 dB

-60 dB

Double Speed Mode Fs = 96kHz

Dynamic Range A-weighted

unweighted

40kHz bandwidth unweighted

Total Harmonic Distortion + Noise (Note 1)

-1 dB

-20 dB

-60 dB

40kHz bandwidth -1dB

Quad Speed Mode Fs = 192kHz

Dynamic Range A-weighted

unweighted

40kHz bandwidth unweighted

Total Harmonic Distortion + Noise (Note 1)

-1 dB

-20 dB

-60 dB

40kHz bandwidth -1dB

Dynamic Performance for All Modes

Interchannel Isolation - 95 - dB
Interchannel Phase Deviation - 0.0001 - Degree

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB
Gain Error ­Gain Drift ­Offset Error HPF enabled

HPF disabled

Analog Input Characteristics

Full-scale Input Voltage 0.9 1.0 1.1 Vrms
Input Impedance 18 - - k

=25°C, VL = VD = 3.3V and VA = 5.0V. Min/Max

A

101

98

THD+N

-

-

-

101

98

-

THD+N

-

-

-

-

101

98

-

THD+N

-

-

-

-

108
105

-98

-85

-45

108
105
102

-98

-85

-45

-95

108
105
102

-98

-85

-45

-95

-

-

-91

-

-

-

-

-

-91

-

-

-

-

-

-

-91

-

-

-

±5%

±100 - ppm/°C

-

-

0

100

-

-

dB
dB

dB
dB
dB

dB
dB
dB

dB
dB
dB
dB

dB
dB
dB

dB
dB
dB
dB

LSB
LSB

Ω

12 DS565PP2

CS5351

DIGITAL DECIMATION FILTER CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Single Speed Mode (2kHz to 50kHz sample rates)

Passband (-0.1 dB) (Note 3) 0 - 0.47 Fs

Passband Ripple - - ±0.035 dB

Stopband (Note 3) 0.58 - - Fs

Stopband Attenuation -95 - - dB

Total Group Delay (Fs = Output Sample Rate) t

Group Delay Variation vs. Frequency ∆t

gd

gd

Double Speed Mode (50kHz to 100kHz sample rates)

Passband (-0.1 dB) (Note 3) 0 - 0.45 Fs

Passband Ripple - - ±0.035 dB

Stopband (Note 3) 0.68 - - Fs

Stopband Attenuation -92 - - dB

Total Group Delay (Fs = Output Sample Rate) t

Group Delay Variation vs. Frequency ∆t

gd

gd

Quad Speed Mode (100kHz to 192kHz sample rates)

Passband (-0.1 dB) (Note 3) 0 - 0.24 Fs

Passband Ripple - - ±0.035 dB

Stopband (Note 3) 0.78 - - Fs

Stopband Attenuation -97 - - dB

Total Group Delay (Fs = Output Sample Rate) t

Group Delay Variation vs. Frequency ∆t

gd

gd

High Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 2)

Phase Deviation @ 20Hz (Note 2) - 10 - Deg

Passband Ripple - - 0 dB

Filter Settling Time 10

-12/Fs- s

--0.0µs

-9/Fs- s

--0.0µs

-5/Fs- s

--0.0µs

-120-

5

/Fs s

-

Hz
Hz

Notes: 2. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

3. The filter frequency response scales precisely with Fs.

DS565PP2 13

CS5351

0

-10

-20

-30

-40

-50

-60

-70

-80

Amplitude (dB)

-90

-100

-110

-120

-130

-140

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to Fs)

0

-10

-20

-30

-40

-50

-60

-70

-80

Amplitud e (dB)

-90

-100

-110

-120

-130

-140

0.40 0.42 0.44 0.4 6 0.48 0.50 0.52 0.54 0.56 0. 58 0.60

Frequenc y (normalize d to Fs)

Figure 4. Single Speed Mode Stopband Rejection Figure 5. Single Speed Mode Transition Band

0

-1

-2

-3

-4

-5

Amplitude (dB)

-6

-7

-8

-9

-10

0.45 0.46 0.47 0 .48 0. 49 0.50 0.51 0.52 0.53 0.54 0.55

Frequency (normalized to Fs)

0.10

0.08

0.05

0.03

0.00

Amplitude (dB)

-0.03

-0.05

-0.08

-0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalizedto Fs)

Figure 6. Single Speed Mode Transition Band (Detail)

0

-10

-20

-30

-40

-50

-60

-70

-80

Amplitude (dB)

-90

-100

-110

-120

-130

-140

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (norma lized to Fs)

Figure 7. Single Speed Mode Passband Ripple

0

-10

-20

-30

-40

-50

-60

-70

-80

Amplitude (d B)

-90

-100

-110

-120

-130

-140

0.40 0.43 0.45 0.48 0.50 0.5 3 0.55 0.5 8 0.60 0.63 0.65 0. 68 0.70

Frequency(normalized toFs)

Figure 8. Double Speed Mode Stopband Rejection Figure 9. Double Speed Mode Transition Band

14 DS565PP2

CS5351

0

-1

-2

-3

-4

-5

Amplitude (dB)

-6

-7

-8

-9

-10

0.40 0.43 0.45 0.48 0 .50 0.5 3 0.55

Frequency (normalized to Fs)

0.10

0.08

0.05

0.03

0.00

Amplitu de (dB)

-0.03

-0.05

-0.08

-0.10

0.00 0.05 0.1 0 0.15 0 .20 0.25 0.30 0.35 0. 40 0.45 0.50

Frequency (normalizedto Fs)

Figure 10. Double Speed Mode Transition Band (Detail) Figure 11. Double Speed Mode Passband Ripple

0

-10

-20

-30

-40

-50

-60

-70

Amplitude (dB)

-80

-90

-100

-110

-120

0.0 0.1 0.2 0.3 0.4 0 .5 0. 6 0 .7 0.8 0.9 1 .0

Frequency (norma lized to Fs)

0

-10

-20

-30

-40

-50

-60

-70

Amplitude (dB)

-80

-90

-100

-110

-120

-130

0.2 0.2 5 0.3 0.35 0 .4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8

Frequency (normalized to Fs)

Figure 12. Quad Speed Mode Stopband Rejection Figure 13. Quad Speed Mode Transition Band

0

-1

-2

-3

-4

-5

Amplitude (dB)

-6

-7

-8

-9

-10

0.1 0.15 0 .2 0.25 0 .3 0.35 0. 4 0 .45 0.5 0. 55 0.6

Frequency ( normalized to F s)

0.10

0.08

0.06

0.04

0.02

0.00

Amplitude (dB )

-0.02

-0.04

-0.06

-0.08

-0.10

0.00 0.05 0.10 0.1 5 0.20 0.25

Frequenc y (normalize d to Fs)

Figure 14. Quad Speed Mode Transition Band (Detail) Figure 15. Quad Speed Mode Passband Ripple

DS565PP2 15

CS5351

DC ELECTRICAL CHARACTERISTICS (GND = 0V, all voltages with respect to ground.

MCLK=12.288 MHz; Master Mode)

Parameter Symbol Min Typ Max Unit

DC Power Supplies: Positive Analog

Positive Digital

Positive Logic

Power Supply Current VA
(Normal Operation) VL,VD = 5 V

VL,VD = 3.3V

Power Supply Current VA
(Power-Down Mode)(Note 4) VL,VD=5V

Power Consumption
(Normal Operation) VL, VD=5V

VL, VD = 3.3V

(Power-Down Mode)

Power Supply Rejection Ratio (1 kHz) (Note 5) PSRR - 65 - dB

V

Nominal Voltage

Q

Output Impedance
Maximum allowable DC current source/sink

Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink

VA

VD

VL

I

A

I

D

I

D

I

A

I

D

-

-

-

4.75

3.1

2.37

-

-

-

-

-

-

-

-

-

-

-

-

-

-

5.0

-

-

17.5
22

14.5

2
2

198
135

20

2.5
25

0.01

5

35

0.01

5.25

5.25

5.25

21
26
17

-

-

235
161

-

-

-

-

-

-

-

mA
mA
mA

mA
mA

mW
mW
mW

kΩ

mA

kΩ

mA

V
V
V

V

V

Notes: 4. Power Down Mode is defined as RST

= Low with all clocks and data lines held static.

5. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.

DIGITAL CHARACTERISTICS

Parameter Symbol Min Typ Max Units

High-Level Input Voltage (% of VL) V

Low-Level Input Voltage (% of VL) V

High-Level Output Voltage at I

Low-Level Output Voltage at I

OVFL

Current Sink I

= 100 uA (% of VL) V

o

=100 uA (% of VL) V

o

Input Leakage Current I

IH

IL

OH

OL

ovfl

in

70% - - V

--30%V

70% - - V

--15%V

--4.0mA

--±10 µA

THERMAL CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Allowable Junction Temperature - - 135 °C

Junction to Ambient Thermal Impedance

Ambient Operating Temperature (Power Applied)

-KS/KZ

-BS/BZ

θ

JA

T

A

T

A

-70 -°C/W

-10

-40

-

-

+70
+85

°C
°C

16 DS565PP2

CS5351

ABSOLUTE MAXIMUM RATINGS (GND = 0V, All voltages with respect to ground.) (Note 8)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Analog

Logic

Digital

Input Current (Note 6) I

Analog Input Voltage (Note 7) V

Digital Input Voltage (Note 7) V

Ambient Operating Temperature (Power Applied) T

Storage Temperature T

Notes: 6. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SRC

latch-up.

7. The maximum over/under voltage is limited by the input current.

8. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

VA

VL

VD

in

IN

IND

A

stg

-0.3

-0.3

-0.3

--±10 mA

GND-0.7 - VA+0.7 V

-0.7 - VL+0.7 V

-50 - +95 °C

-65 - +150 °C

-

-

-

+6.0
+6.0
+6.0

V
V
V

DS565PP2 17

CS5351

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V;

Logic "1" = VL = 2.37V to 5.25V, VA = 5V

Parameter Symbol Min Typ Max Unit

Input Sample Rate Single Speed Mode

OVFL to LRCK edge setup time t

OVFL to LRCK edge hold time t

OVFL time-out on overrange condition

Fs = 44.1, 88.2, 176.4kHz

MCLK Specifications

MCLK Period t

MCLK Pulse Width High t

MCLK Pulse Width Low t

Master Mode

SCLK falling to LRCK t

SCLK falling to SDOUT valid t

SCLK Duty Cycle - 50 - %

SCLK Output Frequency - 50 - %

Slave Mode

Single Speed

Output Sample Rate Fs 2 - 50 kHz

LRCKDutyCycle 405060%

SCLK Period t

SCLK High/Low t

SCLK falling to SDOUT valid t

SCLK falling to LRCK edge t

Double Speed

Output Sample Rate Fs 50 - 100 kHz

LRCKDutyCycle 405060%

SCLK Period t

SCLK High/Low t

SCLK falling to SDOUT valid t

SCLK falling to LRCK edge t

Quad Speed

Output Sample Rate Fs 100 - 192 kHz

LRCKDutyCycle 405060%

SCLK Period t

SCLK High/Low t

SCLK falling to SDOUT valid t

SCLK falling to LRCK edge t

±5%, VD = 3.1V to 5.25V, C

Double Speed Mode

Quad Speed Mode

Fs = 48, 96, 192kHz

=20pF)

L

Fs
Fs
Fs

setup

hold

clkw

clkh 15 - - ns

clkl 15 - - ns

mslr

sdo

sclkw

sclkhl

dss

slrd

sclkw

sclkhl

dss

slrd

sclkw

sclkhl

dss

slrd

100

16/f

1/f

2

50

sclk

sclk

-

-

-

-

-

50
100
192

--s

--s

740
680

-

-

40 - 1953 ns

-20 - 20 ns

0 - 40 ns

163 - - ns

20 - - ns

- - 40 ns

-20 - 20 ns

163 - - ns

20 - - ns

- - 40 ns

-20 - 20 ns

81 - - ns

20 - - ns

- - 20 ns

-10 - 10 ns

kHz
kHz
kHz

ms
ms

18 DS565PP2

t

sclkh

CS5351

t

sclkl

SCLK output

LRCK
output

SDOUT

msl

t

r

sd

t

o

MSB MSB-1

SCLK input

LRCK input

SDOUT

t

srdl

t

lrdss

MSB MSB-1 MSB-2

Figure 16. Master Mode, Left Justified SAI Figure 17. Slave Mode, Left Justified SAI

t

sclkh

SCLK
output

LRCK output

SDOUT

t

mslr

t

sdo

MSB

SCLK input

LRCK input

SDOUT

t

sclkw

t

dss

t

sclkl

t

sclkw

t

dss

MSB MSB-1

Figure 18. Master Mode, I2S SAI Figure 19. Slave Mode, I2SSAI

LRCK

t

setup

t

hold

OVFL

Figure 20. OVFL Output Timing

DS565PP2 19

CS5351

LRCK

SCLK

SDATA 23 22 7 6 23 22

Left C hannel Right Channel

23 225432108 7654321089 9

Figure 21. Left-Justified Serial Audio Interface

LRCK

SCLK

SDA TA 2 3 22 8 7 23 22

Left Channel Right Channel

23 226543210 8765432109 9

Figure 22. I2S Serial Audio Interface

LRCK

SCLK

OVFL

LRCK

SCLK

OVFL

OVFL_R OVFL_L OVFL_R

Figure 23. OVFL Output Timing, I2SFormat

OVFL_R OVFL_L OVFL_R

Figure 24. OVFL Output Timing, Left-Justified Format

20 DS565PP2

5 PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not affect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

CS5351

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

DS565PP2 21

6 PACKAGE DIMENSIONS

24L SOIC (300 MIL BODY) PACKAGE DRAWING

1

b

CS5351

HE

c

SEATING

PLANE

D

A

e

A1

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.093 0.104 2.35 2.65

A1 0.004 0.012 0.10 0.30

B 0.013 0.020 0.33 0.51
C 0.009 0.013 0.23 0.32
D 0.598 0.614 15.20 15.60
E 0.291 0.299 7.40 7.60

e 0.040 0.060 1.02 1.52

H 0.394 0.419 10.00 10.65

L 0.016 0.050 0.40 1.27

∝ 0° 8° 0° 8°

∝

L

22 DS565PP2

CS5351

24L TSSOP (4.4 mm BODY) PACKAGE DRAWING

N

1

23

TOP VIEW

D

E

e

2

b

SIDE VIEW

A2

A1

A

SEATING

PLANE

L

INCHES MILLIMETERS

1

E1

END VIEW

NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10
A1 0.002 0.004 0.006 0.05 -- 0.15
A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3
D 0.303 0.307 0.311 7.70 7.80 7.90 1
E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

∝

0° 4° 8° 0° 4° 8°

∝

JEDEC #: MO-153

Controlling Dimension is Millimeters.

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

DS565PP2 23

CS5351

7 ADDENDUM

The CS5351 and CS5361 family of analog-to-digi­tal converters are functionally compatible and can
easily be interchanged with minimal modifications
to the input buffer circuitry.

Figure 25 shows an analog input buffer that pro­vides anti-alias filtering, proper dc biasing, and op­timum source impedance for the modulators. The
input buffer shown will work well with both the
CS5351 and the CS5361, merely by changing the
bill of materials.

In order to use this buffer design with the CS5351,
one would stuff the 0ohm resistors R19 and R22
and not populate R3 and R20. This will create a sin­gle-ended input buffer (as shown in Figure 3) with
the unused differential input pin connected to the
quiescent voltage of the converter (VQ). Note that
in this configuration, it is unnecessary to have the
second op-amp and related components.

In order to use this buffer design with the CS5361,
one would stuff the 0ohm resistors R3 and R20 and
not populate R19 and R22. This will create a fully
differential analog input buffer.

Figure 25. CS5351/CS5361 Analog Input Buffer

24 DS565PP2