Advanced Multi-bit Delta-Sigma Architecture
24-bit Conversion
Supports All Audio Sample Rates Including
192 kHz
101 dB Dynamic Range at 5 V
-94 dB THD+N
90 mW Power Consumption
High-Pass Filter to Remove DC Offsets
Analog/Digital Core Supplies from 3.3 V to 5 V
Supports Logic Levels between 1.8 V and 5 V
Auto-detect Mode Selection in Slave Mode
Auto-Detect MCLK Divider
General Description
The CS5340 is a complete an alog-to-digital converter
for digital audio systems. It perfor ms sa mplin g, an alog to-digital conversion, and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form
at sample rates up to 200 kHz per channel.
The CS5340 uses a 5th-order, multi-bit Delta-Sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The CS5340 is available in a 16-pin TSSOP package
for Commercial (-10° to +70° C) and Automotive grades
(-40° to +85° C). The CDB5340 Customer Demonstration Board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 22 for complete ordering
information.
The CS5340 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as set-top boxes, DVD-karaoke players, DVD recorders, A/V receivers, and automotive applications.
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 17
DS601F23
Confidential Draft
3/11/08
CS5340
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and spe cif icat ion s ar e de riv e d from measurements taken at typical supply voltages
and T
= 25°C.)
A
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
ParameterSymbol Min TypMaxUnit
Power SuppliesAnalog
Digital
Logic
Ambient Operating TemperatureCommercial
Automotive
VA
VD
VL
T
T
AC
AC
3.1
3.1
1.7
-10
-40
(Note 1)
3.3
3.3
-
-
5.25
5.25
5.25
70
85
V
V
V
°C
°C
Notes:
1. This part is specified at typical analog vo ltages of 3. 3 V and 5. 0 V. See Ana log Ch arac terist ics - Commercial Grade and Analog Characteristics - Automotive Grade, below, for details.
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 2)
ParameterSymbolMinMaxUnits
DC Power Supplies:Analog
Logic
Digital
Input Current(Note 3)
Analog Input Voltage(Note 4)
Digital Input Voltage(Note 4)
Ambient Operating Temperature (Power Applied)T
Storage Temperature
V
T
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SRC latch-up.
4. The maximum over/under voltage is limited by the input current.
VA
VL
VD
I
in
V
IND
stg
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
V
V
V
-10+10mA
IN
GND-0.7VA+0.7V
-0.7VL+0.7V
A
-50+95
°C
-65+150°C
4DS601F2
Confidential Draft
3/11/08
CS5340
ANALOG CHARACTERISTICS - COMMERCIAL GRADE
Test Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
Dynamic Performance for Commercial GradeVA = 5 VVA = 3.3 V
Single-Speed Mode Fs = 48 kHz
Dynamic RangeA-weighted
unweighted
Total Harmonic Distortion + Noise(Note 5)
-1 dB
-20 dB
-60 dB
Double-Speed Mode Fs = 96 kHz
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise (Note 5)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
SymbolMinTypMaxMinTypMaxUnit
95
92
THD+N
101
98
-
-
-
-94
-78
-38
-88
-
-
-
-
92
89
98
95
-
-91
-
-75
-
-35
-
-
-85
-
-
dB
dB
dB
dB
dB
SymbolMinTypMaxMinTypMaxUnit
95
92
THD+N
101
98
-
-
-
-
-
95
-94
-78
-38
-91
-88
-
-
-
-
-
-
92
89
98
95
-
-
-
-
-
92
-91
-75
-35
-85
-
-
-
-85
-
-
-
dB
dB
dB
dB
dB
dB
dB
Quad-Speed Mode Fs = 192 kHz
Dynamic RangeA-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise(Note 5)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
Dynamic Performance All Modes
Interchannel Isolation-90-dB
SymbolMinTypMaxMinTypMaxUnit
95
92
THD+N
101
98
-
-
-
-
-
95
-94
-78
-38
-91
-88
-
-
-
-
-
-
92
89
98
95
-
-
-
-
-
92
-91
-75
-35
-85
MinTypMax
-
-
-
-85
-
-
-
dB
dB
dB
dB
dB
dB
dB
Unit
DC Accuracy
Interchannel Gain Mismatch-0.1-dB
Gain Error-5-+5%
Gain Drift-
MCLK2Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VL3Logic Power (Input) - Positive power for the digital input/output.
SDOUT4Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
GND5,14Ground (Input) - Ground reference. Must be connected to analog ground.
VD6Digital Power (Input) - Positive power supply for the digital section.
SCLK7Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK8
RST
AINL
AINR
VQ11
VA13Analog Power (Input) - Positive power supply for the analog section.
FILT+15
1
16
9Reset (Input) - The device enters a low power mode when low.
10
12
Mode Selection (Input) - Determines the operational mode of the device.
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio data line.
Analog Input (Input) - The full-scale analog input level is specified in the Analog Charac-
teristics specification table.
Quiescent Volt age (Output) - Filter connection for the internal quiescent
reference voltage.
Positive Voltage Reference (Output) - Positive reference voltage for the internal
sampling circuits.
1
1
1
1
2
2
2
2
3
3
4
4
5
5
5
5
6
6
6
6
7
7
8
8
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
DS601F213
Confidential Draft
3. TYPICAL CONNECTION DIAGRAM
3.3V to 5V
3.3V to 5V
µ
1
+
Analog Input Buffer
Figure 21
+
1µF
+
1µF
***
+
F
0.1µF
0.1µF
0.1µF
FILT+
VA
5.1
**
Ω
D
V
REFGND
1µ
0.1µF
F
VQ
CS5340
A/D CONVERTER
AINL
AINR
3/11/08
0.1µF
V
0.1µF
L
RST
SDOUT
M0
M1
+
VL or GND
10k
Ω
CS5340
1.8 V to 5V
1µF
Power Down
and Mode
Settin g s
*
Audio Data
Processor
GND
MCLK
LRCK
SCLK
* Pull-up to VL for I2S
Pull-down to GND for LJ
** Resistor may only be
used if VD is derived from
VA. If used, do not drive
any other logic from VD
Timing Logic
and Clock
*** Cap a c ito r v a lue a ff ec ts
low frequency distortion
performance as described
in Section 4.8
14DS601F2
Confidential Draft
3/11/08
4. APPLICATIONS
4.1Single-, Double-, and Quad-Speed Modes
The CS5340 can support outpu t sample rates from 2 kHz to 200 kHz. The prop er spee d mode can be de termined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
Speed Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
* Quad-Speed Mode, 64x only available in Master Mode.
Table 1. S peed Modes and the Associated Output Sample Rates (Fs)
The CS5340 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK
pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the
LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The
selection of clock master or slave is made via the Mode pins as shown in Table 2.
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as
shown in Figure 18.
MCLK
÷ 1
÷ 2
0
1
3/11/08
÷ 256
÷ 128
÷ 64
÷ 4
Single
Speed
Double
Speed
Quad
Speed
Single
Speed
00
01
10
00
CS5340
LRCK Output
(Equal to Fs)
M0M1
Auto-Select
Figure 18. CS5340 Master Mode Clocking
4.2.2Operation as a Clock Slave with Auto-Detect
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the
serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system
performance.
A unique feature of the CS5340 is the automatic selection of either Single-, Double- or Quad-Speed mode
when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode
pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio
sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are
not supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Do uble-, and Quad -Speed
Modes, respectively). Please refer to Table for supported sample rate ranges.
÷ 2
÷ 1
Double
Speed
Quad
Speed
01
10
SCLK Output
16DS601F2
Confidential Draft
3/11/08
4.2.3Master Clock
The CS5340 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is also an internal MCLK divider which is automatically activated based on the speed mode and
frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required.
Table 4 lists some comm on audio output sample rates and th e required MCLK frequency. Please note
that not all of the listed sample rates are supported when operating with a fast MCLK (512x, 256x, 128x
for Single-, Double-, and Quad-Speed Modes, respectively).
Single-Speed ModeDouble-Speed ModeQuad-Speed Mode
MCLK/LRCK Ratio256x, 512x128x, 256x64x*,128x
* Quad Speed, 64x only available in Master Mode.
T able 3. Master Clock (MCLK) Ratios
SAMPLE RATE (kHz)MCLK (MHz)
328.192
44.111.2896
22.5792
4812.288
24.576
648.192
88.211.2896
22.5792
9612.288
24.576
19212.288
24.576
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
CS5340
4.3Serial Audio Interface
The CS5340 supports both I²S and Left-Justified serial audio formats. Upon start-up, the CS5340 will detect
the logic level on SDOUT (pin 4). A 10 kΩ pull-up to VL is needed to select I²S format, and a 10 kΩ pulldown to GND is needed to select Left-Justified format. Figures 19 and 20 illustrate the I²S and Left-Justified
audio formats. Please see Figures 13 through 16, for more information on the required timing for the two
serial audio interface formats. Also see Application Note AN28 2 for a detaile d discussion o f the serial aud io
interface formats.
LRC K
SCLK
SDATA23 228 723 22
LRCK
SCLK
SDATA23 227 623 22
Left ChannelRight Channel
23 22654321087654321099
Figure 19. I²S Serial Audio Interface
Left ChannelRight Channel
23 22543210876543210899
Figure 20. Left-Justified Serial Audio Interface
DS601F217
Confidential Draft
4.4Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power-glitch-related issues.
4.5Analog Connections
The analog modulator samples the input at half of the MCLK frequency, or nominally 6.144MHz. The digital
filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which
are multiples of the input sampling frequency (n
shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the
optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient
(such as general purpose ceramics ) m ust be av oided since these can degrade signal linearity.
AINx
100 kΩ
4.7 µF
100 kΩ
VA
3/11/08
CS5340
× 6.144 MHz), where n=0,1,2,... Refer to Figure 21 which
634 Ω
470 pF
C0G
91 Ω
CS5340 AINx
2700 pF
Figure 21. CS5340 Recommended Analog Input Buffer
4.6Grounding and Power Supply Decoupling
As with any high-resolution converter, achieving optimal performance from the CS5340 requires carefu l attention to power supply and grounding arrangements. Figure 17 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the
system logic supply or may be powered from the analog supply via a resistor. In this case, no additional
devices should be powered from VD. Decoupling capacito rs should be as near to the ADC as possible, with
the low-value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from
the FILT+ and VQ pins in order to avoid unwanted cou pling into the modu lators. The FILT+ a nd VQ decoupling capacitors, particularly the 0.01 µF, must be positioned to minimize the electrical path from FILT+ and
REF_GND. Furthermore, all ground pins on CS5340 should be referenced to the same ground reference.
The CDB5340 evaluation board demonstrates the optim um layout and power supply arr angements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
4.7Synchronization of Multiple Devices
In systems where multiple ADCs are required, the user can a chieve simultaneous sampling if the MCLK and
LRCK signals are the same for all of the CS5340’s in the system. If only one master clock source is needed,
one solution is to place one CS5340 in Master mode, and slave all of the othe r CS5340’s to the one master.
If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same
external source and time the CS5340 reset with the inactive (falling) edge of MCLK. This will ensure that all
converters begin sampling on the same clock edge.
18DS601F2
Confidential Draft
3/11/08
4.8Capacitor Size on the Reference Pin (FILT+)
The CS5340 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this
decoupling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger
capacitor values used to optimize low frequency distortion performance. This plot was taken using the
CDB5340 evaluation platform, with the device running in Single-Speed Mode and VA=VD=VL=5 V.
1 uF
2.2 uF
3.3 uF
4.7 uF
5.6 uF
6.8 uF
10 uF
47 uF
22 uF
CS5340
100 uF
Figure 22. CS5340 THD+N versus Frequency
DS601F219
Confidential Draft
5. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal t o the rms su m of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal t o the rms su m of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude r es po ns e va riatio n from 10 Hz to 20 kHz relative to the amplitude r es po ns e at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
3/11/08
CS5340
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog input for a full-scale digital output.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
20DS601F2
Confidential Draft
3/11/08
6. PACKAGE DIMENSIONS
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS
ParameterSymbolMinTypMaxUnit
Allowable Junction Temperatu re--135
Junction to Ambient Thermal Impedanceθ
Redefine Serial Audio Port Switching Characteristics
Correct dimension “e” under Package Dimensions
Update Output Sample Rate Range
Update maximum current and power specifications
Update Filt+ output impedance specification
Reduced minimum sample rate to 4 kHz for Double-Speed Mode 128x in Table 1 on page 15
Updated Legal Text
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without not ice and is pr ovided "AS IS" witho ut warr anty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other inte llectual property rig hts. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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or service marks of their respective owners.
22DS601F2
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