Cirrus Logic CS5180-CL Datasheet
CS5180
∆Σ Modulator & 8 kHz to 400 kHz 16-Bit ADC
Features
16-Bit Delta-Sigma A/D Converter
Fully Differential Input with 4.0 VppRange
Dynamic Range: 93 dB
Spurious Free Dynamic Range: 96 dB
Total Harmonic Distortion: -95 dB @ 22 kHz
Up to 400 kHz Output Word Rate
No Missing Codes
Non-Aliasing Low-Pass Digital Filter
High Speed 3-Wire Serial Interface
Supply Options:
- VA+=5V,VD+=5V,690mW
- VA+=5V,VD+=3V,368mW
Modulator Output Mode
Power Down Mode
I
VA+
AGND
Description
CS5180 is a fully calibrated high-speed ∆Σ analog-todigital converter, capable of 400 kSamples/second output word rate (OWR). The OWR scales with the master
clock. It consists of a 5th order ∆Σ modulator, decimation
filter, and serial interface. The chip can use the 2.375 V
on-chip voltage reference, or an external 2.5 V reference. The input voltage range is 1.6 × VREFIN V
differential. Multiple CS5180s can be fully synchronized
in multi-channel applications with a SYNC signal. The
part has a power-down mode to minimize power consumption at times of system inactivity. The high speed
digital I/O lines have complementary signals to help reduce radiated noise from traces on the PC board. The
CS5180 can also be operated in modulator-only mode
which provides the delta-sigma modulator bitstream as
the output.
ORDERING INFORMATION
CS5180-CL 0 °C to 70 °C 28-pin PLCC
VD+
DGND
pp
fully
AIN+
AIN-
VREF-
VREF+
VREFIN
VREFOUT
VREFCAP
x1.6
Reference
∆Σ
Modulator
PWDN SYNC RESET MODE
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Decimator Clock
Mode
Selector
Timing
and
Control
Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrus Logic, Inc. 2002
(All Rights Reserved)
Serial
Interface
MCLK
MCLK
MFLAG
SDO
SDO
SCLK
SCLK
FSO
DS259PP4
APR ‘02
1
TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS ............................................................4
ANALOG CHARACTERISTICS...................................................................4
DYNAMIC CHARACTERISTICS ................................................................. 6
DIGITAL CHARACTERISTICS.................................................................... 6
SWITCHING CHARACTERISTICS ............................................................. 7
RECOMMENDED OPERATING CONDITIONS .......................................... 8
ABSOLUTE MAXIMUM RATINGS.............................................................. 8
GENERAL DESCRIPTION .................................................................................. 9
THEORY OF OPERATION .................................................................................. 9
Converter Initialization: Calibration and Synchronization .......................... 9
Clock Generator ........................................................................................ 10
Voltage Reference .................................................................................... 10
Analog Input ............................................................................................. 11
Output Coding .......................................................................................... 11
Modulator-Only mode ............................................................................... 11
Instability Indicator .................................................................................... 13
Digital Filter Characteristics ...................................................................... 13
Serial Interface .......................................................................................... 13
Power Supplies / Board Layout ................................................................ 13
Power-down Mode .................................................................................... 15
PIN DESCRIPTION ............................................................................................ 16
PARAMETER DEFINITIONS ............................................................................. 19
APPENDIX A: CIRCUIT APPLICATIONS ......................................................... 21
PACKAGE OUTLINE DIMENSIONS ................................................................. 26
CS5180
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product inf ormation describes products that are in production, but for which full characterization data is not yet available. "Advance" product inf ormation describes products that are in development and subject to devel opment changes. Cirrus Logi c, I nc. and its subsi diari es ("Cirrus") believe that the inf ormation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, befor e placing orders, that information being
relied on is current and complete. All products are sold subj ect to the terms and conditions of sal e supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, i ncludi ng use of this
information as the basis for manufacture or sale of any items, or for i nfringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishi ng th is information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, tr ade secrets or
other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gi ves consent for copies to be made of the i nformation only
for use within your organization with respect to Ci rrus integrat ed circuits or ot her parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional p urposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thismaterial and controll ed under the "Foreign Exchange and Forei gn Trade Law" i s to be exported or taken out of Japan. An export l icense and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies describe d in this material is subject to the PRC Foreign
Trade Law and i s to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logi c logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2
LIST OF FIGURES
Figure 1. Serial Port Timing (not to scale) .................................................................. 7
Figure 2. RESET and SYNC logic and timing. ........................................................... 9
Figure 3. CS5180 connection diagram for using the internal voltage reference. ...... 10
Figure 4. CS5180 connection diagram for using an external voltage reference. ...... 11
Figure 5. Modulator Only Mode Data RTZ Format. .................................................. 12
Figure 6. Circuit to Reconstruct
Return-to-Zero (RTZ) Data from SDO/SDO into Original Modulator Bitstream. 12
Figure 7. Magnitude versus frequency spectrum of modulator
bitstream (MCLK = 25.6 MHz). .......................................................................... 12
Figure 8. Expanded view of the magnitude versus frequency spectrum of
modulator bitstream (MCLK = 25.6 MHz). ......................................................... 12
Figure 9. CS5180 Digital Filter Magnitude Response (MCLK = 25.6 MHz) .............. 13
Figure 10. CS5180 Digital Filter Phase Response
(MCLK = 25.6 MHz) ........................................................................................... 13
Figure 11. CS5180 System Connection Diagram ..................................................... 14
Figure 12. Single amplifier driving only AIN+, AIN- held at steady dc value ............. 21
Figure 13. Performance of amplifier of Figure 12 overdriving AIN+ input to the
CS5180 at 4 VPP ............................................................................................... 21
Figure 14. Performance of amplifier of Figure 12 with AIN+ driven at 2 VPP ........... 21
Figure 15. AC-coupled driver using two amplifiers. .................................................. 22
Figure 16. Performance of amplifier in Figure 15 ..................................................... 22
Figure 17. Three amplifier driver .............................................................................. 23
Figure 18. Performance of amplifier in Figure 17 ..................................................... 23
Figure 19. Four amplifier driver. ............................................................................... 24
Figure 20. Performance of amplifier in Figure 19 ..................................................... 24
Figure 21. Performance of amplifier in Figure 19 ..................................................... 24
Figure 22. CS5180 Differential Non-linearity plot.
(Data taken with repeating ramp) ....................................................................... 25
Figure 23. Histogram of DNL from Figure 22 ........................................................... 25
Figure 24. CS5180 Noise Histogram, > 60,000 samples. ........................................ 25
CS5180
3
CHARACTERISTICS/SPECIFICATIONS
CS5180
ANALOG CHARACTERISTICS (T
DGND = 0 V; MCLK = 25.6 MHz; VREFIN = VREFOUT; MODE = VD+; Analog source impedance = 301 Ohms
with 2200 pF to AGND; Full-Scale input sinewave at 22 kHz; Unless otherwise noted)
Parameter Symbol Min Typ Max Unit
Dynamic Performance
Dynamic Range (Note 1) DR 90 93 - dB
Total Harmonic Distortion THD -90 -95 - dB
Signal to (Noise + Distortion) SINAD 87 91 - dB
Spurious Free Dynamic Range SFDR 90 96 - dBc
Static Performance
Linearity Error (Note 2) INL - ±2 - LSB
Differential Non-Linearity (Note 2) DNL - - ±0.5 LSB
Full Scale Error (Note 6) - ±8 - LSB
Full Scale Drift with Internal Reference (Notes 2 and 5) - ±50 - ppm/°C
Offset Error (Note 6) - ±8 - LSB
Offset Drift (Note 2) - ±6.0 - µV/°C
Analog Input
Differential Input Voltage Range (Note 3) - 1.6 X
Common Mode Range CMR 1 - VREFIN
Input Capacitance - 4.0 - pF
Differential Input Impedance MCLK = 25.6 MHz - 500 - kΩ
Common Mode Rejection Ratio (Note 2) CMRR 50 - - dB
Common Mode Input Current MCLK = 25.6 MHz - ±100 ±200 µA
Reference Input
VREFIN 2.25 2.375 2.6 V
VREFIN Current (Note 4) - 1 ±200 µA
Reference Output
VREFOUT Voltage 2.25 2.375 2.5 V
VREFOUT Output Current - - ±500 µA
VREFOUT Impedance - 0.1 - Ω
= 0 °C to 70 °C; VA+ = 5 V ± 5%, VD+ = 3 V ± 10%; AGND =
A
-V
VREFIN
+0.25
pp
V
Notes: 1. Dynamic range is tested with a 22 kHz input signal 60 dB below full scale.
2. Specification guaranteed by design, characterization, and/or test.
3. Full scale fully-differential input span is nominally 1.6 X the VREFIN voltage. The peak negative
excursion of the signals at AIN+ or AIN- should not go below AGND for proper operation.
4. VREFIN current is less than 1 µA under normal operation, but can be as high as ±200 µA during
calibration.
5. Drift of the on-chip reference alone is typically about ±30 ppm/°C. If using an external reference, total
full scale drift will be that of the external reference ±20 ppm/°C, which is the typical drift of the X1.6 buffer.
6. Applies after self-calibration at final operating ambient temperature.
4
ANALOG CHARACTERISTICS (Continued)
Parameter Symbol Min Typ Max Unit
Power Supplies
CS5180
Power Supply Current (MODE = 1, PWDN
VA1+ , VA 2 + = 5 V
VD1+, VD2+ = 5 V
VD1+, VD2+ = 3 V
Power Supply Current (MODE = 1, PWDN
VA1+ , VA 2 + = 5 V
VD1+, VD2+ = 5 V
VD1+, VD2+ = 3 V
Power Supply Current (MODE = 0, PWDN
VA1+ , VA 2 + = 5 V
VD1+, VD2+ = 5 V
VD1+, VD2+ = 3 V
Power Supply Current (MODE = 0, PWDN
VA1+ , VA 2 + = 5 V
VD1+, VD2+ = 5 V
VD1+, VD2+ = 3 V
Power Supply Rejection (Note 9) PSRR - 55 - dB
Notes: 7. All outputs unloaded. All digital inputs except MCLK held static at VD+ or DGND.
8. Power consumption when PWDN
9. Measured with a 100 mV
=1) (Note7)
-
-
-
=0) (Notes7,8)
-
-
-
=1) (Note7)
-
-
-
=0) (Notes7,8)
= 0 applies only with no master clock applied (MCLK held high or low).
sine wave on the VA+ supplies at a frequency of 100 Hz.
pp
-
-
-
46
92
46
3.7
0.068
0.060
46
15
8.5
3.7
0.068
0.060
55
110
55
6
0.2
0.2
55
20
11.0
6
0.2
0.2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5
CS5180
DYNAMIC CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
Modulator Sampling Frequency - MCLK - Hz
Output Word Rate - MCLK/64 - Hz
Filter Characteristics (Note 2)
-3 dB Corner - MCLK/142.3804 - Hz
Passband Ripple - - ±0.05 dB
Stopband Frequency - MCLK/128 - Hz
Stopband Rejection 90 - - dB
Group Delay - 2370/MCLK - s
DIGITAL CHARACTERISTICS
(TA=0°Cto70°C;VA+=5V±5%;AGND=DGND=0V)
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage VD+ = 5 V
VD+ = 3 V
Low-Level Input Voltage VD+ = 5 V
VD+ = 3 V
High-Level Output Voltage (I
= -100 µA) VD+ = 5 V
O
VD+ = 3 V
Low-Level Output Voltage (I
= 100 µA) VD+ = 5 V
O
VD+ = 3 V
Input Leakage Current VD+ = 5 V
VD+ = 3 V
Input Capacitance C
V
IH
V
IH
V
IL
V
IL
V
OH
V
OH
V
OL
V
OL
I
in
I
in
in
4.0
2.0
-
-
4
2.7
-
-
-
-
-6-pF
±1
±1
-
-
-
-
-
-
-
-
-
-
0.8
0.8
-
-
0.4
0.3
±10
±10
V
V
V
V
V
V
V
V
µA
µA
6
CS5180
SWITCHING CHARACTERISTICS (T
= 0 °C to 70 °C; VA+ = 5 V ±5%, VD+ = 2.7 V to 5.5 V;
A
AGND = DGND = 0 V; MODE = VD+)
Parameter Symbol Min Typ Max Unit
Master Clock Frequency (Note 2) MCLK 0.512 25.6 26 MHz
Master Clock Duty Cycle 45 - 55 %
Rise Times (Notes 2, 10, and 11)
Any Digital Input, Except MCLK
MCLK
Any Digital Output
Fall Times (Notes 2, 10, and 11)
Any Digital Input, Except MCLK
MCLK
Any Digital Output
t
t
rise
fall
-
-
-
-
-
-
20
20
-
-
-
-
100
.2/MCLK
-
100
.2/MCLK
-
ns
s
ns
ns
s
ns
Calibration/Sync
RESET
RESET
rising to MCLK rising
rising recognized, to FSO falling
-3 -ns
- 988205/MCLK - s
SYNC rising to MCLK rising - 3 - ns
SYNC rising recognized to FSO falling - 5161/MCLK - s
PWDN
rising recognized to FSO falling
SYNC high time
RESET
low time
- 5168/MCLK - s
1/MCLK - - s
1/MCLK - - s
Serial Port Timing (Note 12)
SCLK frequency - MCLK/3 - Hz
SCLK high time t
SCLK low time t
FSO falling to SCLK rising t
SCLK falling to new data bit available t
SCLK rising to FSO rising t
1
2
3
4
5
-1/MCLK -s
-2/MCLK -s
-2/MCLK+2E-9 - s
-1.5 -ns
-1/MCLK-2E-9 - s
Notes: 10. Rise and Fall times are specified at 10% to 90% points on waveform.
11. RESET
12. Specifications applicable to complementary signals SCLK
, SYNC, and PWDN have Schmitt-trigger inputs.
FSO
t1t
2
SCLK
SDATA
t
3
t
4
XX
MSB MSB-1 LSB-1 LSB
and SDO.
Figure 1. Serial Port Timing (not to scale)
t
5
XX
7
CS5180
RECOMMENDED OPERATING CONDITIONS (AGND = DGND = 0 V)
Parameter Symbol Min Typ Max Unit
DC Power Supplies Digital
Analog
Analog Reference Voltage VREFIN 2.25 2.5 2.6 V
AGND to DGND Differential -100 0 100 mV
Operating Junction Temperature T
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Unit
DC Power Supplies Ground
Digital
Analog
Input Current, Any pin except Supplies I
Output Current I
Power Dissipation (Total) - 1000 mW
Analog Input Voltage and VREFIN voltage V
Digital Input Voltage V
Ambient Operating Temperature T
Storage Temperature T
VD+
VA+
j
AGND/DGND
VD+
VA+
in
out
INA
IND
A
stg
2.7
4.75
- - 120 °C
3
5
-0.3
-0.3
-0.3
-±10mA
-±25mA
-0.3 (VA+) + 0.3 V
-0.3 (VD+) + 0.3 V
070°C
-65 150 °C
5.5
5.25
0.3
6.0
6.0
V
V
V
V
V
WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not
guaranteed at these extremes.
8
CS5180
GENERAL DESCRIPTION
The CS5180 is a monolithic CMOS 16-bit A/D
converter designed to operate in a continuous mode
after being reset.
The CS5180 can operate in a modulator-only mode
in which the unfiltered bit stream from the modulator is the data output from the device.
THEORY OF OPERATION
The front page of this data sheet illustrates the
block diagram of the CS5180.
Converter Initialization: Calibration and Synchronization
The CS5180 does not have an internal power-on reset circuit. Therefore when power is first applied to
the device the RESET
power is established and the voltage reference has
stabilized. This resets the converter’s logic to a
known state. When power is fully established the
converter will perform a self-calibration, starting
with the first MCLK rising edge after RESET
high. The converter will use 988,205 MCLK cycles
to complete the calibration and to allow the digital
filter to fully settle, after which, it will output fullysettled conversion words. The converter will then
continue to output conversion words at an output
pin should be held low until
goes
word rate equal to MCLK/64. Figure 2 illustrates
the RESET
and SYNC logic and timing for the con-
verter.
The CS5180 is designed to perform conversions
continuously with an output rate that is equivalent
to MCLK/64. The conversions are performed and
the serial port is updated independent of external
controls. The converter is designed to measure differential bipolar input signals, and unipolar signals,
with a common mode voltage of between 1.0 V and
VREF + 0.25 V. Calibration is performed when the
RESET
signal to the device is released. If RESET
is properly framed to MCLK, the converter can be
synchronized to a specific MCLK cycle at the system level.
The SYNC signal can also be used to synchronize
multiple converters in a system. When SYNC is
used, the converter does not perform calibration.
The SYNC signal is recognized on the first rising
edge of MCLK after SYNC goes high. SYNC
aligns the output conversion to occur every 64
MCLK clock cycles after the SYNC signal is recognized and the filter is settled. After the SYNC is
initiated by going high, the converter will wait
5,161 MCLK cycles for the digital filter to settle
before putting out a fully-settled conversion word.
To synchronize multiple converters in a system, the
RESET
MCLK
SYNC
CS5180
D
CLK
D
CLK
Figure 2. RESET and SYNC logic and timing.
Q
Q RESET
QSYNC
MCLK
RESET
FSO
988205 MCLK Cycles
MCLK
SYNC
FSO
5161 MCLK Cycles
9
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