Cirrus Logic CS4955-CQ, CS4954-CQ Datasheet
NTSC/PAL Digital Video Encoder
CS4954
CS4955
Features
l Six DACs provid ing si multan eo us composi te,
S-video, and RGB or Component YUV
outputs
l Programmable DAC ou tput currents for low
imped-ance (37.5 Ω) and high impedance
(150 Ω) loads.
l Multi-standard support for NTSC-M, NTSC-
JAPAN, PAL (B, D, G, H, I, M, N,
Combination N)
l ITU R.BT656 input mode supporting
EAV/SAV codes and CC IR601 Master /Slave
input modes
l Programmable HS YNC and VSYNC timing
l Multistandard Teletext (Europe, NABTS,
WST) support
l VBI encoding support
l Wide-Screen Signaling (WSS) support, EIA-J
CPX1204
l NTSC closed caption encoder with interrupt
l CS4955 supports Macrovision copy
protection Version 7
l Host interface configurable
for parallel or I2C
compatible operation
l On-chip voltage reference
generator
l +3.3 V or +5 V operation,
CMOS, low-power modes,
tri-state DACs
CLK
SCL
SDA
PDAT[7:0]
RD
WR
ADDR
XTAL_IN
XTAL_OUT
TTXDAT
TTXRQ
VD[7:0]
HSYNC
VSYNC
FIELD
INT
RESET
8
8
Description
The CS4954/5 provides full conversion from digital video
formats YCbCr or YUV into NT SC a nd PA L Com posite ,
Y/C (S-video) and RGB, or YUV analog video. Input formats can be 27 MHz 8-bit YUV, 8-bit YCbCr, or ITU
R.BT656 with support for EAV/SAV codes. Video output
can be formatted to be compatible with NTSC-M, NTSCJ, PAL-B,D,G,H,I,M,N, and Combination N systems.
Closed Caption is supported in NTSC. Teletext is supported for NTSC and PAL.
Six 10-bit DACs provide two channels for an S-Video
output port, one or two composite video outputs, and
three RGB or YUV outputs. Two-times oversampling reduces the output filter requi rements and guarante es no
DAC-related modulation components within the specified bandwidth of any of the supported video standards.
Parallel or high-speed I
provided for flexibility in system design. The parallel interface
doubles as a general purpose I/O port when th e CS4954/5 is
2
in I
C mode to help conserve valuable board area.
ORDERING INFORMATION
CS4954-CQ 48-pin TQFP
CS4955-CQ 48-pin TQFP
I2C Interface
Control
Host
Parallel
Interface
Color Sub-carrier Synthesizer
Teletext
Encoder
Video Formatter
Video Timing
Generator
Registers
YCbCr to RBG
Color Space
Converter
DGND
2
VAA
Output
Interpolate
Chroma Amplifier
Chroma Modulate
Chroma Interpolate
U,V
Y
Luma Interpolate
Luma Amplifier
Sync Insert
RGB
C compatible control interfaces are
Burst Ins e rt
LPF
Y
LPF
Y
RGB
Σ
10-Bit
DAC
10-Bit
DAC
10-Bit
DAC
10-Bit
DAC
10-Bit
DAC
10-Bit
DAC
Voltage
Reference
Current
Reference
TEST
C
CVBS
Y
R
G
B
VREF
ISET
Preliminary Product Information
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 1999
(All Rights Reserved)
DS278PP4
APR ‘99
1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................5
AC & DC PARAMETRIC SPECIFICATIONS ................................................ ...... ..... ...... .....5
RECOMMENDED OPERATING CONDITIONS .....................................................................5
DC CHARACTERISTICS ....................................................................................................5
AC CHARACTERISTIC .......................................................................................................7
TIMING CHARACTERISTICS .............................................................................................8
2. ADDITIONAL CS4954/5 FEATURES ...............................................................................10
3. CS4954 INTRODUCTION .................................................................................................10
4. FUNCTIONAL DESCRIPTION ................... ....................................... ...... ..... ...... ..... .........10
4.1. Video Timing Generator .........................................................................................10
4.2. Video Input Formatter .............................................................................................11
4.3. Color Subcarrier Synthesizer ..................................................................................11
4.4. Chroma Path ..........................................................................................................11
4.5. Luma Path ..............................................................................................................12
4.6. RGB Path and Component YUV Path ....................................................................12
4.7. Digital to Analog Converters ...................................................................................12
4.8. Voltage Reference ..................................................................................................13
4.9. Current Reference ....................................... ....................................... ...... ..............13
4.10. Host Interface .........................................................................................................13
4.11. Closed Caption Services ........................................................................................13
4.12. Teletext Services ....................................................................................................14
4.13. Wide-Screen Signaling Support and CGMS ...................... ...... ...... ..... ...... ..............14
4.14. VBI Encoding ............................................................................................ ..... .........14
4.15. Control Registers ....................................................................................................14
4.16. Testability ...............................................................................................................14
5. OPERATIONAL DESCRIPTION .......................................................................................14
5.1. Reset Hierarchy ......................................................................................................14
5.2. Video Timing ...........................................................................................................15
5.2.1. Slave Mode Input Interface ..........................................................................15
5.2.2. Master Mode Input Interface ........................................................................15
5.2.3. Vertical Timing ............................................. ...... ..... ...... ...............................16
5.2.4. Horizontal Timing .........................................................................................16
5.2.5. NTSC Interlaced ..........................................................................................16
5.2.6. PAL Interlaced .............................................................................................16
5.2.7. Progressive Scan ......................................................................................... 17
5.2.8. NTSC Progressive Scan ..............................................................................17
5.2.9. PAL Progressive Scan .................................................................................18
5.3. ITU-R.BT656 ..........................................................................................................18
5.4. Digital Video Input Modes .......................................................................................21
5.5. Multi-standard Output Format Modes .....................................................................21
5.6. Subcarrier Generation ............................................................................................21
5.7. Subcarrier Compensation .......................................................................................21
5.8. Closed Caption Insertion ........................................................................................22
5.9. Programmable H-sync and V-sync .........................................................................22
5.10. Wide Screen Signaling (WSS) and CGMS .............................................................23
CS4954 CS4955
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product info rmation describes products which are i n p r od ucti on, b ut for which full characterizat i on da t a i s not yet available. Advance produ ct i nf or mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” withou t warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document i s the propert y of Cirru s Logic, Inc. and implie s no licen se under patent s, copyri ghts, trademarks, or tr ade secrets. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pri or wri tt en consen t of Ci rrus Logic, Inc. Items from any Cirrus Logic websi t e or di sk may be pri nted for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS278PP4
CS4954 CS4955
5.11. Teletext Support .....................................................................................................23
5.12. Color Bar Generator ...............................................................................................25
5.13. VBI encoding .............................. ...... ..... ...... ...... ....................................... ..... .........25
5.14. Super White/Super Black support ........................................... ...... ..... ....................26
5.15. Interrupts ................................................................................................................26
5.16. General Purpose I/O Port .......................................................................................26
6. FILTER RESPONSES ......................................................................................................27
7. ANALOG ..........................................................................................................................30
7.1. Analog Timing ........................................................................................................30
7.2. VREF ...................................................................................................................... 30
7.3. ISET .......................................................................................................................30
7.4. DACs ...................................................................................................................... 30
7.4.1. Luminance DAC ..........................................................................................30
7.4.2. Chrominance DAC ......................................................................................30
7.4.3. CVBS DAC ..................................................................................................31
7.4.4. Red DAC .....................................................................................................31
7.4.5. Green DAC ..................................................................................................31
8. PROGRAMMING .............................................................................................................. 32
9. BOARD DESIGN AND LAYOUT CONSIDERATIONS ....................................................50
10. PIN DESCRIPTION ............................. ...... ....................................... ...... ..... ....................53
11. PACKAGE DRAWING ......................................................................................................55
7.4.6. Blue DAC .....................................................................................................31
8.1. Host Control Interface ............................................................................................32
8.2. Register Description .......................................................... ...... ...............................34
9.1. Power and Ground Planes .....................................................................................50
9.2. Power Supply Decoupling ......................................................................................50
9.3. Digital Interconnect ................................................................................................50
9.4. Analog Interconnect ...............................................................................................50
9.5. Analog Output Protection .......................................................................................51
9.6. ESD Protection .......................................................................................................51
9.7. External DAC Output Filter .....................................................................................51
2
8.1.1. I
8.1.2. 8-bit Parallel Interface .................................................................................33
8.2.1. Control Registers .........................................................................................34
C Interface ................................................................................................32
DS278PP4 3
TABLE OF FIGURES
1. Video Pixel Data and Control Port Timing .........................................................................7
2
2. I
C Host Port Timing ..........................................................................................................8
3. Reset Timing ......................................................................................................................9
4. ITU R.BT601 Input Slave Mode Horizontal Timing ..........................................................15
5. ITU R.BT601 Input Master Mode Horizontal Timing ........................................................15
6. Vertical Timing ............ ....... ...... ....... ...... ....... ...... ....... ...... ...... ....................................... ....17
7. NTSC Video Interlaced Timing ........................................................................................18
8. PAL Video Interlaced Timing ...........................................................................................19
9. NTSC Video Non-Interlaced Progressive Scan Timing ...................................................20
10. PAL Video Non-Interlaced Progressive Scan Timing ......................................................20
11. CCIR656 Input Mode Timing ...........................................................................................21
12. Teletext Timing (Pulsation Mode) ....................................................................................24
13. Teletext Timing (Window Mode) ......................................................................................24
14. 1.3 Mhz Chrominance low-pass filter transfer characteristic ...........................................27
15. 1.3 Mhz Chrominance low-pass filter transfer characterstic (passband) .........................27
16. 650 kHz Chrominance low-pass filter transfer characteristic ...........................................27
17. 650 kHz Chrominance low-pass filter transfer characteristic (passband) ........................27
18. Chrominance output interpolation filter transfer characteristic (passband) ......................28
19. Luminance interpolation filter transfer characteristic .......................................................28
20. Luminance interpolation filter transfer characterstic (passband) .....................................28
21. Chrominance interpolation filter transfer characteristic for RGB datapath .......................28
22. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) .............29
23. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) .............29
24. Chroma Interpolator for RGB Datapath when rgb_bw=0 -3 dB .......................................29
25. Chroma Interpolator for RGB Datapath when rgb_bw=0 (Full Scale) ..............................29
2
26. I
C Protocol .....................................................................................................................32
27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle ........................................33
28. 8-bit Parallel Host Port Timing: Address Read Cycle ......................................................33
29. 8-bit Parallel Host Port Timing: Address Write Cycle .......................................................34
30. External Low Pass Filter C
31. Typical Connection Diagram ............................................................................................52
should be chosen so that C1 = C2 + C
2
CS4954 CS4955
......................... 51
cable
4 DS278PP4
1. CHARACTERISTICS AND SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
CS4954 CS4955
AC & DC PARAMETRIC SPECIFICATIONS
Parameter Symbol Min Max Units
Power Supply VAA/VDD -0.3 6.0 V
Input Current Per Pin (Except Supply Pins) -10 10 mA
Output Current Per Pin (Except Supply Pins) -50 +50 mA
Analog Input Voltage -0.3 VAA + 0.3 V
Digital Input Voltage -0.3 VDD + 0.3 V
Ambient Temperature Power Applied -55 + 125 °C
Storage Temperature -65 + 150 °C
WARNING: Operating beyond these limits can result in permanent damage to the device. Normal operation is not
guaranteed at these extremes.
(AGND,DGND = 0 V, all voltages with respect to 0V
RECOMMENDED OPERATING CONDITIONS (AGND,DGND = 0 V, all voltages with respect to 0 V.)
Parameter Symbol Min Typ Max Units
Power Supplies: Digital Analo g VAA/VDD 3.15
4.75
Operating Ambient Temperature TA 0 + 25 + 70 °C
Note: Operation outside the ranges is not recommended.
3.3
5.0
3.45
5.25
V
)
DC CHARACTERISTICS (T
Parameter Symbol Min Typ Max Units
Digital Inputs
High level Input Voltage
V [7:0], PDAT [7:0], Hsync/Vsync/Field/CLKIN
2
High Level Input Voltage I
Low level Input Voltage All Inputs - -0.3 - 0.8 V
Input Leakage Current - -10 - +10
Digital Outputs
High Level Output Voltage lo = -4 mA VOH 2.4 - VDD V
Low level Output Voltage lo = 4 mA VOL - - 0.4 V
Low Level Output Voltage SDA pin only, lo = 6mA VOL - - 0.4 V
Output Leakage Current High -Z Digital Outputs - -10 - + 10
C
= 25° C; VAA, VDD = 5 V; GNDA, GNDD = 0 V.)
A
VIH 2.2 - VDD+0.3 V
VIH 0.7 VDD - - V
µ
A
µ
A
DS278PP4 5
CS4954 CS4955
DC CHARACTERISTICS (Continued)
Parameter Symbol Min Typ Max Units
Analog Outputs
Full Scale Output Current CVBS/Y/C/R/G/B (Notes 1, 2, 3) IO 32.9 34.7 36.5 mA
Full Scale Output Current CVBS/Y/C/R/G/B (Notes 1, 2, 4) IO 8.22 8.68 9.13 mA
LSB Current CVBS/Y/C/R/G/B (Notes 1, 2, 3) IB 32.2 33.9 35.7
LSB Current CVBS/Y/C/R/G/B (Notes 1, 2, 4) IB 8.04 8.48 8.92
DAC-to DAC Matching (Note 1) MAT - 2 - %
Output Compliance (Note 1) VOC 0 - + 1.4 V
Output Impedance (Note 1) ROUT - 15 - k
Output Capacitance (Note 1) COUT - - 30 pF
DAC Output Delay (Note 1) ODEL - 4 12 ns
DAC Rise/Fall Time (Note 1, 5) TRF - 2.5 5 ns
Voltage Reference
Reference Voltage Output VOV 1.170 1.232 1.294 V
Reference Input Current (Note 1) UVC - - 10 uA
Power Supply
Supply Voltage VAA, VDD 3.15
4.75
Digital Supply Current IAA1 - 70 - mA
Analog Supply Low-Z (Note 6) IAA2 - 100 - mA
Analog Supply High-Z (Note 7) IAA3 - 60 - mA
Power Supply Rejection Ratio PSRR 0.02 0.05 %/%
3.3
5.0
3.45
5.25
Static Performance
DAC Resolution (Note 1) - - 10 Bits
Differential Non-Linearity (Note 1) DNL -1 +
Integral Non-Linearity (Note 1) INL - 2 +
0.5 + 1 LSB
1+ 2LSB
Dynamic Performance
Differential Gain (Note 1) DG - 2 5 %
Differential Phase (Note 1) DP - +
Hue Accuracy (Note 1) HA - - 2 °
Signal to Noise Ratio SNR 70 - - dB
Saturation Accuracy (Note 1) SAT - 1 2 %
0. 5 + 2 °
µ
µ
V
A
A
Ω
Notes: 1. Values are by characterization only
2. Output current levels with ISET = 4 KΩ , VREF = 1.232 V.
3. DACs are set to low impedance mode
4. DACs are set to high impedance mode
5. Times for black-to-white-level and white-to-black-level transitions.
6. Low-Z - 3 dacs on
7. High-Z - 6 dacs on
6 DS278PP4
CS4954 CS4955
AC CHARACTERISTIC
Parameter Symbol Min Typ Max Units
Pixel Input and Control Port (Figure 1)
Clock Pulse High Time Tch 14.82 18.52 22.58 ns
Clock Pulse Low Time Tcl 14.82 18.52 22.58 ns
Clock to Data Set-up Time Tisu 6 - - ns
Clock to Data Hold Time Tih 0 - - ns
Clock to Data Output Delay Toa - - 17 ns
CLK
T
isu
T
chTcl
V[7:0]
HSYNC
HSYNC
/VSYNC
(Inputs)
/VSYNC
CB/FIELD/INT
(Outputs)
T
ih
T
oa
Figure 1. Video Pixel Data and Control Port Timing
DS278PP4 7
CS4954 CS4955
TIMING CHARACTERISTICS
Parameter Symbol Min Typ Max Units
I2C Host Port Timing (Figure 2)
SCL Frequency Fclk 100 1000 KHz
Clock Pulse High Time Tsph 0.1
Clock Pulse Low Time Tspl 0.7
Hold Time (Start Cond.) Tsh 100 ns
Setup Time (Start Cond.) Tssu 100 ns
Data Setup Time Tsds 50
Rise Time Tsr 1
Fall Time Tsf 0.3
Setup Time (Stop Cond.) Tss 100 ns
Bus Free Time Tbuf 100 ns
Data H old Time Tdh 0 ns
SCL Low to Data Out Valid Tvdo 600 ns
µ
µ
n
µ
µ
s
s
s
s
s
SDA
SCL
T
dh
vdo
ds
T
sh
T
ssu
T
ss
T
sh
T
sph T
T
T
si
T
bu
T
sr
T
spi
Figure 2. I2C Host Port Timing
8 DS278PP4
CS4954 CS4955
TIMING CHARACTERISTICS(Continued)
Parallel Host Port Timing (Figure 27, 28, 29)
Read Cycle Time Trd 60 - - ns
Read Pulse Width Trpw 30 - - ns
Address Setup Time Tas 3 - - ns
Read Address Hold Time Trah 10 - - ns
Read Data Access Time Trda - - 40 ns
Read Data Hold Time Trdh 10 - 50 ns
Write Recovery Time Twr 60 - - ns
Write Pulse Width Twpw 40 - - ns
Write Data Setup Time Twds 8 - - ns
Write Data Hold Time Twdh 3 - - ns
Write-Read/Read-Write Recovery Time Trec 50 - - ns
Address from Write Hold Time Twac 0 - - ns
Reset Timing (Figure 3)
Reset Pulse Width Tres 100 ns
RESET*
T
res
Figure 3. Reset Timing
DS278PP4 9
CS4954 CS4955
2. ADDITIONAL CS4954/5 FEATURES
• Five programmable DAC output combinations,
including YUV and second composite
• Optional progressive scan @ MPEG2 field rates
• Stable color subcarrier for MPEG2 systems
• General purpose input and output pins
• Individual DAC power-down capability
• On-chip color bar generator
• Supports RS170A and ITU R.BT601 composite output timing
• HSYNC and VSYNC output in ITU R.BT656
mode
• Teletext encoding selectable on two composite
and S-video signals
• Programmable saturation, SCH Phase, hue,
brightness and contrast
• Device power-down capability
• Super White and Super Black support
3. CS4954 INTRODUCTION
The CS4954/5 is a complete multi-standard digital
video encoder implemented in current CMOS technology. The device can operate at 5 V as well as at
3.3 V. ITU R.BT601- or ITU R.BT656-compliant
digital video input is converted into NTSC-M,
NTSC-J, PAL-B, PAL-D, PAL-G, PAL-H, PAL-I,
PAL-M, PAL-N, or PAL-N Argentina-compatible
analog video. The CS4954/5 is designed to connect, without glue logic, to MPEG1 and MPEG2
digital video decoders.
Two 10-bit DAC outputs provide high quality SVideo analog output while another 10-bit DAC simultaneously generates composite analog video. In
addition, there are three more DACs to provide simultaneous analog RGB or analog YUV outputs.
The CS4954/5 will accept 8-bit YCbCr or 8-bit
YUV input data.
The CS4954/5 is completely configured and controlled via an 8-bit host interface port or an I2C
compatible serial interface. This host port provide s
access and control of all CS4954/5 options and features, such as closed caption insertion, interrupts,
etc.
In order to lower overall system costs, the
CS4954/5 provides an internal voltage reference
that eliminates the requirement for a n external, discrete, three-pin voltage reference.
In ISO MPEG-2 system configurations, the
CS4954/5 can be augmented with a common colorburst crystal to provide a stable color subcarrier
given an unstable 27 MHz clock input. The use of
the crystal is optional, but the facility to connect
one is provided for MPEG-2 environments in
which the system clock frequency variability is too
wide for accurate color sub-carrier generation.
4. FUNCTIONAL DESCRIPTION
In the following subsections, the functions of the
CS4954/5 will be described. The descriptions refer
to the device elements shown in the block diagram
on the cover page.
4.1. Video Timing Generator
All timing generation is accomplished via a
27 MHz input applied to the CLK pin. The
CS4954/5 can also accept a signal from an optional
color burst crystal on the XTAL_IN &
XTAL_OUT pins. See the section, Color Subcarrier Synthesizer, for further details.
The Video Timing Generator is responsible for orchestrating most of the other modules in the device.
It operates in harmony with external sync input
timing, or it can provide external sync timing outputs. It automatically disables color burst on appropriate scan lines and automatically generates
serration and equalization pulses on appropriate
scan lines.
10 DS278PP4
CS4954 CS4955
The CS4954/5 is designed to function as a video
timing master or video timi ng slave. In both Master
and Slave Modes, all timing is sampled and asserted with the rising edge of the CLK pin.
In most cases, the CS4954/5 will serve as the video
timing master. HSYNC, VSYNC, and FIELD are
configured as outputs in Master Mode. HSYNC or
FIELD can also be defined as a composite blanking
output signal in Master Mode. In Master Mode, the
timing of HSYNC, VSYNC, FIELD and Composite Blank (CB) signals is programmable. Exact horizontal and vertical display timing is addressed in
the Operational Description section.
In Slave Mode, HSYNC and VSYNC are typically
configured as input pins and are used to initialize
independent vertical and horizontal timing generators upon their respective falling edges. HSYNC
and VSYNC timing must conform to the ITUR BT.601 specifications.
CLK input (27 MHz). Color burst accuracy and
stability are limited by the accuracy of the 27 MHz
input. If the frequency varies, then the color burst
frequency will also vary accordingly.
For environments in which the CLK input varies or
jitters unacceptably, a local crystal frequency reference can be used on the XTAL_IN and
XTAL_OUT pins. In this instance, the input CLK is
continuously compared with the external crystal reference input and the internal timing of the CS4954/5
is automatically adjusted so that the color burst frequency remains within tolerance.
Controls are provided for phase adjustment of the
burst to permit color adjustment and phase compensation. Chroma hue control is provided by the
CS4954/5 via a 10-bit Hue Control Register
(HUE_LSB and H_MSB). Burst amplitude control
is also made available to the host via the 8-bit burst
amplitude register (SC_AMP).
The CS4954/5 also provides a ITU R.BT656 Slave
Mode in which the video input stream contains
EAV and SAV codes. In this case, proper HSYNC
and VSYNC timing are extracted automatically
without any inputs other than the V [7:0]. ITU
R.BT656 input data is sampled with the leading
edge of CLK.
In addition, it is also possible to output HSYNC
and VSYNC signals during CCIR-656 Slave
Mode.
4.2. Video Input Formatter
The Video Input Formatter translates YCbCr input
data into YUV information, when necessary, and
splits the luma and chroma information for filtering, scaling, and modulation.
4.3. Color Subcarrier Synthesizer
The subcarrier synthesizer is a digital frequency
synthesizer that produces the appropriate subcarrier frequency for NTSC or PAL. The CS4954/5
generates the color burst frequency based on the
4.4. Chroma Path
The Video Input Formatter delivers 4:2:2 YUV
outputs into separate chroma and luma data paths.
The chroma path will be discussed here.
The chroma output of the Video Input Formatter is
directed to a chroma low-pass 19-tap FIR filter.
The filter bandwidth is selected (or the filter can be
bypassed) via the CONTROL_1 Register. The
passband of the filter is either 650 KHz or 1.3 MHz
and the passband ripple is less than or equal to
0.05 dB. The stopband for the 1.3 MHz selection
begins at 3 MHz with an attenuation of greater than
35 dB. The stopband for the 650 KHz selection begins around 1.1 MHz with an attenuation of greater
than 20 dB.
The output of the chroma low-pass filter is connected to the chroma interpolation filter in which upsampling from 4:2:2 to 4:4:4 is accomplished.
Following the interpolation filter, the U and V
chroma signals pass through two independent variable gain amplifiers in which the chroma amplitude
DS278PP4 11
CS4954 CS4955
can be varied via the U_AMP and V_AMP 8-bit
host addressable registers.
The U and V chroma signals are fed to a quadrature
modulator in which they are combined with the
output from the subcarrier synthesizer to produce
the proper modulated chrominance signal.
The chroma then is interpolated by a factor of two
in order to operate the output DACs at twice the
pixel rate. The interpolated filters enable running
the DACs at twice the pixel rate and this helps reduce the sinx/x roll-off for higher frequencies and
reduces the complexity of the external analog low
pass filters.
4.5. Luma Path
Along with the chroma output path, the CS4954/5
Video Input Formatter initiates a parallel luma data
path by directing the luma data to a digital delay
line. The delay line is built as a digital FIFO in
which the depth of the FIFO replicates the clock
period delay associated with the more complex
chroma path. Brightness adjustment is also provided via the 8-bit BRIGHTNESS_OFFSET Register.
Following the luma delay, the data is passed
through an interpolation filter that has a programmable bandwidth, followed by a variable gain amplifier in which the luma DC values are mod ifi abl e
via the Y_AMP Register.
three pixel clocks. This variable delay is useful to
offset different propagation delays of the luma
baseband and modulated chroma signals. This adjustable luma delay is available only on the
CVBS_1 output.
4.6. RGB Path and Component YUV Path
The RGB datapath has the same latency as the luma
and chroma path. Therefore all six simultaneous
analog outputs are synchronized. The 4:2:2 YCbCr
data is first interpolated to 4:4:4 and then interpolated to 27 MHz. The color space conversion is performed at 27 MHz. The coefficients for the color
space conversion conform to the ITU R.BT601
specifications.
After color space conversion, the amplitude of each
component can be independently adjusted via the
R_AMP, G_AMP, and B_AMP 8-bit host addressable registers. A synchronization signal can be added to either one, two or all of the RGB signals. The
synchronization signal conforms to NTSC or PAL
specifications.
Some applications (e.g., projection TVs) require
analog component YUV signals. The chip provides
a programmable mode that outputs component
YUV data. Sync can be added to the luminance signal. Independent gain adjustment of the three components is provided as well.
The output of the luma amplifier connects to the
sync insertion block. Sync insertion is accomplished by multiplexing, into the luma data path,
the different sync DC values at the appropriate
times. The digital sync generator takes horizontal
sync and vertical sync timing signals and generates
the appropriate composite sync timing (including
vertical equalization and serration pulses), blanking information, and burst flag. The sync edge rates
conform to RS-170A or ITU R.BT601 and ITU
R.BT470 specifications.
It is also possible to delay the luminance signal,
with respect to the chrominance signal, by up to
12 DS278PP4
4.7. Digital to Analog Converters
The CS4954/5 provides six discrete 27 MHz DACs
for analog video. The default configuration is one
10-bit DAC for S-video chrominance, one 10-bit
DAC for S-Video luminance, one 10-bit DAC for
composite output, and three 10-bit DACs for RGB
outputs. All six DACs are designed for driving either low-impedance loads (double terminated
75 Ω) or high-impedance loads (double terminated
300 Ω). There are five different DAC configurations to choose from (see Table 1, below).
The DACs can be put into tri-state mode via hostaddressable control register bits. Each of the six
CS4954 CS4955
DAC Pin # Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
Y 48 Y Y Y CVBS_2 CVBS_2
C47CCC- -
CVBS 44 CVBS_1 CVBS_1 CVBS_1 CVBS_1 CVBS_1
R 39 R Cr (V) - R Cr (V)
G 40 G Y CVBS_2 G Y
B43BCb (U)- BCb (U)
Table 1. DAC configuration Modes
DACs has its own associated DAC enable bit. In
the Disable Mode, the 10-bit DACs source (or sink)
zero current.
When running the DACs with a low-impedance
load, a minimum of three DACs must be powered
down. When running the DACs with a high-impedance load, all the DACs can be enabled simultaneously.
For lower power standby scenarios, the CS4954/5
also provides power shut-off control for the DACs.
Each DAC has an associated DAC shut-off bit.
4.8. Voltage Reference
The CS4954/5 is equipped with an on-board voltage reference generator (1.232 V) that is used by
the DACs. The internal reference voltage is accurate enough to guarantee a maximum of 3% overall
gain error on the analog outputs. However, it is
possible to override the internal reference voltage
by applying an external voltage source to the VREF
pin.
output current modes are software selectable
through a register bit.
4.10. Host Interface
The CS4954/5 provides a parallel 8-bit data interface for overall configuration and control. The host
interface uses active-low read and write strobes,
along with an active-low address enable signal, to
provide microprocessor-compatible read and write
cycles. Indirect host addressing to the CS4954/5 internal registers is accomplished via an internal a ddress register that is uniquely accessible via bus
write cycles in which the host address enable signal
is asserted.
The CS4954/5 also provides an I2C-compatible serial interface for device configuration and control.
This port can operate in standard (100Kb/sec) or
fast (400 Kb/sec) modes. When in I2C mode, the
parallel data interface pins, PDAT [7:0], can be
used as a general purpose I/O port controlled by the
I2C interface.
4.9. Current Reference
The DAC output current-per-bit is derived in the
current reference block. T he current step is specified by the size of resistor placed between the ISET
current reference pin and electrical ground.
4.11. Closed Caption Services
The CS4954/5 supports the generation of NTSC
Closed Caption services. Line 21 and Line 284 captioning can be generated and enabled independently via a set of control registers. When enabled,
clock run-in, start bit, and data bytes are automati-
A 4 kΩ resistor needs to be connected between
ISET pin and GNDA. The DAC output currents are
optimized to either drive a doubly terminated load
of 75 Ω (low impedence mode) or a double termi-
cally inserted at the appropriate video lines. A convenient interrupt protocol simplifies the software
interface between the host processor and the
CS4954/5.
nated load of 300 Ω (high impedence mode). The 2
DS278PP4 13
CS4954 CS4955
4.12. Teletext Services
The CS4954/5 encodes the most common teletext
formats, such as European Teletext, World Standard Teletext (PAL and NTSC), and North American Teletext (NABTS).
Teletext data can be inserted in any of the TV lines
(blanking lines as well as active lines). In addition
the blanking lines can be individually allocated for
Teletext instantiation.
The input timing for teletext data is user programmable. See the section Teletext Services for further
details.
Teletext data can be independently inserted on either one or all of the CVBS_1, CVBS_2, or S-video
signals.
4.13. Wide-Screen Signaling Support and
CGMS
Insertion of wide-screen signal encoding for PAL
and NTSC standards is supported and CGMS
(Copy Generation Management System) for NTSC
in Japan. Wide-screen signals are inserted in lines
23 and 336 for PAL, and lines 20 and 283 for
NTSC.
4.14. VBI Encoding
This chip supports the transmission of control signals in the vertical blanking t ime interval according
to SMPTE RP 188 recommendations. VBI encoded
data can be independently inserted into either or all
of CVBS_1, CVBS_2 or S-video signals.
4.15. Control Registers
The control and configuration of the CS4954/5 is
accomplished primarily through the control register block. All of the control registers are uniquely
addressable via the internal address register. The
control register bits are initialized during device
RESET.
See the Programming section of this data sheet for
the individual register bit allocations, bit operational descriptions, and initialization states.
4.16. Testability
The digital circuits are completely scanned by an
internal scan chain, thus providing close to 100%
fault coverage.
5. OPERATIONAL DESCRIPTION
5.1. Reset Hierarchy
The CS4954/5 is equipped with an active low asynchronous reset input pin, RESET. RESET is used to
initialize the internal registe rs and the internal st ate
machines for subsequent default operation. See the
electrical and timing specification section of this
data sheet for specific CS4954/5 device RESET
and power-on signal timing requirements and restrictions.
While the RESET pin is held low, the host interface
in the CS4954/5 is disabled and will not respond to
host-initiated bus cycles. All outputs are valid after
a time period following RESET pin low.
A device RESET initializes the CS4954/5 internal
registers to their default values as described by Table 9, Control Registers. In the default state, the
CS4954/5 video DACs are disabled and the device
is internally configured to provide blue field video
data to the DACs (any input data present on the
V [7:0] pins is ignored at this time). Otherwise, the
CS4954/5 registers are configured for NTSC-M
ITU R.BT601 output operation. At a minimum, the
DAC Registers (0x04 and 0x05) must be written (to
enable the DACs) and the IN_MODE bit of the
CONTROL_0 Register (0x01) must be set (to enable ITU R.BT601 data input on V [7:0]) for the
CS4954/5 to become operational after RESET.
14 DS278PP4
NTSC 27MHz Clock Count
PAL 27MHz Clock Count
CLK
HSYNC (input)
V[7:0]
(SYNC_DLY=0)
1682
1702
Y
• • •
CS4954 CS4955
168616851684
1683
1703
Cr
active pixel
#720
17051704
Y Cb Y Cr Y
1706
• • •
• • •
1716
1728
1
23 128
1
23 128
horizontal blanking
• • •
• • •
129
129
• • •
• • •
244 245
264 265
active pixel#1active pixel
246 247
266 267
248
268
#2
V[7:0]
(SYNC_DLY=1)
Y
Cb
active pixel
#719
Cr
Y
active pixel
#720
Figure 4. ITU R.BT601 Input Slave Mode Horizontal Tim ing
5.2. Video Timing
5.2.1. Slave Mode Input Interface
In Slave Mode, the CS4954/5 receives signals on
VSYNC and HSYNC as inputs. Slave Mode is the
default following RESET and is changed to Master
Mode via a control register bit (CONTROL_0 [4]).
The CS4954/5 is limited to ITU R.BT601 horizontal and vertical input timing. All clocking in the
CS4954/5 is generated from the CLK pin. In Slave
Mode, the Sync Generator uses externally provided
horizontal and vertical sync signals to synchronize
the internal timing of the CS4954/5. Video data that
is sent to the CS4954/5 must be synchronized to the
horizontal and vertical sync signals. Figure 4 illustrates horizontal timing for ITU R.BT601 input in
Slave Mode. Note that the CS4954/5 expects to receive the first active pixel data on clock cycle 245
(NTSC) when CONTROL_2 Register (0x02) bit
Cb
Y
Cr
horizontal blanking active pixel#1active pixel
#2
SYNC_DLY = 0. When SYNC_DLY = 1, it expects
the first active pixel data on clock cycle 246 (NTSC).
5.2.2. Master Mode Input Interface
The CS4954/5 defaults to Slave Mode following
RESET high but can be switched into Master Mode
via the MSTR bit in the CONTROL_0 Register
(0x00). In Master Mode, the CS4954/5 uses the
VSYNC, HSYNC and FIELD device pins as outputs to schedule the proper external delivery of digital video into the V [7:0] pins. Figure 5 illustrates
horizontal timing for the CCIR601 input in Master
Mode.
The timing of the HSYNC output is selectable in
the PROG_HS Registers (0x0D, 0x0E). HSYNC
can be delayed by one full line cycle. The timing of
the VSYNC output is also selectable in the
NTSC 27MHz Clock Count
PAL 27MHz Clock Count
CLK
HSYNC (output)
CB (output)
V[7:0]
1682
1702
Y
• • •
1683
1703
Cr
active pixel
#720
17051704
Y Cb Y Cr Y
1706
• • •
• • •
1716
1728
1
23 128
1
23 128
horizontal blanking
• • •
• • •
129
129
• • •
• • •
244 245
264 265
246 247
266 267
active pixel#1active pixel
248
268
#2
168616851684
Figure 5. ITU R.BT601 Input Master Mode Horizontal Timing
DS278PP4 15
CS4954 CS4955
Mode Field Active Lines
NTSC 1, 3;
2, 4
22-261;
285-524
P AL 1, 3, 5, 7;
2, 4, 6, 8
23-310;
336-623
NTSC Progressive-Scan NA 22-261
PAL Progressive-Scan NA 23-310
Table 2. Vertical Timing
PROG_VS Register (0x0D). VSYNC can be delayed by thirteen lines or advanced by eighteen lines.
5.2.3. Vertical Timing
The CS4954/5 can be configured to operate in any
of four different timing modes: PAL, which is 625
vertical lines, 25 frames per second interlaced;
NTSC, which is 525 vertical lines, 30 frames per
second interlaced; and either PAL or NTSC in Progressive Scan, in which the display is non-interlaced. These modes are selected in the
CONTROL_0 Register (0x00).
The CS4954/5 conforms to standard digital decompression dimensions and does not process digital
input data for the active analog video half lines as
they are typically in the over/underscan region of
televisions. 240 active lines total per field are processed for NTSC, and 288 active lines total per
field are processed for PAL. Frame vertical dimensions are 480 lines for NTSC and 576 lines for
PAL. Table 2 specifies active line numbers for both
NTSC and PAL. Refer to Figure 6 for HSYNC,
VSYNC and FIELD signal timing.
(falling) edge of HSYNC if the PROG_HS Registers are set to default values.
5.2.5. NTSC Interlaced
The CS4954/5 supports NTSC-M, NTSC-J and
PAL-M modes where there are 525 total lines per
frame and two fixed 262.5-line fields per frame and
30 total frames occurring per second. NTSC inter laced vertical timing is illustrate d in Figure 7. Each
field consists of one line for closed caption, 240 active lines of video, plus 21.5 lines of blanking.
VSYNC field one transitions low at the beginning
of line four and will remain low for three lines or
2574 pixel cycles (858 × 3). The CS4954/5 exclusively reserves line 21 of field one for closed caption insertion. Digital video input is expected to be
delivered to the CS4954/5 V [7:0] pins for 240
lines beginning on active video lines 22 and continuing through line 261. VSYNC field two transitions low in the middle of line 266 and stays low for
three line-times and transitions high in the middle
of line 269. The CS4954/5 exclusively reserves line
284 of field two for closed caption insertion. Video
input on the V [7:0] pins is expected between lines
285 through line 525.
5.2.4. Horizontal Timing
HSYNC is used to synchronize the horizontal-input-to-output timing in order to provide proper horizontal alignment. HSYNC defaults to an input pin
following RESET but switches to an output in Master Mode (CONTROL_0 [4] = 1). Horizontal timing is referenced to HSYNC transitioning low. For
active video lines, digital video input is to be applied to the V [7:0] inputs for 244 (NTSC) or for
264 (PAL) CLK periods following the leading
16 DS278PP4
5.2.6. PAL Interlaced
The CS4954/5 supports PAL modes B, D, G, H, I,
N, and Combination N, in which there are 625 total
lines per frame, two fixed 312.5 line fields per
frame, and 25 total frames per second. Figure 8 illustrates PAL interlaced vertical timing. Each field
consists of 287 active lines of video plus 25.5 lines
of blanking.
VSYNC will transition low to begin field one and
will remain low for 2.5 lines or 2160 pixel cycles
(864 × 2.5). Digital video input is expected to be
delivered to the CS4954/5 V [7:0] pins for 287
lines beginning on active video line 24 and continuing through line 310.
Field two begins with VSYNC transitioning low
after 312.5 lines from the beginning of field one.
NTSC Vertical Timing (odd field)
CS4954 CS4955
Line
HSYNC
VSYNC
FIELD
Line
HSYNC
VSYNC
FIELD
Line
HSYNC
VSYNC
FIELD
3
NTSC Vertical Timing (even fiel d)
264 265
PAL Vertical Timing (odd field)
265 1 2
4
5 6
266 267 268 269 270
7 8 9
3 4 5 6
10
271
7
PAL Vertical Timing (even field)
Line
HSYNC
VSYNC
FIELD
311 312
313 314 315 316 317
Figure 6. Vertical Timing
VSYNC stays low for 2.5 line-times and transitions
high with the beginning of line 315. Video input on
the V [7:0] pins is expected between line 336
through line 622.
5.2.7. Progressive Scan
The CS4954/5 supports a progessive scan mode in
which the video output is non-interlaced. This is
accomplished by displaying only the odd video
field for NTSC or PAL. To preserve precise
MPEG-2 frame rates of 30 and 25 per second, the
CS4954/5 displays the same odd field repetitively
but alternately varies the field times. This mode is
in contrast to other digital video encoders, which
318
commonly support progressive scan by repetitively
displaying a 262 line field (524/525 lines for
NTSC). The common method is flawed: over time,
the output display rate will overrun a system-clo cklocked MPEG-2 decompressor and display a field
twice every 8.75 seconds.
5.2.8. NTSC Progressive Scan
VSYNC will transition low at line four to begin
field one and will remain low for three lines or
2574 pixel cycles (858 × 3). NTSC interlaced timing is illustrated in Figure 9. In this mode, the
CS4954/5 expects digital video input at the V [7:0]
DS278PP4 17
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