Cirrus Logic CS4953-CQ, CS4953-CL, CS4952-CQ, CS4952-CL Datasheet
CS4952/53
T
NTSC/PAL Digital Video Encoder
Features
l
Simultaneous composi t e and S-video output
l
Supports RS170A and CCIR601 composite
output timing
l
Multi-standard support for NTSC-M, PAL (B, D,
G, H, I, M, N, Combination N)
l
Optional progre ssive scan @ M PEG2 field ra tes
l
CCIR656 input mode supporting EAV/SAV
codes and CCIR601 Master/Slave i nput modes
l
Stable color subcarrier for MPEG2 systems
l
NTSC closed caption enc oder with inte rrupt
l
Supports Macrovision copy protection in
CS4953 version
l
Host interfac e c onfigurable fo r parallel or I2C
compatible operation
l
General pur pose input and output pins
l
Individual DAC power-down capabilit y
l
On-chip vol ta ge reference generator
l
On-chip col or bar generato r
l
+5 volt only, CMOS, low power modes, tri-sta te
DACs
Description
The CS4952/3 provides full conversion from YCbCr or
YUV digital video formats into NTSC & PAL Composite
and Y/C (S-video) analog video. Input formats can be
27 MHz 8-bit YUV, 8-bit YCbCr, or CCIR656 with support for EAV/SAV codes. Output video can be form atted
to be compatible with NTSC-M, or PAL B,D,G,H,I,M,N,
and Combination N systems. Also supported is NTSC
line 21 and line 284 closed captioning encoding.
Four 9-bit DACs provide two channels for an S-Video output port and two composite video outputs. 2x oversampling
reduces the output filter requirements and guarantees
no DAC related modulation co mponents within the specified bandwidth of any of the suppor ted video standards.
Parallel or high speed I
are provided for flexibility in system design. The parallel
interface doubl es as a general pu rpose I/O port when t he
CS4952/3 is in I
board area.
ORDERING INFORMATION
CS4952/3-CL 44 pin PLCC
CS4952/3-CQ 44 pin TQFP
2
C compat ible con trol int erfac es
2
C mode to help conserve valuable
CLK
SCL
SDA
PDAT[7:0]
RD*
WR*
ADDR
XTAL
VD[7:0]
HSYNC*
VSYNC*
FIELD
INT
RESET*
2
I C
Interface
8
Host
Parallel
Interface
Color Sub-carrier
Synthesizer
8
Formatter
Video Timing
Generator
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
VAA
LPF
LPF
9-Bit
DAC
9-Bit
Σ
DAC
9-Bit
DAC
9-Bit
DAC
Voltage
Reference
Current
Reference
C
CVBS37
CVBS75
Y
VREFIN
VREFOU
ISET
Video
Control
Registers
Output
Interpolat e
Chroma Amplifier
Chroma Modulate
Burst Insert
Chroma I n terpolate
LPF
U, V
Y
Luma Delay
Luma Amplifier
Sync Insert
Output
Interpolate
GND TEST
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, I nc. 1997
(All Rights Reserv ed)
OCT ‘97
DS223PP2
1
TABLE OF CONTENTS
AC & DC PARAMETRIC SPECIFICATIONS .....................................................................4
INTRODUCTION ...............................................................................................................11
FUNCTIONAL DESCRIPTION .........................................................................................11
Video Timing Generator .........................................................................................11
Video Input Formatter .............................................................................................11
Color Subcarrier Synthesizer ..................................................................................12
Chroma Path ..........................................................................................................12
Luma Path ........................................ ........ ......... ........ ........ ......... ........ ......... ...........12
Digital to Analog Converters ...................................................................................13
Voltage Reference ..................................................................................................13
Current Reference ..................................................................................................13
Host Interface .........................................................................................................13
Closed Caption Services ........................................................................................ 13
Control Registers ....................................................................................................13
OPERATIONAL DESCRIPTION .......................................................................................14
Reset Hierarchy ......................................................................................................14
Video Timing ...........................................................................................................14
Slave Mode Input Interface .............................................................................14
Master Mode Input Interface ...........................................................................14
Vertical Timing .................................................................................................15
Horizontal Timing ............................................................................................15
NTSC Interlaced ..............................................................................................17
PAL Interlaced .................................................................................................17
Progressive Scan ............................................................................................19
PAL Progressive Scan ....................................................................................19
NTSC Progressive Scan .................................................................................19
CCIR-656 ................................................................................................................19
Digital Video Input Modes .......................................................................................22
Multi-standard Output Format Modes .....................................................................22
Subcarrier Generation ............................................................................................22
Subcarrier Compensation .......................................................................................22
Closed Caption Insertion ........................................................................................23
Color Bar Generator ...............................................................................................23
Interrupts ................................................................................................................24
General Purpose I/O Port .......................................................................................24
ANALOG ...........................................................................................................................24
Analog Timing .........................................................................................................24
VREF ......................................................................................................................25
ISET ........................................................................................................................25
DACs ......................................................................................................................25
Luminance DAC ..............................................................................................25
Chrominance DAC ... ........ ......... ........ ......... .......................................... ........ ...25
CVBS75 DAC ..................................................................................................26
CVBS37 DAC ..................................................................................................26
PROGRAMMING ..............................................................................................................27
Host Control Interface .............................................................................................27
I2C Interface ....................................................................................................27
8-bit Parallel Interface .....................................................................................27
Register Description ................................. ......... ........ ........ ......... ........ ......... ........ ...28
Control Register 0............................................................................................28
Control Register 1............................................................................................29
Control Register 2............................................................................................30
DAC Power Down Register..............................................................................30
Status Register.................................................................................................31
Background Color Register..............................................................................31
GPIO Control Register ......................................................... ........ ......... ........ ...31
GPIO Data Register .. ........ ......... .......................................... ........ ......... ........ ...32
Chroma Filter Register.....................................................................................32
Luma Filter Register............................................ ........ ......... ........ ......... ........ ...32
I2C Address Register.......................................................................................32
Subcarrier Amplitude Register .........................................................................33
CS4952/53
2 DS223PP2
Subcarrier Synthesis Register .........................................................................33
Hue LSB Adjust Register.................................................................................33
Hue MSB Adjust Register................................................................................33
Closed Caption Enable Register......................................................................34
Closed Caption Data Register.........................................................................34
Interrupt Enable Register.................................................................................34
Interrupt Clear Register....................................................................................35
Device ID Register...........................................................................................35
BOARD DESIGN & LAYOUT CONSIDERATIONS .........................................................36
Power and Ground Planes .....................................................................................36
Power Supply Decoupling ......................................................................................36
VREF Decoupling ...................................................................................................36
Digital Interconnect ................................................................................................36
Analog Interconnect ...............................................................................................37
Analog Output Protection .......................................................................................37
ESD Protection .......................................................................................................37
External DAC Output Filter .....................................................................................37
DEVICE PINOUT - 44 PLCC ............................................................................................38
PLCC Pin Description ............................................................................................39
DEVICE PINOUT - 44 TQFP ............................................................................................41
TQFP Pin Description ............................................................................................42
CS4952/53
DS223PP2 3
CS4952/53
AC & DC PARAMETRIC SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS: (AGND, DGND = 0 V, all voltages with respect to 0 V.)
Parameter Symbol Min Max Units
Power Supply
Input Current Per Pin Except Supply Pins -10 10 mA
Output Current Per Pin Except Supply Pins -50 +50 mA
Analog Input Voltage -0.3
Digital Input Voltage -0.3
Ambient Temperatur e Power Applied -55 +125 °C
Storage Temperature -65 +150 °C
Warning: Operating beyond these limits may result in permanent damage to the device.
Normal operation is not guarant eed at these extremes.
RECOMMENDED OPERATING CONDITI ONS: (AGND, DGND = 0 V, all voltages with
respect to 0 V.)
V
AA
-0.3 6.0 V
V
+0.3
AA
VAA+0.3
V
V
Parameter Symbol Min TypMax Units
Power Supplies: Digital Analog
Operating Ambient Temperature
V
AA
T
A
4.75 5.0 5.25 V
0+25+70 °C
4 DS223PP2
CS4952/53
D.C. CHARACTERISTICS: (T
=25 C; VAA = 5 V; GND = 0 V.)
A
Parameter Symbol Min T yp Max Units
Digital Inputs
High Level Input Voltage V [7:0], PDAT [7:0],
HSYNC
High Level Input Voltage I
/VSYNC/FIELD/CLKIN
2
Low Level Input Voltage All Inputs
V
IH
V
C
IH
V
IL
2.0 -
0.7V
AA
--V
-0.3 - 0.8 V
VAA+0.3
Input Leakage Current Digital Input s - -10 - +10
Digital Outputs
High Level Output Voltage Io = -4mA
Low Level Output Voltage Io = 4mA
Low Level Output Voltage SDA pin only, Io = 6mA
V
OH
V
OL
V
OL
2.4 -
--0.4V
--0.4V
V
AA
Output Leakage Current High-Z Digital Outputs - -10 - +10
Analog Outputs
Full Scale Output Current CVBS37/Y/C (Note 1) IO37 32.9 34.7 36.5 mA
Full Scale Output Current CVBS75 (Note 1) IO75 16.4 17.3 18.2 mA
LSB Current CVBS37/Y/C (Note 1) IB37 64.5 68 71.5
LSB Current CVBS75 (Note 1) IB35 32.2 34 35.8
DAC-to-DAC Matching MAT - 2 - %
R
C
O
V
OUT
OUT
T
OC
DEL
RF
0-+1.4V
-15-k
--30pF
-412ns
-2.55ns
Output Compliance
Output Impedance
Output Capacitance
DAC Output Delay
DAC Rise/Fall Time (Note 2)
Voltage Reference
Reference Voltage Output
Reference Input Current
V
OV
I
VC
1.198 1.232 1.272 V
--10
Power Supply
Supply Voltage
Supply Current All DACs on
CVBS75/CVGS37 only
CVBS75 only
V
AA
IAA1
IAA2
IAA3
4.75 5 5.25 V
-
-
-
180
110
75
200
-
-
mA
mA
mA
V
µ
A
V
µ
A
µ
A
µ
A
Ω
µ
A
Notes: 1. Output current level s with ISET = 10 kΩ, VREFIN = 1.232 V.
2. Times for black-to-white level and white-to-bl ack level transitions.
DS223PP2 5
CS4952/53
D.C. CHARACTERISTICS (Continued)
Parameter Symbol Min Typ Max Units
Static Performan c e
DAC Resolution - - 9 Bits
Differential Non-Line arity DNL -1 ±0.5 +1 LSB
Integral Non-Linearity INL -1 ±0.35 +1 LSB
Dynamic Performance
Differential Gain DB - 2 5 %
Differential Phase DP - ±0.5 ±2 °
Signal to Noise Ratio SNR -70 - - dB
Hue Accuracy
Saturation Accuracy
H
A
S
A
--2°
--2%
6 DS223PP2
A.C. CHARACTERISTICS:
Parameter Symbol Min Typ Max Units
Pixel Input and Control Port
Clock Pulse High Time
Clock Pulse Low Time
Clock to Data Set-up Time
Clock to Data Hold Time
Clock to Data Output Delay
CLK
TchT
V[7:0]
HSYNC*/VSYNC*
(Inputs)
HSYNC*/VSYNC*/
CB/FIELD/INT
(Outputs)
Figure 1. Video Pixel Data and Control Port Timing
CS4952/53
T
ch
T
cl
T
isu
T
ih
T
oa
T
cl
isu
T
ih
14.82 18.52 22.58 ns
14.82 18.52 22.58 ns
6--ns
0--ns
--17ns
T
oa
Parameter Symbol Min Typ Max Units
I2C Host Port Timing
SCL Frequency
Clock Pulse High Time
Clock Pulse Low Time
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
Rise Time
Fall Time
Setup Time (Stop Condition)
Bus Free Time
Data Hold Time
SCL Low to Data Out Valid
SDA
SCL
F
clk
T
sph
T
spl
T
sh
T
ssu
T
sds
T
sr
T
sf
T
ss
T
buf
T
dh
T
vdo
T
T
sh
buf
T
sr
T
sph
T
T
sds
dh
T
vdo
100 1000 KHz
0.1 µs
0.7 µs
100 ns
100 ns
50 ns
1µs
0.3 µs
100 ns
100 ns
0ns
600 ns
T
sh
T
ss
T
spl
T
sf
T
ssu
Figure 2. I2C Host Port Timing
DS223PP2 7
A.C. CHARACTERISTICS: (Continued)
Parameter Symbol Min Typ Max Units
8-bit Parallel Host Interface
Read Cycle Time
Read Pulse Width
Address Setup Ti me
Read Address Hold Time
Read Data Access Time
Read Data Hold Time
Write Recovery Time
Write Pu lse Width
Write Data Setup Time
Write Data Hold Time
Write-Read/Read-Write Recovery Time
Address from Write Hold Time
T
T
T
T
T
T
T
T
T
T
T
wpw
wds
wdh
T
wac
rd
rpw
as
rah
rda
rdh
wr
rec
CS4952/53
60 - - ns
30 - - ns
3--ns
10 - - ns
--40ns
10 - 50 ns
60 - - ns
40 - - ns
8--ns
3--ns
50 - - ns
0--ns
RD*
ADDR
PDAT[7:0]
WR*
ADDR
PDAT[7:0]
T
rd
T
rpw
T
as
T
rda
T
rah
T
rdh
8-bit Parallel Host Port Timing: Read Cycle
T
wpw
T
as
T
wds
T
wr
T
wac
T
wdh
8-bit Parallel Host Port Timing: Address Write Cycle
WR*
T
rec
RD*
T
rec
8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle
Figure 3.
8 DS223PP2
A.C. CHARACTERISTICS: (Continued)
Parameter Symbol Min Typ Max Units
Reset Timing
Reset Pulse Width
RESET*
Figur e 4. Reset Timing
CS4952/53
T
res
T
res
100 ns
DS223PP2 9
+5V
(Vcc)
L1
Ferrite Bead
4.7 µF 0.1 µF
18
NC
19
XTAL
ADDR
1
3
VAA
VREFOUT
20 29
VREFIN
42
41
CS4952/53
0.1 µF
2
I C
Controller
27 MHz Clock
GPIO Port
+5V (Vcc)
Ω
1.5k
Pixel Data
1.5k
Ω
110
110
8
Ω
Ω
8
31
32
35
36
33
7-14
15
16
17
PDAT[7: 0]
RD*
WR*
SDA
SCL
CLK
V[7:0]
FIELD
HSYNC*/CB
VSYNC*
6
TEST
CS4952
CS4953
GND
2 21 22
CVBS75
CVBS37
RESET*
38
INT
ISET
5
75
4
75
43
Y
75
44
C
75
34
37
40
10 kΩ±1%
To RF Modulator
Ω
Composite Video
Connector
Ω
Ω
S-Video
Connector
Ω
Figure 5. Typical Connection Diagram (I2C host interface)
10 DS223PP2
CS4952/53
INTRODUCTION
The CS4952/3 is a co mp lete mult i-stan dard dig ital
video enco der implem ented in current 5-volt only
CMOS technology. CCIR601 or CCIR656 compliant digital video input can be converted into
NTSC-M, PAL B, PAL D, PAL G, PAL H, PAL I,
PAL M, PAL N, or PAL N A rgentina- compatib le
analog vide o. Th e CS49 52/ 3 is de sig ned to conn ect
to MPEG1 and MPEG2 dig ital video decompressors without glue logic .
Two 9-bit DAC outputs provide high quality
S-Video analog output while two other 9-bit DACs
simultaneously generate composite analog video.
The CS4952/3 will accept 8-bit YCbCr or 8-bit
YUV input data.
The CS495 2/3 is completely con figured and con-
2
trolled via an 8-bit host interface port or an I
compatible serial interface. This host port provides
access and control of all CS4952/3 options and features like closed caption insertion, interrupts, etc.
In order to lo wer the en d user set- top overall s ystem costs, the CS4 952/3 provide s an inter nal volt age reference which eliminates the requirement for
an external disc re te 3-pin voltage reference.
C
FUNCTIONAL DESCRIPTION
In the following subse ctions, the functi ons of the
CS4952/3 will be described. The descriptions refer
to the block diagram on the cover page.
Video Timing Generator
All timing generation is accomplished via a
27 MHz input applied to the CLK pin. The
CS4952/3 can also accept an opti onal color burst
crystal on the ADDR & XTAL pins. See section:
Color Subcarrier Synthesizer (page 12), for further
details.
The Video Ti mi ng Generator is responsible for orchestrating most all of th e other modules in th e device. It wor ks i n harmony wi th external sync input
timing or by providing external sync timing out-
puts. It automatically disables color burst on appropriate scan lines and generates serration and
equalization pulses on appropriate sca n li nes.
The CS4952/ 3 is designed to function a s a video
timing master or video timing slave. In both Master
and Slave Modes, all timing is sampled and asserted with the rising edge of the CLK pin.
In most cases the CS495 2/3 will serve as the vi deo
timing master. The master timing cannot be externally altere d other than through the host interface
by changing the video display modes: PAL or
NTSC and Progressive Scan. HSYNC
and FIELD are configured as outputs for Master
Mode. HSYNC
blanking output signal in Mast er Mode. Exact horizontal and vertical displ ay timing is a ddressed in
section: Operati ona l De scription (page 14).
In Slave Mode HSYN C
ured as input pins and are used to initialize inde pendent vertical and horizontal timing generators
upon their respective falling edges. FIELD remains
an output in Slave Mode.
The CS4952/3 also provides a CCIR-656 Slave
Mode where the video inpu t stream c ontains EAV
and SAV codes. In this case, proper HSYNC
VSYNC timing is extracted automatically without
aid from any inputs other than the V [7:0].
CCIR-656 input data is sampled with th e leading
edge of C LK. Slave M ode vertical an d horizontal
timing derived via CCIR-656 or ext er na l ha rdware
must be equivalent to timing generated by the
CS4952/3 in Master Mode .
can also be defined as a composite
and VSYNC are config-
, VSYNC
Video Input Formatter
The video input form atter translates YCbCr input
data into YUV information, if necessary, and splits
the luma and chroma information for filtering, scaling, and modulation.
DS223PP2 11
CS4952/53
Color Subcarrier Synthesizer
The subcarrier synthesizer is a digital frequency
synthesizer that produces the correct subcarrier frequency for NTSC or PAL. The CS4952/3 generates
the color burst fre quency based on the input CLK
(27 MHz). Color burst accuracy and stability are
limited by the accuracy of the 27 MHz input. If the
frequency varies then the color burst frequency will
also vary accordi ngl y.
In order to handle situations in which the CLK varies unacceptably, a local crystal frequency reference may be used on the ADDR & X TAL device
pins. In this instance the input CLK is continuously
compared with the external crystal reference input
and the internal timing of the CS4952/3 is auto matically adjusted so that the color burst frequency remains close to the requirements.
Controls are pr ovided for phase ad justment of the
burst to permit color adjustment and phase compensation. C hroma hue c ontrol is pro vided by t he
CS4952/3 via a 10-bit Hue Control Register
(HUE_LSB and H_MSB). Burst amplitude control
is also made available to the host via the 8-bit burst
amplitude register (SC_AMP).
The output of the chroma low pass filter is connected to the c hro ma i nterp ol atio n filt er whe re upsam pling from 4:2:2 to 4:4:4 is accomplished. The
chroma digital data is fed to a quadrature modulator
where they are combined with the output from the
subcarrier synthesizer to produce the proper modulated chrominance signal.
Following chroma modulation the chroma data
passes through a vari able gai n amp lifi er w here t he
chroma amp litude may be varied via th e C_AMP
8-bit host addressa ble re giste r. Th e c hroma then i s
interpola ted by a fact or of 2 in orde r to operate the
output DACs at 2 times the pixel rate. The interpolated filters help reduce the sinx/x roll-off for higher frequencies and reduce the complexity of the
external ana log low pa ss filte rs.
Luma Path
Along with the chr oma output pat h, the CS495 2/3
Video Input Formatter initiates a parallel luma data
path by d irecting the luma data to a digital delay
line. The delay line is built as a digital FIFO where
the depth of the FIFO repl icates the cloc k period
delay associated with the more complex chroma
path.
Chroma Path
The Video Input Formatter a t conclusion deli vers
4:2:2 YUV o u tputs into se parate chro ma and lum a
data paths. The chroma path will be discussed here.
The chroma output of the Video Input Formatter is
directed to a chroma low pass 19-tap FIR filter. The
filter bandwidth is selected or the filt er may be bypassed via the CONTROL_1 register. The passband of the filter is either 650 KHz or 1.3 MHz and
the passband ripple is less than or equal to 0.05 dB.
The stopband for the 1.3 MHz se lection begins at
3 MHz with an attenuation of greater that 35 dB.
The stopband for the 650 KHz selection begins
around 1.1 MHz with an attenuation of greater than
20 dB.
12 DS223PP2
Following the luma delay, the data is passed
through a varia ble gain amplifier wher e the luma
DC values are modifiable via the Y_AMP register.
The output of the luma amplifier connects to the
sync insertion block. Sync insertion is accomplished by multiplexing into the luma data path the
different sync DC value s at the appropri ate times.
The digital sync generator takes horizontal sync
and vertical sync timing signals and gene rates the
appropriat e composite sync timing (inc luding ver tical equalization and serration pulses), blanking
information, and burst flag. The sync edge rates
conform to RS-170A or CCIR specifications.
The luma only path is concluded via output interpolation by a factor of two in order to operate the output DACs at two times the pixel rate.
CS4952/53
Digital to Analog Converters
The CS4952/3 provides four complete simultaneous 27 MHz DACs for analog video output : one
9-bit for S-video chrominance, one 9-bit for S-Video luminance, and two 9-bit composite outputs.
Both S-Video DACs are designed for 37.5 Ω overall loads. Th e two composite 9-bit DACs are not
identical. One DAC is designed to drive 37.5 Ω derived from a double termina ted 75 Ω circuit. The
second 9-bit DAC is targeted for an on-board local
video connection where single point 75 Ω termination is suffic ient i.e. Ch3/4 RF modulators, video
amps, muxes.
The DACs ca n be put into tri- state mode vi a host
addressable cont rol register bits. Each of the fou r
DACs has its own separate DAC enable associated
with it. In the disable mode, the 9-bit DACs source
or sink zero current .
For lower power sta ndby scenarios the CS495 2/3
also provides power shut-off control for the DACs.
Each DAC has a separate DAC shut-off associated
with it.
Voltage Reference
The CS4952/3 is equipped with an on-board
1.235 V voltage reference generator used by the
Video DACs. For most requirements, the voltage
reference outpu t pin can be connec ted to the voltage reference input pin along with a decoupling capacitor. Otherwise the voltage reference input may
be connected to an external vo l ta g e refe rence.
Current Reference
The DAC outpu t current per bit is derived in the
current refere nce block. The current step i s specified by the siz e of resi sto r plac e betw ee n the ISE T
current reference pin and electrical ground. This
has been optimized for 10kΩ (see “ISET” on
page 25 for more informmation on selecting the
proper ISET value).
Host Interface
The CS4952/ 3 provides a parall el 8-bit d ata inter face for overall configuration and control. The host
interface uses active low read and write strobes
along with a n active low addre ss enable signal to
provide micro proce ssor comp atible read an d write
cycles. Indirect host addressing to the CS4952/3 internal regis ters is ac com plishe d via an interna l address register which i s u nique ly a cce ssible via bus
write cy cles with the h ost addres s enable sign al asserted.
2
The CS4952/3 al so provides an I
rial interf ace for dev ice co nfigur ation and c ontrol.
This port can operate in standard or fast (400 KHz)
2
modes. When in I
face PDAT [7:0] pins may be used as a general purpose I/O port control le d by the I
C mode, the pa rallel data i nter -
C compatible se-
2
C interface.
Closed Caption Services
The CS4952/3 supports the generation of NTSC
Closed Caption services. Line 21 and Line 284 captioning can be generated and enabled independently via a set of control registers. When enabled,
clock run-in, sta rt bit , and d ata byte s are aut oma tically inserted at the appropriate video lines. A convenient inte rrupt interface simplifi es the software
interface between the host processor and the
CS4952/3.
Control Registers
The control an d configuration of the CS49 52/3 is
primarily acco mplished through the control register block. All of the control registe rs are uniquely
addressable via the internal address register. The
control register bits are initialized during a chip reset.
See the detailed operation section of this data sheet
for all of the individua l register bit allo cation s, bit
operational descripti ons and initialization st at es .
DS223PP2 13
CS4952/53
OPERATIONAL DESCRIPTION
Reset Hierarchy
The CS4952/3 is equipped with an active low asynchronous reset input pin RESET
initialize the internal registers and the internal state
machines for subsequent default operation. See the
electrical and timing specification section of this
data sheet for specific CS4952/3 chip reset and
power-on signaling timing requirements and restrictions. All chip outputs are valid after a time period following RESET
pin low.
When the RESET pin is held low, the host interface
in the CS4952/3 is disabled and will not respond to
host initiated bus cycles.
A reset initializes the CS4952/3 internal registers to
their default va lues a s descr ibed by Table 5. In the
default state, the CS49 52/53 video DACs are disabled and the device is configured to internally provide blue field video data to the DACs (an y input
data present on t he V [7:0] pins is ignored). Other wise the CS4952/53 registers are configured for
NTSC-M CCIR601 output operation. At a minimum, the DAC registe r (0 x04) mu st be wri tten (to
enable the DACs) and the IN_MODE bit of the
CONTROL_0 regi ster (0x01) must be set (to enable CCIR601 data input on V [7:0]) for the
CS4952/53 to become operational after RESE T.
. RESET is used to
Video Timing
Slave Mode Input Interface
In Slave Mode, the CS4952/3 takes VSYNC and
HSYNC
as inputs. Slave Mode is the de fault following a reset and is changed to Master Mode via a
contol register bit (CONTROL_0 [4]). The
CS4952/3 is limited to CCIR601 horizontal and
vertical input timing. All clocking in the CS4952/3
is generated fr om th e C LK pin . In Sla ve Mod e the
Sync Generator uses externally provided horizontal
and vertical sync signals to synchronize the internal
timing of the CS4952/3.
Video data that is sent to the CS4952/3 must be
synchronized to the horizontal and vertical sync
signals. Figure 6 illustrates horizontal timing for
CCIR601 input in Slave Mode. Note that the
CS4952/3 expec ts to receive the first ac tive pixel
data on clock cycle 245 (NTSC) when bit
SYNC_DLY=0 in the CONTROL_2 Register
(Ox02). When SYNC_DLY=1, it expects the first
active pixel data on clock cycle 246 (NTSC).
Master Mode Input Interface
The CS4952/3 defaults to Slave Mode following
RESET
Mode via the MSTR bit in the CONTROL_0 Register (0x00). In Maste r Mode, the CS4952/3 uses
the VSYNC
high but may be switched into Master
, HSYNC and FIELD device pins as
1686168516841683 1716 1 2 3 128 129 244 245 246 247 248
PAL 27MHz Clock Count 1702
HSYNC* (input)
(SYNC_DLY=0)
(SYNC_DLY=1)
14 DS223PP2
1682
CLK
V[7:0]
YCrY Cb Y Cr Y
active pixel
• • •
#720
V[7:0]
YCrY Cb Y Cr
Cb
active pixel
#719
Figure 6. CCIR601 Input Slave Mode Horizontal Timing
170517041703 1728 1 2 3 128 129 264 265 266 267 268
active pixel
#720
1706
• • •
• • •
horizontal blanki ng activ e pixel#1active pixel
horizontal blanking active pixel#1active pixel
• • •
• • •
• • •NTSC 27MHz Clock Count
• • •
#2
#2
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