Cirrus Logic CS43L42-KZ, CS43L42 Datasheet

CS43L42

Low Voltage, Stereo DAC with Headphone Amp

Features

l 1.8 to 3.3 Volt su pply l 24-Bit conversion / 96 kHz sample rate l 96 dB dynamic range at 3 V supply l -85 dB THD+N l Low power consumption l Digital volume control

— 96 dB attenuation, 1 dB step size

l Digital bass and treble boost

— Selectable corner frequencies — Up to 12 dB boost in 1 dB increments

l Peak signal limiting to prevent clipping l De-emphasis for 32 kHz, 44.1 kHz, a nd 48 kHz l Headphone amplifier

— up to 25 mW — 25 dB analog attenuation and mute — Zero crossing click free level transitions

l ATAPI mixing functions l 24-Pin TSSOP package

* 1 kHz sine wave at 3.3V supply

power output into 16 Ω load*

rms

Description

The CS43L42 is a complete stereo digital-to-analog output system including interpolation, 1-bit D/A conversion, analog filtering, vo lu me c ontrol , li ne l eve l ou tput s, and a headphone amplifier, in a 24-pin TSSOP package.

The CS43L42 is based on delta-sigma modulation, where the modulator output cont rols the reference vo ltage input to an ultra-linear analog low -pass filter. This architectu re allo ws infin ite adju stme nt of the sa mple ra te between 2 kHz and 100 kHz simply by changing the master clock freque nc y.

The CS43L42 contain s on-chip digital ba ss and treble boost, peak signal limiting, and de-emphasis. The CS43L42 operates fr om a +1.8 V to +3.3 V supply and consumes only 16 mW of power with a 1.8 V supply with the line amplifier powered-down. These features are ideal for portable CD, MP3 and MD players and ot her portable playback systems that require extremely low power consumption.

ORDERING INFORMATION

CS43L42-KZ -10 to 70 °C 24-pin TSSOP CDB43L42 Evaluation Board

SCL/CCLK/DIF1 SDA/CDIN/DIF0

RST

VA VL

LRCK

Bass/Treble

SCLK/DEM1

SDATA

De-emphasis

Serial Port

GND

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

Control Port

Digital Volume Control

Boost

Limiting

AD0/CS/DEM0

MCLK

MUTEC

External

Mute Control

∆Σ

DAC

∆Σ

Digital Filters

DAC

FILT+ REF_GND VQ_LINE

Analog

Filter

Analog

Filter

VQ_HP

Analog Volume Control

a G

VA_HP

Amplifier

Headphone

Line

Compensation

Amplifier

VA_LINE

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

HP_A

HP_B

AOUTA

AOUTB

APR ‘00

DS481PP1

1. CHARACTERISTICS/SPECIFICATIONS .................................................................... 5

ANALOG CHARACTERISTICS................................................................................ 5

ANALOG CHARACTERISTICS................................................................................ 6

ANALOG CHARACTERISTICS................................................................................ 7

POWER AND THERMAL CHARACTERISTICS ...................................................... 8

DIGITAL CHARACTERISTICS................................................................................. 9

ABSOLUTE MAXIMUM RATINGS........................................................................... 9

RECOMMENDED OPERATING CONDITIONS....................................................... 9

SWITCHING CHARACTERISTICS ................................................. ....... ...... .......... 10

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE ...... 12

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE.................... 13

2. TYPICAL CONNECTION DIAGRAM ....................................................................... 14

3. REGISTER QUICK REFERENCE ......................................... ....... ...... ....... ................ 15

4. REGISTER DESCRIPTION ................... ....... ...... ............................................. ....... ... 1 6

4.1 Power and Muting Control (address 01h)....................................................... 16

4.1.1 Auto-mute (AMUTE) ..................................................................................... 16

4.1.2 Soft Ramp AND Zero Cross CONTROL (SZC)............................................. 16

4.1.3 Popguard® Transient Control (POR)............................................................ 17

4.1.4 Power Down Headphone Amplifier (PDNHP)................................................ 17

4.1.5 Power Down Line Amplifier (PDNLN)............................................................ 17

4.1.6 Power Down (PDN) ....................................................................................... 17

4.2 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA).. 18

4.3 Channel B Analog Headphone Attenuation Control (address 03h) (hVOLB).. 18

4.4 Channel A Digital Volume Control (address 04h) (DVOLA) ............................ 18

4.5 Channel B Digital Volume Control (address 05h) (DVOLB) ............................ 18

4.6 Tone Control (address 06h)............................................................................. 19

4.6.1 Bass Boost Level (BB).................................. .............................................. ... 19

4.6.2 Treble Boost Level (tb) .................................................................................. 19

4.7 Mode Control (address 07h)............................................................................ 20

4.7.1 Bass Boost Corner Frequency (bbcf) ............................................................ 20

4.7.2 Treble Boost Corner Frequency (TBCF)........................................................ 20

4.7.3 Channel A Volume = Channel B Volume (A=B) ............................................ 20

4.7.4 De-Emphasis Control (DEM)......................................................................... 21

4.7.5 Digital Volume Control Bypass (VCBYP)....................................................... 21

4.8 Limiter Attack Rate (address 08h) (ARATE).................................................... 21

4.9 Limiter Release Rate (address 09h) (RRATE) ............................................ 22

CS43L42

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

I2C is a registered trademark of Ph ilips Semiconductors. Preliminary product inf o rmation describes products whi ch are i n production, but for whi c h ful l characterization data is not yet available. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best effort s to ensure that the information contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. Ite ms f rom any Ci rrus L ogi c websi t e or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2 DS481PP1

CS43L42

4.10 Volume and Mixing Control (address 0Ah).....................................................22

4.10.1 Tone Control MODE (TC).............................................................................22

4.10.2 Tone Control Enable (TC_EN) .....................................................................22

4.10.3 Peak Signal Limiter Enable (LIM_EN)..........................................................23

4.10.4 ATAPI Channel Mixing and Muting (atapi) ...................................................23

4.11 Mode Control 2 (address 0Bh) .......................................................................24

4.11.1 Master Clock DIVIDE ENABLE (mclkdiv).....................................................24

4.11.2 Line Amplifier Gain Compensation (line)......................................................24

4.11.3 Digital Interface Format (dif).........................................................................24

5. PIN DESCRIPTION .......................... ...... ............................................. ....... ...... ....... ....26

6. APPLICATIONS .........................................................................................................29

6.1 Grounding and Power Supply Decoupling ......................................................29

6.2 Clock Modes ....................................................................................................29

6.3 De-Emphasis ...................................................................................................29

6.4 Recommended Power-up Sequence ..............................................................29

6.5 PopGuard® Transient Control .........................................................................29

7. CONTROL PORT INTERFACE ....... ...... ....... ...... ...... .............................................. ....30

7.1 SPI Mode .........................................................................................................30

7.2 Two-Wire Mode ...............................................................................................30

7.3 Memory Address Pointer (MAP) .............................................................31

7.3.1 INCR (Auto Map Increment Enable)...............................................................31

7.3.2 MAP0-3 (Memory Address Pointer) ...............................................................31

8. PARAMETER DEFINITIONS ......................................................................................39

9. REFERENCES ............................................................................................................39

10. PACKAGE DIMENSIONS .......................................................................................40

LIST OF FIGURES

Figure 1. External Serial Mode Input Timing ......................................................................... 11

Figure 2. Internal Serial Mode Input Timing ............. ...... ............................................. ....... ... 1 1

Figure 3. Internal Serial Clock Generation .. ...... ....... ...... ...... ....... ...... ....... ............................. 11

Figure 4. Control Port Timing - Two-Wire Mode .................................................................... 12

Figure 5. Control Port Timing - SPI Mode ............................................................................. 13

Figure 6. Typical Connection Diagram ................................. ....... ...... .................................... 14

Figure 7. Control Port Timing, SPI mode ............................................................................... 31

Figure 8. Control Port Timing, Two-Wire Mode ..................................................................... 31

Figure 9. Base-Rate Stopband Rejection .............................................................................. 32

Figure 10. Base-Rate Transition Band .................................................................................. 32

Figure 11. Base-Rate Transition Band (Detail) ...................................................................... 32

Figure 12. Base-Rate Passband Ripple ................................................................................ 32

Figure 13. High-Rate Stopband Rejection ............................................................................. 32

Figure 14. High-Rate Transition Band ................................................................................... 32

Figure 15. High-Rate Transition Band (Detail) ...................................................................... 33

Figure 16. High-Rate Passband Ripple ................................................................................. 33

Figure 17. Line Output Test Load .......................................................................................... 33

Figure 18. Headphone Output Test Load .............................................................................. 33

Figure 19. CS43L42 Control Port Mode - Serial Audio Format 0 .......................................... 34

Figure 20. CS43L42 Control Port Mode - Serial Audio Format 1 .......................................... 34

Figure 21. CS43L42 Control Port Mode - Serial Audio Format 2 .......................................... 34

Figure 22. CS43L42 Control Port Mode - Serial Audio Format 3 .......................................... 35

Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4 .......................................... 35

Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5 .......................................... 35

Figure 25. CS43L42 Control Port Mode - Serial Audio Format 6 .......................................... 36

Figure 26. CS43L42 Stand Alone Mode - Serial Audio Format 0 .......................................... 36

DS481PP1 3

Figure 27. CS43L42 Stand Alone Mode - Serial Audio Format 1 ..........................................36

Figure 28. CS43L42 Stand Alone Mode - Serial Audio Format 2 ..........................................37

Figure 29. CS43L42 Stand Alone Mode - Serial Audio Format 3 ..........................................37

Figure 30. De-Emphasis Curve ..............................................................................................38

Figure 31. ATAPI Block Diagram ........................................................................................... 38

LIST OF TABLES

Table 1. Example Analog Volume Settings ............................................................................ 18

Table 2. Example Digital Volume Settings ............................................................................. 19

Table 3. Example Bass Boost Settings .................................................................................. 19

Table 4. Example Treble Boost Settings ................................................................................ 19

Table 5. Example Limiter Attack Rate Settings ...................................................................... 21

Table 6. Example Limiter Release Rate Settings .................................................................. 22

Table 7. ATAPI Decode ......................................................................................................... 23

Table 8. Digital Interface Format ............................................................................................ 25

Table 9. Stand Alone De-Emphasis Control .......................................................................... 27

Table 10. HRM Common Clock Frequencies ........................................................................ 27

Table 11. BRM Common Clock Frequencies ......................................................................... 27

Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode) ............................. 28

CS43L42

4 DS481PP1

1. CHARACTERISTICS/SPECIFICATIONS

CS43L42

ANALOG CHARACTERISTICS (T

Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz. Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz. Test load R ure 18) for headphone out).

Parameter

=10kΩ, CL= 10 pF (see Figure 17) for line out, RL=16Ω, CL = 10 pF (see Fig-

= 25° C; Logic "1" = VL = 1.8 V; Logic "0" = GND = 0 V;

Base-rate Mode High-Rate Mode

Symbol Min Typ Max Min Typ Max Unit

Line Output Dynamic Performance for VA = VA_LINE = 1.8 V

Dynamic Range (Note 1)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 100 - - 100 - dB

THD+N

TBD TBD

91 94 89 92

-80

-71

-31

-78

-69

-29

TBD

TBD TBD

89 92 87 90

-80

-69

-29

-78

-67

-27

TBD

dB dB dB dB

dB dB dB dB dB dB

Headphone Output Dynamic Performance for VA = VA_HP = 1.8 V

Dynamic Range (Note 1)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 66 - - 66 - dB

THD+N

TBD TBD

88 91 86 89

-82

-68

-28

-80

-66

-26

TBD

TBD TBD

88 91 86 89

-85

-68

-28

-83

-66

-26

TBD

dB dB dB dB

dB dB dB dB dB dB

Notes: 1. One-half LSB of triangular PDF dither is added to data.

DS481PP1 5

CS43L42

ANALOG CHARACTERISTICS (Continued)

Base-rate Mode High-Rate Mode

Parameter

Line Output Dynamic Performance for VA = VA_LINE = 3.0 V

Dynamic Range. (Note 1)

18 to 24-Bit. unweighted

A-Weighted

16-Bit. unweighted

A-Weighted

Total Harmonic Distortion + Noise. (Note 1)

18 to 24-Bit. 0 dB

-20 dB

-60 dB

16-Bit. 0 dB

-20 dB

-60 dB

Interchannel Isolation. (1 kHz) - 100 - - 100 - dB

Headphone Output Dynamic Performance for VA = VA_HP = 3.0 V

Dynamic Range. (Note 1)

18 to 24-Bit. unweighted

A-Weighted

16-Bit. unweighted

A-Weighted

Total Harmonic Distortion + Noise. (Note 1)

18 to 24-Bit. 0 dB

-20 dB

-60 dB

16-Bit. 0 dB

-20 dB

-60 dB

Interchannel Isolation. (1 kHz) - 66 - - 66 - dB

Symbol Min T yp Max Min Typ Max Unit

TBD TBD

THD+N

TBD TBD

THD+N

93 96 91 94

-85

-73

-33

-83

-71

-31

90 93 88 91

-76

-70

-30

-74

-68

-28

TBD

TBD TBD

93 96 91 94

-85

-73

-33

-83

-71

-31

90 93 88 91

-73

-70

-30

-71

-68

-28

TBD

dB dB dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB dB dB dB dB

6 DS481PP1

CS43L42

ANALOG CHARACTERISTICS (Continued)

Parameters Symbol Min Typ Max Units

Analog Output

Full Scale Line Output Voltage (Note 2) V Line Output Quiescent Voltage V Full Scale Headphone Output Voltage V Headphone Output Quiescent Voltage V Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C

Maximum Line Output AC-Current VA=VA_LINE=1.8 V

VA=VA_LINE=3.0 V

Maximum Headphone Output VA=VA_HP=1.8 V AC-Current VA=VA_HP=3.0 V

FS_LINE

Q_LINE

FS_HP

Q_HP

LINE

Base-rate Mode High-Rate Mode

Parameter

Combined Digital and On-chip Analog Filter Response (Note 3)

Passband (Note 4)

to -0.05 dB corner

to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz

(Note 5) StopBand .5465 - - .577 - - Fs StopBand Attenuation (Note 6) 50 - - 55 - - dB Group Delay tgd - 9/Fs - - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz

0 - 20 kHz

De-emphasis Error Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

Symbol Min Typ Max Min Typ Max Unit

-.02 - +.08 0 - +0.11 dB

--±0.36/Fs

TBD G x VA TBD Vpp

- 0.5 x VA_LINE - VDC

TBD 0.55 x VA TBD Vpp

- 0.5 x VA_HP - VDC

.4535

.4998

+.2/-.1

+.05/-.14

+0/-.22

0.1

0.15 31

0 0

--±1.39/Fs

±0.23/Fs--

(Note 7)

.4426 .4984

mA mA

Fs Fs Fs

s s

dB dB dB

Notes: 2. See

3. Filter response is not tested but is guaranteed by design.

4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9-16) have

5. Referenced to a 1 kHz, full-scale sine wave.

6. For Base-Rate Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.

7. De-empha si s is not availab le in High - Rate Mode.

DS481PP1 7

Line Amplifier Gain Compensation (line)

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

For High-Rate Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

for details.

CS43L42

POWER AND THERMAL CHARACTERISTICS (GND = 0 V; All voltages with respect to

ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current- VA =1.8 V Normal Operation VA_HP=1.8 V

VA_LINE=1.8 V

A_LINE

VL=1.8 V

Power Supply Current- VA =1.8 V Power Down Mode (Note 8) VA _HP=1.8 V

VA_LINE=1.8 V

A_LINE

VL=1.8 V

Power Supply Current- VA =3.0 V Normal Operation VA_HP=3.0 V

VA_LINE=3.0 V

A_LINE

VL=3.0 V

Power Supply Current- VA =3.0 V Power Down Mode (Note 8) VA _HP=3.0 V

VA_LINE=3.0 V

A_LINE

VL=3.0 V

Total Power Dissipation- All Supplies=1.8 V Normal Operation All Supplies=3.0 V

Maximum Headphone Power Dissipation (1 kHz full-scale sine wave VA=1.8 V into 16 ohm load) VA=3.0 V

Package Thermal Resistance θ Power Supply Rejection Ratio (Note 9) (1 kHz)

PSRR -

(60 Hz)

A_HP

D_L

A_HP

D_L

A_HP

D_L

A_HP

D_L

7.3

1.5

1.6 4

TBD TBD TBD TBD

10.5

1.5

1.7

9.3

TBD TBD TBD TBD

19 41

TBD TBD

mA mA mA

µA µA

µA µA µA

mA mA mA

µA µA

µA µA µA

mW mW

- 75 - °C/Watt 60

dB dB

Notes: 8. Power Down Mode is defined as RST

= LO with all clocks and data lines held static.

9. Valid with the recommended capacitor values on FILT+, VQ_LINE and VQ_HP as shown in Figure 6. Increasing the capacitance will also increase the PSRR. Note that care should be taken when selecting capacitor type, as any leakage current in excess of 1.0 µA will cause degradation in analog

performance.

8 DS481PP1

CS43L42

DIGITAL CHARACTERISTICS (T

= 25° C; VL = 1.7 V - 3.6 V; GND = 0 V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage Low-Level Input Voltage Input Leakage Current I

0.7 x VL - - V

- - 0.3 x VL V

--±10µA Input Capacitance - 8 - pF Maximum MUTEC Drive Capability VA=1.8 V

VA=3.0 V

TBD

mA MUTEC High-Level Output Voltage - VA - V MUTEC Low-Level Output Voltage - 0 - V

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supplies: Positive Analog

Headphone Line

Digital I/O Input Current, Any Pin Except Supplies I Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

VA_HP

VA_LINE

IND

stg

-0.3

4.0

V V V V

-±10mA

-0.3 VL+0.4 V

-55 125 °C

-65 150 °C

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages wit h resp ect to gro un d.)

Parameters Symbol Min Typ Max Units

Ambient Temperature T DC Power Supplies: Positive Analog

Headphone (Note 10)

Line

VA_HP

VA_LINE

Digital I/O

Notes: 10. To prevent clipping the outputs, VA_HP

VA_HP must be 200 mV greater than V

is limited by the Full-Scale Output Voltage V

MIN

. However, if distortion is not a concern, VA_HP may be

FS_HP

as low as 0.9 V at any time.

-10 - 70 °C

1.7

0.9 VA

1.7

3.6

FS_HP

V V V V

, where

DS481PP1 9

CS43L42

SWITCHING CHARACTERISTICS (T

Logic 1 = VL, C

=20pF)

= -10 to 70° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,

Parameters Symbol Min Typ Max Units

Input Sample Rate Base Rate Mode

High Rate Mode

Fs Fs

100

kHz

kHz MCLK Pulse Width High MCLK/LRCK = 1024 7 - - ns MCLK Pulse Width Low MCLK/LRCK = 1024 7 - - ns MCLK Pulse Width High MCLK/LRCK = 768 10 - - ns MCLK Pulse Width Low MCLK/LRCK = 768 10 - - ns MCLK Pulse Width High MCLK/LRCK = 512 15 - - ns MCLK Pulse Width Low MCLK/LRCK = 512 15 - - ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 25 - - ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 25 - - ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 35 - - ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 35 - - ns

External SCLK Mode

LRCK Duty Cycle (External SCLK only) 40 50 60 % SCLK Pulse Width Low t SCLK Pulse Width High t SCLK Period Base Rate Mode t

High Rate Mode t

SCLK rising to LRCK edge delay t SCLK rising to LRCK edge setup time t SDATA valid to SCLK rising setup time t SCLK rising to SDATA hold time t

sclkl

sclkh

sclkw sclkw

slrd

slrs

sdlrs

sdh

20 - - ns 20 - - ns

------------------- --128()Fs

------------------ 64()Fs

--ns

20 - - ns 20 - - ns 20 - - ns 20 - - ns

Internal SCLK Mode (Note 11)

LRCK Duty Cycle (Internal SCLK only) (Note 12) - 50 - % SCLK Period t

SCLK rising to LRCK edge t SDATA valid to SCLK rising setup time t

SCLK rising to SDATA hold time Base Rate Mode t

High Rate Mode t

sclkw

sclkr sdlrs

sdh

---------------- SCLK

--µs

------------------- --- 10+ 512()Fs

------------------ ----15+ 512()Fs

------------------ ----15+ 384()Fs

--ns

tsclkw

----------------- 2

--ns

Notes: 11. Internal SCLK Mode timing is not tested, but is guaranteed by design.

12. In Internal SCLK Mode, the LRCK duty cycle must be 50% +/− 1/ 2 MCLK Peri od.

10 DS481PP1

CS43L42

sclkh

slrs

slrd

sdlrs

sdh

sclkl

SDATA

SCLK

LRCK

sclkr

SDATA

sclkw

sdlrstsdh

*INTERNAL SCLK

Figure 1. External Serial Mode Input Timing Figure 2. Internal Serial Mode Input Timing

*The SCLK pulses shown are internal to the CS43L42.

MCLK

*INTERNAL SCLK

SDATA

LRCK

N 2

Figure 3. Internal Serial Clock Generation

* The SCLK pulses shown are internal to the CS43L42.

N equals MCLK divided by SCLK

DS481PP1 11

CS43L42

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE

(TA= 25° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL=30pF)

Parameter Symbol Min Max Unit

Two-Wire Mode (Note 13)

SCL Clock Frequency f

Rising Edge to Start t

RST Bus Free Time Between Transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling (Note 14) t SDA Setup time to SCL Rising t Rise Time of SCL t Fall Time SCL t Rise Time of SDA t Fall Time of SDA t Setup Time for Stop Condition t

scl irs

buf

hdst

low high sust

hdd

sud

rc fc rd fd

susp

-100kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs 0-µs

250 - ns

-25ns

-25ns 1µs

300 ns

4.7 - µs

Notes: 13. The Two-Wire Mode is compatible with the I

14. Data must be held for sufficient time to bridge the transition time, t

RST

irs

Stop Start

SDA

SCL

buf

hdst

low

high

hdd

Figure 4. Control Port Timing - Two-Wire Mode

C protocol.

sud

Repeated

Start

sust

hdst

, of SCL.

Stop

susp

12 DS481PP1

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(TA= 25° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL=30pF)

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f

Rising Edge to CS Falling t

RST CCLK Edge to CS

High Time Between Transmissions t

Falling to CCLK Edge t

Falling (Note 15) t

CCLK Low Time t CCLK High Time t CDIN to CCLK Rising Setup Time t CCLK Rising to DATA Hold Time (Note 16) t Rise Time of CCLK and CDIN (Note 17) t Fall Time of CCLK and CDIN (Note 17) t

sclk

srs

spi csh css

scl

sch dsu

-6MHz 500 - ns 500 - ns

1.0 - µs 20 - ns 66 - ns 66 - ns 40 - ns 15 - ns

-100ns

CS43L42

Notes: 15. t

16. Data must be held for sufficient time to bridge the transition time of CCLK.

17. For F

only needed before first falling edge of CS after RST rising edge. t

spi

< 1 MHz

SCK

RST

CCLK

CDIN

srs

css

spi

tr2t

scl

sch

= 0 at all other times.

spi

csh

dsu

Figure 5. Control Port Timing - SPI Mode

DS481PP1 13

+ 29 hidden pages

Cirrus Logic CS43L42-KZ, CS43L42 Datasheet

Features

Description

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

1. CHARACTERISTICS/SPECIFICATIONS

ANALOG CHARACTERISTICS (T

POWER AND THERMAL CHARACTERISTICS (GND = 0 V; All voltages with respect to

DIGITAL CHARACTERISTICS (T

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages wit h resp ect to gro un d.)

SWITCHING CHARACTERISTICS (T

Figure 1. External Serial Mode Input Timing Figure 2. Internal Serial Mode Input Timing

Figure 3. Internal Serial Clock Generation

Figure 4. Control Port Timing - Two-Wire Mode

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

Figure 5. Control Port Timing - SPI Mode