Cirrus Logic CS43L42-KZ, CS43L42 Datasheet

CS43L42

Low Voltage, Stereo DAC with Headphone Amp

Features

l 1.8 to 3.3 Volt su pply l 24-Bit conversion / 96 kHz sample rate l 96 dB dynamic range at 3 V supply l -85 dB THD+N l Low power consumption l Digital volume control

— 96 dB attenuation, 1 dB step size

l Digital bass and treble boost

— Selectable corner frequencies — Up to 12 dB boost in 1 dB increments

l Peak signal limiting to prevent clipping l De-emphasis for 32 kHz, 44.1 kHz, a nd 48 kHz l Headphone amplifier

— up to 25 mW — 25 dB analog attenuation and mute — Zero crossing click free level transitions

l ATAPI mixing functions l 24-Pin TSSOP package

* 1 kHz sine wave at 3.3V supply

power output into 16 Ω load*

rms

Description

The CS43L42 is a complete stereo digital-to-analog output system including interpolation, 1-bit D/A conversion, analog filtering, vo lu me c ontrol , li ne l eve l ou tput s, and a headphone amplifier, in a 24-pin TSSOP package.

The CS43L42 is based on delta-sigma modulation, where the modulator output cont rols the reference vo ltage input to an ultra-linear analog low -pass filter. This architectu re allo ws infin ite adju stme nt of the sa mple ra te between 2 kHz and 100 kHz simply by changing the master clock freque nc y.

The CS43L42 contain s on-chip digital ba ss and treble boost, peak signal limiting, and de-emphasis. The CS43L42 operates fr om a +1.8 V to +3.3 V supply and consumes only 16 mW of power with a 1.8 V supply with the line amplifier powered-down. These features are ideal for portable CD, MP3 and MD players and ot her portable playback systems that require extremely low power consumption.

ORDERING INFORMATION

CS43L42-KZ -10 to 70 °C 24-pin TSSOP CDB43L42 Evaluation Board

SCL/CCLK/DIF1 SDA/CDIN/DIF0

RST

VA VL

LRCK

Bass/Treble

SCLK/DEM1

SDATA

De-emphasis

Serial Port

GND

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

Control Port

Digital Volume Control

Boost

Limiting

AD0/CS/DEM0

MCLK

MUTEC

External

Mute Control

∆Σ

DAC

∆Σ

Digital Filters

DAC

FILT+ REF_GND VQ_LINE

Analog

Filter

Analog

Filter

VQ_HP

Analog Volume Control

a G

VA_HP

Amplifier

Headphone

Line

Compensation

Amplifier

VA_LINE

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

HP_A

HP_B

AOUTA

AOUTB

APR ‘00

DS481PP1

1. CHARACTERISTICS/SPECIFICATIONS .................................................................... 5

ANALOG CHARACTERISTICS................................................................................ 5

ANALOG CHARACTERISTICS................................................................................ 6

ANALOG CHARACTERISTICS................................................................................ 7

POWER AND THERMAL CHARACTERISTICS ...................................................... 8

DIGITAL CHARACTERISTICS................................................................................. 9

ABSOLUTE MAXIMUM RATINGS........................................................................... 9

RECOMMENDED OPERATING CONDITIONS....................................................... 9

SWITCHING CHARACTERISTICS ................................................. ....... ...... .......... 10

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE ...... 12

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE.................... 13

2. TYPICAL CONNECTION DIAGRAM ....................................................................... 14

3. REGISTER QUICK REFERENCE ......................................... ....... ...... ....... ................ 15

4. REGISTER DESCRIPTION ................... ....... ...... ............................................. ....... ... 1 6

4.1 Power and Muting Control (address 01h)....................................................... 16

4.1.1 Auto-mute (AMUTE) ..................................................................................... 16

4.1.2 Soft Ramp AND Zero Cross CONTROL (SZC)............................................. 16

4.1.3 Popguard® Transient Control (POR)............................................................ 17

4.1.4 Power Down Headphone Amplifier (PDNHP)................................................ 17

4.1.5 Power Down Line Amplifier (PDNLN)............................................................ 17

4.1.6 Power Down (PDN) ....................................................................................... 17

4.2 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA).. 18

4.3 Channel B Analog Headphone Attenuation Control (address 03h) (hVOLB).. 18

4.4 Channel A Digital Volume Control (address 04h) (DVOLA) ............................ 18

4.5 Channel B Digital Volume Control (address 05h) (DVOLB) ............................ 18

4.6 Tone Control (address 06h)............................................................................. 19

4.6.1 Bass Boost Level (BB).................................. .............................................. ... 19

4.6.2 Treble Boost Level (tb) .................................................................................. 19

4.7 Mode Control (address 07h)............................................................................ 20

4.7.1 Bass Boost Corner Frequency (bbcf) ............................................................ 20

4.7.2 Treble Boost Corner Frequency (TBCF)........................................................ 20

4.7.3 Channel A Volume = Channel B Volume (A=B) ............................................ 20

4.7.4 De-Emphasis Control (DEM)......................................................................... 21

4.7.5 Digital Volume Control Bypass (VCBYP)....................................................... 21

4.8 Limiter Attack Rate (address 08h) (ARATE).................................................... 21

4.9 Limiter Release Rate (address 09h) (RRATE) ............................................ 22

CS43L42

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

I2C is a registered trademark of Ph ilips Semiconductors. Preliminary product inf o rmation describes products whi ch are i n production, but for whi c h ful l characterization data is not yet available. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best effort s to ensure that the information contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. Ite ms f rom any Ci rrus L ogi c websi t e or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2 DS481PP1

CS43L42

4.10 Volume and Mixing Control (address 0Ah).....................................................22

4.10.1 Tone Control MODE (TC).............................................................................22

4.10.2 Tone Control Enable (TC_EN) .....................................................................22

4.10.3 Peak Signal Limiter Enable (LIM_EN)..........................................................23

4.10.4 ATAPI Channel Mixing and Muting (atapi) ...................................................23

4.11 Mode Control 2 (address 0Bh) .......................................................................24

4.11.1 Master Clock DIVIDE ENABLE (mclkdiv).....................................................24

4.11.2 Line Amplifier Gain Compensation (line)......................................................24

4.11.3 Digital Interface Format (dif).........................................................................24

5. PIN DESCRIPTION .......................... ...... ............................................. ....... ...... ....... ....26

6. APPLICATIONS .........................................................................................................29

6.1 Grounding and Power Supply Decoupling ......................................................29

6.2 Clock Modes ....................................................................................................29

6.3 De-Emphasis ...................................................................................................29

6.4 Recommended Power-up Sequence ..............................................................29

6.5 PopGuard® Transient Control .........................................................................29

7. CONTROL PORT INTERFACE ....... ...... ....... ...... ...... .............................................. ....30

7.1 SPI Mode .........................................................................................................30

7.2 Two-Wire Mode ...............................................................................................30

7.3 Memory Address Pointer (MAP) .............................................................31

7.3.1 INCR (Auto Map Increment Enable)...............................................................31

7.3.2 MAP0-3 (Memory Address Pointer) ...............................................................31

8. PARAMETER DEFINITIONS ......................................................................................39

9. REFERENCES ............................................................................................................39

10. PACKAGE DIMENSIONS .......................................................................................40

LIST OF FIGURES

Figure 1. External Serial Mode Input Timing ......................................................................... 11

Figure 2. Internal Serial Mode Input Timing ............. ...... ............................................. ....... ... 1 1

Figure 3. Internal Serial Clock Generation .. ...... ....... ...... ...... ....... ...... ....... ............................. 11

Figure 4. Control Port Timing - Two-Wire Mode .................................................................... 12

Figure 5. Control Port Timing - SPI Mode ............................................................................. 13

Figure 6. Typical Connection Diagram ................................. ....... ...... .................................... 14

Figure 7. Control Port Timing, SPI mode ............................................................................... 31

Figure 8. Control Port Timing, Two-Wire Mode ..................................................................... 31

Figure 9. Base-Rate Stopband Rejection .............................................................................. 32

Figure 10. Base-Rate Transition Band .................................................................................. 32

Figure 11. Base-Rate Transition Band (Detail) ...................................................................... 32

Figure 12. Base-Rate Passband Ripple ................................................................................ 32

Figure 13. High-Rate Stopband Rejection ............................................................................. 32

Figure 14. High-Rate Transition Band ................................................................................... 32

Figure 15. High-Rate Transition Band (Detail) ...................................................................... 33

Figure 16. High-Rate Passband Ripple ................................................................................. 33

Figure 17. Line Output Test Load .......................................................................................... 33

Figure 18. Headphone Output Test Load .............................................................................. 33

Figure 19. CS43L42 Control Port Mode - Serial Audio Format 0 .......................................... 34

Figure 20. CS43L42 Control Port Mode - Serial Audio Format 1 .......................................... 34

Figure 21. CS43L42 Control Port Mode - Serial Audio Format 2 .......................................... 34

Figure 22. CS43L42 Control Port Mode - Serial Audio Format 3 .......................................... 35

Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4 .......................................... 35

Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5 .......................................... 35

Figure 25. CS43L42 Control Port Mode - Serial Audio Format 6 .......................................... 36

Figure 26. CS43L42 Stand Alone Mode - Serial Audio Format 0 .......................................... 36

DS481PP1 3

Figure 27. CS43L42 Stand Alone Mode - Serial Audio Format 1 ..........................................36

Figure 28. CS43L42 Stand Alone Mode - Serial Audio Format 2 ..........................................37

Figure 29. CS43L42 Stand Alone Mode - Serial Audio Format 3 ..........................................37

Figure 30. De-Emphasis Curve ..............................................................................................38

Figure 31. ATAPI Block Diagram ........................................................................................... 38

LIST OF TABLES

Table 1. Example Analog Volume Settings ............................................................................ 18

Table 2. Example Digital Volume Settings ............................................................................. 19

Table 3. Example Bass Boost Settings .................................................................................. 19

Table 4. Example Treble Boost Settings ................................................................................ 19

Table 5. Example Limiter Attack Rate Settings ...................................................................... 21

Table 6. Example Limiter Release Rate Settings .................................................................. 22

Table 7. ATAPI Decode ......................................................................................................... 23

Table 8. Digital Interface Format ............................................................................................ 25

Table 9. Stand Alone De-Emphasis Control .......................................................................... 27

Table 10. HRM Common Clock Frequencies ........................................................................ 27

Table 11. BRM Common Clock Frequencies ......................................................................... 27

Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode) ............................. 28

CS43L42

4 DS481PP1

1. CHARACTERISTICS/SPECIFICATIONS

CS43L42

ANALOG CHARACTERISTICS (T

Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz. Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz. Test load R ure 18) for headphone out).

Parameter

=10kΩ, CL= 10 pF (see Figure 17) for line out, RL=16Ω, CL = 10 pF (see Fig-

= 25° C; Logic "1" = VL = 1.8 V; Logic "0" = GND = 0 V;

Base-rate Mode High-Rate Mode

Symbol Min Typ Max Min Typ Max Unit

Line Output Dynamic Performance for VA = VA_LINE = 1.8 V

Dynamic Range (Note 1)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 100 - - 100 - dB

THD+N

TBD TBD

91 94 89 92

-80

-71

-31

-78

-69

-29

TBD

TBD TBD

89 92 87 90

-80

-69

-29

-78

-67

-27

TBD

dB dB dB dB

dB dB dB dB dB dB

Headphone Output Dynamic Performance for VA = VA_HP = 1.8 V

Dynamic Range (Note 1)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 1)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 66 - - 66 - dB

THD+N

TBD TBD

88 91 86 89

-82

-68

-28

-80

-66

-26

TBD

TBD TBD

88 91 86 89

-85

-68

-28

-83

-66

-26

TBD

dB dB dB dB

dB dB dB dB dB dB

Notes: 1. One-half LSB of triangular PDF dither is added to data.

DS481PP1 5

CS43L42

ANALOG CHARACTERISTICS (Continued)

Base-rate Mode High-Rate Mode

Parameter

Line Output Dynamic Performance for VA = VA_LINE = 3.0 V

Dynamic Range. (Note 1)

18 to 24-Bit. unweighted

A-Weighted

16-Bit. unweighted

A-Weighted

Total Harmonic Distortion + Noise. (Note 1)

18 to 24-Bit. 0 dB

-20 dB

-60 dB

16-Bit. 0 dB

-20 dB

-60 dB

Interchannel Isolation. (1 kHz) - 100 - - 100 - dB

Headphone Output Dynamic Performance for VA = VA_HP = 3.0 V

Dynamic Range. (Note 1)

18 to 24-Bit. unweighted

A-Weighted

16-Bit. unweighted

A-Weighted

Total Harmonic Distortion + Noise. (Note 1)

18 to 24-Bit. 0 dB

-20 dB

-60 dB

16-Bit. 0 dB

-20 dB

-60 dB

Interchannel Isolation. (1 kHz) - 66 - - 66 - dB

Symbol Min T yp Max Min Typ Max Unit

TBD TBD

THD+N

TBD TBD

THD+N

93 96 91 94

-85

-73

-33

-83

-71

-31

90 93 88 91

-76

-70

-30

-74

-68

-28

TBD

TBD TBD

93 96 91 94

-85

-73

-33

-83

-71

-31

90 93 88 91

-73

-70

-30

-71

-68

-28

TBD

dB dB dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB dB dB dB dB

6 DS481PP1

CS43L42

ANALOG CHARACTERISTICS (Continued)

Parameters Symbol Min Typ Max Units

Analog Output

Full Scale Line Output Voltage (Note 2) V Line Output Quiescent Voltage V Full Scale Headphone Output Voltage V Headphone Output Quiescent Voltage V Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C

Maximum Line Output AC-Current VA=VA_LINE=1.8 V

VA=VA_LINE=3.0 V

Maximum Headphone Output VA=VA_HP=1.8 V AC-Current VA=VA_HP=3.0 V

FS_LINE

Q_LINE

FS_HP

Q_HP

LINE

Base-rate Mode High-Rate Mode

Parameter

Combined Digital and On-chip Analog Filter Response (Note 3)

Passband (Note 4)

to -0.05 dB corner

to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz

(Note 5) StopBand .5465 - - .577 - - Fs StopBand Attenuation (Note 6) 50 - - 55 - - dB Group Delay tgd - 9/Fs - - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz

0 - 20 kHz

De-emphasis Error Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

Symbol Min Typ Max Min Typ Max Unit

-.02 - +.08 0 - +0.11 dB

--±0.36/Fs

TBD G x VA TBD Vpp

- 0.5 x VA_LINE - VDC

TBD 0.55 x VA TBD Vpp

- 0.5 x VA_HP - VDC

.4535

.4998

+.2/-.1

+.05/-.14

+0/-.22

0.1

0.15 31

0 0

--±1.39/Fs

±0.23/Fs--

(Note 7)

.4426 .4984

mA mA

Fs Fs Fs

s s

dB dB dB

Notes: 2. See

3. Filter response is not tested but is guaranteed by design.

4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9-16) have

5. Referenced to a 1 kHz, full-scale sine wave.

6. For Base-Rate Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.

7. De-empha si s is not availab le in High - Rate Mode.

DS481PP1 7

Line Amplifier Gain Compensation (line)

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

For High-Rate Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

for details.

CS43L42

POWER AND THERMAL CHARACTERISTICS (GND = 0 V; All voltages with respect to

ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current- VA =1.8 V Normal Operation VA_HP=1.8 V

VA_LINE=1.8 V

A_LINE

VL=1.8 V

Power Supply Current- VA =1.8 V Power Down Mode (Note 8) VA _HP=1.8 V

VA_LINE=1.8 V

A_LINE

VL=1.8 V

Power Supply Current- VA =3.0 V Normal Operation VA_HP=3.0 V

VA_LINE=3.0 V

A_LINE

VL=3.0 V

Power Supply Current- VA =3.0 V Power Down Mode (Note 8) VA _HP=3.0 V

VA_LINE=3.0 V

A_LINE

VL=3.0 V

Total Power Dissipation- All Supplies=1.8 V Normal Operation All Supplies=3.0 V

Maximum Headphone Power Dissipation (1 kHz full-scale sine wave VA=1.8 V into 16 ohm load) VA=3.0 V

Package Thermal Resistance θ Power Supply Rejection Ratio (Note 9) (1 kHz)

PSRR -

(60 Hz)

A_HP

D_L

A_HP

D_L

A_HP

D_L

A_HP

D_L

7.3

1.5

1.6 4

TBD TBD TBD TBD

10.5

1.5

1.7

9.3

TBD TBD TBD TBD

19 41

TBD TBD

mA mA mA

µA µA

µA µA µA

mA mA mA

µA µA

µA µA µA

mW mW

- 75 - °C/Watt 60

dB dB

Notes: 8. Power Down Mode is defined as RST

= LO with all clocks and data lines held static.

9. Valid with the recommended capacitor values on FILT+, VQ_LINE and VQ_HP as shown in Figure 6. Increasing the capacitance will also increase the PSRR. Note that care should be taken when selecting capacitor type, as any leakage current in excess of 1.0 µA will cause degradation in analog

performance.

8 DS481PP1

CS43L42

DIGITAL CHARACTERISTICS (T

= 25° C; VL = 1.7 V - 3.6 V; GND = 0 V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage Low-Level Input Voltage Input Leakage Current I

0.7 x VL - - V

- - 0.3 x VL V

--±10µA Input Capacitance - 8 - pF Maximum MUTEC Drive Capability VA=1.8 V

VA=3.0 V

TBD

mA MUTEC High-Level Output Voltage - VA - V MUTEC Low-Level Output Voltage - 0 - V

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supplies: Positive Analog

Headphone Line

Digital I/O Input Current, Any Pin Except Supplies I Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

VA_HP

VA_LINE

IND

stg

-0.3

4.0

V V V V

-±10mA

-0.3 VL+0.4 V

-55 125 °C

-65 150 °C

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages wit h resp ect to gro un d.)

Parameters Symbol Min Typ Max Units

Ambient Temperature T DC Power Supplies: Positive Analog

Headphone (Note 10)

Line

VA_HP

VA_LINE

Digital I/O

Notes: 10. To prevent clipping the outputs, VA_HP

VA_HP must be 200 mV greater than V

is limited by the Full-Scale Output Voltage V

MIN

. However, if distortion is not a concern, VA_HP may be

FS_HP

as low as 0.9 V at any time.

-10 - 70 °C

1.7

0.9 VA

1.7

3.6

FS_HP

V V V V

, where

DS481PP1 9

CS43L42

SWITCHING CHARACTERISTICS (T

Logic 1 = VL, C

=20pF)

= -10 to 70° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,

Parameters Symbol Min Typ Max Units

Input Sample Rate Base Rate Mode

High Rate Mode

Fs Fs

100

kHz

kHz MCLK Pulse Width High MCLK/LRCK = 1024 7 - - ns MCLK Pulse Width Low MCLK/LRCK = 1024 7 - - ns MCLK Pulse Width High MCLK/LRCK = 768 10 - - ns MCLK Pulse Width Low MCLK/LRCK = 768 10 - - ns MCLK Pulse Width High MCLK/LRCK = 512 15 - - ns MCLK Pulse Width Low MCLK/LRCK = 512 15 - - ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 25 - - ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 25 - - ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 35 - - ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 35 - - ns

External SCLK Mode

LRCK Duty Cycle (External SCLK only) 40 50 60 % SCLK Pulse Width Low t SCLK Pulse Width High t SCLK Period Base Rate Mode t

High Rate Mode t

SCLK rising to LRCK edge delay t SCLK rising to LRCK edge setup time t SDATA valid to SCLK rising setup time t SCLK rising to SDATA hold time t

sclkl

sclkh

sclkw sclkw

slrd

slrs

sdlrs

sdh

20 - - ns 20 - - ns

------------------- --128()Fs

------------------ 64()Fs

--ns

20 - - ns 20 - - ns 20 - - ns 20 - - ns

Internal SCLK Mode (Note 11)

LRCK Duty Cycle (Internal SCLK only) (Note 12) - 50 - % SCLK Period t

SCLK rising to LRCK edge t SDATA valid to SCLK rising setup time t

SCLK rising to SDATA hold time Base Rate Mode t

High Rate Mode t

sclkw

sclkr sdlrs

sdh

---------------- SCLK

--µs

------------------- --- 10+ 512()Fs

------------------ ----15+ 512()Fs

------------------ ----15+ 384()Fs

--ns

tsclkw

----------------- 2

--ns

Notes: 11. Internal SCLK Mode timing is not tested, but is guaranteed by design.

12. In Internal SCLK Mode, the LRCK duty cycle must be 50% +/− 1/ 2 MCLK Peri od.

10 DS481PP1

CS43L42

sclkh

slrs

slrd

sdlrs

sdh

sclkl

SDATA

SCLK

LRCK

sclkr

SDATA

sclkw

sdlrstsdh

*INTERNAL SCLK

Figure 1. External Serial Mode Input Timing Figure 2. Internal Serial Mode Input Timing

*The SCLK pulses shown are internal to the CS43L42.

MCLK

*INTERNAL SCLK

SDATA

LRCK

N 2

Figure 3. Internal Serial Clock Generation

* The SCLK pulses shown are internal to the CS43L42.

N equals MCLK divided by SCLK

DS481PP1 11

CS43L42

SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE

(TA= 25° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL=30pF)

Parameter Symbol Min Max Unit

Two-Wire Mode (Note 13)

SCL Clock Frequency f

Rising Edge to Start t

RST Bus Free Time Between Transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling (Note 14) t SDA Setup time to SCL Rising t Rise Time of SCL t Fall Time SCL t Rise Time of SDA t Fall Time of SDA t Setup Time for Stop Condition t

scl irs

buf

hdst

low high sust

hdd

sud

rc fc rd fd

susp

-100kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs 0-µs

250 - ns

-25ns

-25ns 1µs

300 ns

4.7 - µs

Notes: 13. The Two-Wire Mode is compatible with the I

14. Data must be held for sufficient time to bridge the transition time, t

RST

irs

Stop Start

SDA

SCL

buf

hdst

low

high

hdd

Figure 4. Control Port Timing - Two-Wire Mode

C protocol.

sud

Repeated

Start

sust

hdst

, of SCL.

Stop

susp

12 DS481PP1

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(TA= 25° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL=30pF)

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f

Rising Edge to CS Falling t

RST CCLK Edge to CS

High Time Between Transmissions t

Falling to CCLK Edge t

Falling (Note 15) t

CCLK Low Time t CCLK High Time t CDIN to CCLK Rising Setup Time t CCLK Rising to DATA Hold Time (Note 16) t Rise Time of CCLK and CDIN (Note 17) t Fall Time of CCLK and CDIN (Note 17) t

sclk

srs

spi csh css

scl

sch dsu

-6MHz 500 - ns 500 - ns

1.0 - µs 20 - ns 66 - ns 66 - ns 40 - ns 15 - ns

-100ns

CS43L42

Notes: 15. t

16. Data must be held for sufficient time to bridge the transition time of CCLK.

17. For F

only needed before first falling edge of CS after RST rising edge. t

spi

< 1 MHz

SCK

RST

CCLK

CDIN

srs

css

spi

tr2t

scl

sch

= 0 at all other times.

spi

csh

dsu

Figure 5. Control Port Timing - SPI Mode

DS481PP1 13

2. TYPICAL CONNECTION DIAGRAM

CS43L42

1.8to3.3V Supply

*Ferrite

bead

1.0 µF 0.1 µF

*Ferrite

bead

1.0 µF 0.1 µF

Digital

Audio

Source

µc/

Mode

Configuration

MCLK

LRCK

SCLK/DEM1

SDATA

CP/SA

RST

SDA/CDIN/DIF0

SCL/CCLK/DIF1

AD0/CS/DEM0

0.1 µF

18 19 20

VA_LINE

VA VA_HP

CS43

AOUTA

AOUTB

MUTEC

VQ_HP

VQ_LINE

HP_A

HP_B

FILT+

*Ferrite

bead

220

3.3 µF

1.0 µ F

µF

Ω

560

Ω

0.9 to 3.3 V

Ω

Supply

4.7 µH

Mute

Circuit

Headphones

4πFs(R

Ω

Audio Output A

Audio Output B

+ 560

560)

* Optional

GND

REF_GND

1.0 µF

1.0 µ F

Figure 6. Typical Connection Diagram

14 DS481PP1

CS43L42

3. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

0h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

default

1h Power and Muting

Control

default

2h Channel A Analog

Headphone Attenuation Control

default

3h Channel B Analog

Headphone Attenuation Control

default

4h Channel A Digital

Volume Control

default

5h Channel B Digital

Volume Control

6h Tone Control BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0

7h Mode Control BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP

8h Limiter Attack Rate ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0

9h Limiter Release Rate RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0

Ah Volume and Mixing

Control

Bh Mode Control 2 MCLKDIV LINE1 LINE0 Reserved Reserved DIF2 DIF1 DIF0

default

00000000

AMUTE SZC1

HVOLA7 HVOL A6 HVOLA5 HVOLA4 HVOLA3 HVOLA2 HVOLA1 HVOLA0

00000000

HVOLB7 HVOL B6 HVOLB5 HVOLB4 HVOLB3 HVOLB2 HVOLB1 HVOLB0

00000000

DVOLA7 DVOL A6 DVOLA5 DVOLA4 DVOLA3 DVOLA2 DVOLA1 DVOLA0

00000000

DVOLB7 DVOL B6 DVOLB5 DVOLB4 DVOLB3 DVOLB2 DVOLB1 DVOLB0

00000000

00010000

00100000

TC1 TC0 TC_EN LIM_EN ATAPI3 ATAPI2 ATAPI1 ATAPI0

00001001

00000000

SZC0

POR PDNHP PDNLN PDN Reserved

10010

DS481PP1 15

CS43L42

4. REGISTER DESCRIPTION

Note: All registers are read/write in Two-Wire mode and write only in SPI, unless otherwise noted.

4.1 Power and Muting Control (address 01h)

76543210

AMUTE SZC1 SZC0 POR PDNHP PDNLN PDN RESERVED

11010010

4.1.1 AUTO-MUTE (AMUTE)

Default = 1

0 - Disabled 1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.

4.1.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10

00 - Immediate Change 01 - Zero Cross Digital and Analog 10 - Ramped Digital and Analog 11 - Reserved

Function:

Immediate Change

When Immediate Change is selected all level changes will take effect immediately in one step.

Zero Cross Digital and Analog

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

Ramped Digital and Analog

Soft Ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Analog level changes will occur in 1 dB steps on a signal zero crossing. The analog level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

Note: Ramped Digital and Analog is not available in High-Rate Mode.

16 DS481PP1

4.1.3 POPGUARD® TRANSIENT CONTROL (POR)

Default - 1

0 - Disabled 1 - Enabled

Function:

The PopGuard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. Please see section 6.5 for implementation details.

4.1.4 POWER DOWN HEADPHONE AMPLIFIER (PDNHP)

Default = 0

0 - Disabled 1 - Enabled

Function:

The headphone amplifier will independently enter a low-power state when this function is enabled.

4.1.5 POWER DOWN LINE AMPLIFIER (PDNLN)

CS43L42

Default = 0

0 - Disabled 1 - Enabled

Function:

The line output amplifier will independently enter a low-power state when this function is enabled.

4.1.6 POWER DOWN (PDN)

Default = 1

0 - Disabled 1 - Enabled

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the control

registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin.

DS481PP1 17

CS43L42

4.2 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA)

4.3 Channel B Analog Headphone Attenuation Control (address 03h) (hVOLB)

76543210

HVOLx7 HVOLx6 HVOLx5 HVOLx4 HVOLx3 HVOLx2 HVOLx1 HVOLx0

00000000

Default = 0 dB (No attenuation)

Function:

The Analog Headphone Attenuation Control operates independently from the Digital Volume Control. The Analog Headphone Attenuation Control registers allow attenuation of the headphone output signal for

each channel in 1 dB increments from 0 to -25 dB. Attenuation settings are decoded using a 2’s complement code, as shown in Table 1. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. All volume settings greater than zero are interpreted as zero.

Note: The Analog Headphone Attenuation only affects the headphone outputs.

Binary Code Decimal Value Volume Setting

00000000 0 0 dB

11110110 -10 -10 dB 11110001 - 15 -15 dB

Table 1. Example Analog Volume Settings

4.4 Channel A Digital Volume Control (address 04h) (DVOLA)

4.5 Channel B Digital Volume Control (address 05h) (DVOLB)

76543210

DVOLx7 DVOLx6 DVOLx5 DVOLx4 DVOLx3 DVOLx2 DVOLx1 DVOLx0

00000000

Default = 0 dB (No attenuation)

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from +18 to -96 dB. Volume settings are decoded using a 2’s complement code, as shown in Table 2. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. All volume settings less than -96 dB are equivalent to muting the channel via the ATAPI bits (see Section 4.10.4).

Note: The digital volume control affects both the line outputs and the headphone outputs. Setting this

18 DS481PP1

CS43L42

Binary Code Decimal Value Volume Setting

00001010 12 +12 dB

00000111 7 +7 dB 00000000 0 0 dB 11000100 -60 -60 dB 10100110 -90 -90 dB

Table 2. Example Digita l Volume Settings

4.6 Tone Control (address 06h)

76543210

BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0

00000000

4.6.1 BASS BOOST LEVEL (BB)

Default = 0 dB (No Bass Boost)

Function:

The level of the shelving bass boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 3. Levels above +12 dB are interpreted as +12 dB.

Binary Code Decimal Value Boost Setting

0000 0 0 dB 0010 2 +2 dB 1010 6 +6 dB 1001 9 +9 dB 1100 12 +12 dB

Table 3. Example Bass Boost Settings

4.6.2 TREBLE BOOST LEVEL (TB)

Default = 0 dB (No Treble Boo st )

Function:

The level of the shelving treble boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 4. Levels above +12 dB are interpreted as +12 dB.

Note: Treble Boost is not available in High-Rate Mode.

Binary Code Decimal Value Boost Setting

0000 0 0 dB 0010 2 +2 dB 1010 6 +6 dB 1001 9 +9 dB 1100 12 +12 dB

Table 4. Example Treble Boost Settings

DS481PP1 19

CS43L42

4.7 Mode Control (address 07h)

76543210

BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP

00000000

4.7.1 BASS BOOST CORNER FREQUENCY (BBCF)

Default = 00

00 - 50 Hz 01 - 100 Hz 10 - 200 Hz 11 - Reserved

Function:

The bass boost corner frequency is user selectable as shown above.

4.7.2 TREBLE BOOST CORNER FREQUENCY (TBCF)

Default = 00

00 - 2 kHz 01 - 4 kHz 10 - 7 kHz 11 - Reserved

Function:

The treble boost corner frequency is user selectable as shown above.

Note: Treble Boost is not available in High-Rate Mode.

4.7.3 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)

Default = 0

0 - Disabled 1 - Enabled

Function:

The AOUTA/HP_A and AOUTB/HP_B volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA/HP_A and AOUTB/HP_B are determined by the A Channel Attenuation and Volume Control Bytes, and the B Channel Bytes are ignored when this function is enabled.

20 DS481PP1

4.7.4 DE-EMPHASIS CONTROL (DEM)

Default = 00

00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz

Function:

Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 30)

Note: De-emphasis is not available in High-Rate Mode.

4.7.5 DIGITAL VOLUME CONTROL BYPASS (VCBYP)

Default = 0

0 - Disabled 1 - Enabled

Function:

The digital volume control section is bypassed when this function is enabled. This disables the digital volume control, muting, bass boost, treble boost, limiting and ATAPI functions. The analog headphone attenuation control will remain functional.

CS43L42

4.8 Limiter Attack Rate (address 08h) (ARATE)

76543210

ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0

00010000

Default = 10h - 2 LRCK’s per 1/8 dB

Function:

The limiter attack rate is user selectable. The rate is a function of sampling frequency, Fs, and the value in the Limiter Attack Rate register. Rates are calculated using the function RATE = 32/{value}, where

{value} is the decimal value in the Limiter Attack Rate register and RATE is in LRCK’s per 1/8 dB of change.

Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.

Use the LIM_EN bit to disable the limiter function (see

Peak Signal Limiter Enable (LIM_EN)

Binary Code Decimal Value LRCK’s per 1/8 dB

00000001 1 32 00010100 20 1.6 00101000 40 0.8

00111100 60 0.53 01011010 90 0.356

Table 5. Example Limiter Attack Rate Settings

DS481PP1 21

CS43L42

4.9 Limiter Release Rate (address 09h) (RRATE)

76543210

RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0

00100000

Default = 20h - 16 LRCK’s per 1/8 dB

Function:

The limiter release rate is user selectable. The rate is a function of sampling frequency, Fs, and the value in the Limiter Release Rate register. Rates are calculated using the function RATE = 512/{value}, where

{value} is the decimal value in the Limiter Release Rate register and RATE is in LRCK’s per 1/8 dB of change.

Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.

Use the LIM_EN bit to disable the limiter function (see

Binary Code Decimal Value LRCK’s per 1/8 dB

00000001 1 512 00010100 20 25 00101000 40 12

00111100 60 8

01011010 90 5

Table 6. Example Limiter Release Rate Settings

Peak Signal Limiter Enable (LIM_EN)

4.10 Volume and Mixing Control (address 0Ah)

76543210

TC1 TC0 TC_EN LIM_EN ATAPI3 ATAPI2 ATAPI1 ATAPI0

00001001

4.10.1 TONE CONTROL MODE (TC)

Default = 00

00 - All settings are taken from user registers 01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz 10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz 11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz

Function:

The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured. The user defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used when these bits are set to ‘00’. Alternately, one of three pre-defined settings may be used.

4.10.2 TONE CONTROL ENABLE (TC_EN)

Default = 0

0 - Disabled 1 - Enabled

Function:

The Bass Boost and Treble Boost features are active when this function is enabled.

22 DS481PP1

4.10.3 PEAK SIGNAL LIMITER ENABLE (LIM_EN)

Default = 0

0 - Disabled 1 - Enabled

Function:

The CS43L42 will limit the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is still clipping, the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate register.

Once the signal has dropped below the clipping level, the attenuation is decreased back to the user selected le vel fo llow ed by the Ba ss Boo st be ing i ncre ased back t o the user selec ted l evel. The relea se rat e is determined by the Limiter Release Rate register.

Note: The A=B bit should be set to ‘1’ for optimal limiter performance.

4.10.4 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

Default = 1001 - AOUTA/HP_A = L, AOUTB/HP_B = R (Stereo)

Function:

The CS43L42 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 7 and Figure 31 for additional information .

CS43L42

Note: All mixing functions occur prior to the digital volume control.

ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTA/HP_A AOUTB/HP_B

0000 MUTE MUTE 0001 MUTE R 0010 MUTE L 0011 MUTE [(L+R)/2] 0100 R MUTE 0101 R R 0110 R L 0111 R [(L+R)/2] 1000 L MUTE 1001 L R 1010 L L 1011 L [(L+R)/2] 1100[(L+R)/2] MUTE 1101[(L+R)/2] R 1110[(L+R)/2] L 1111[(L+R)/2][(L+R)/2]

Table 7. ATAPI Decode

DS481PP1 23

CS43L42

4.11 Mode Control 2 (address 0Bh)

76543210

MCLKDIV LINE1 LINE0 RESERVED RESERVED DIF2 DIF1 DIF0

00000000

4.11.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0

0 - Disabled 1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry.

Note: Internal SCLK is not available when this function is enabled.

4.11.2 LINE AMPLIFIER GAIN COMPENSATION (LINE)

Default = 00

00 - 0.785 x VA 01 - 0.943 x VA 10 - 1.571 x VA 11 - Line Mute

Function:

The Line Amplifier Gain Compensation bits allow the user to scale the full-scale line output level according to the power supply voltage used. The full-scale line output level will be equal to {gain factor}xVA, where {gain factor} is selected from options above. For example, if the user wants the full-scale line output voltage to be 1 V

1.571.

Note: It is possible to exceed the maximum output level, limited by VA_LINE, by incorrectly setting the

gain compensation factor.

The Line Mute option is available to allow muting of the line output when the headphone output is still in use and the line amp is still powered up. To use this feature, first mute the outputs via the ATAPI bits. Next, set the LINE GAIN to Line Mute. Finally, un-mute the outputs with the ATAPI bits. Following these steps will ensure a click free mute.

4.11.3 DIGITAL INTERFACE FORMAT (DIF)

(2.8 VPP) with VA = 1.8 VDC and VA_LINE = 3.0 VDC, then the gain factor would be

RMS

Default = 000 - Format 0 (I2S, up to 24-bit data, 64 x Fs Internal SLCK)

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 19-25.

Note: Internal SCLK is not available when MCLKDIV is enabled.

24 DS481PP1

CS43L42

DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE

000 001 010 011 100 101 110 111

S, up to 24-bit data, 64 x Fs Internal SLCK

S, up to 24-bit data, 32 x Fs Internal SLCK Left Justified, up to 24-bit data, Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 16-bit data Right Justified, 18-bit data Identical to Format 1

019 120 221 322 423 524 625 120

Table 8. Digital Interface Format

DS481PP1 25

5. PIN DESCRIPTION

CS43L42

Reset RST MUTEC Mute Control

Left/Right Clock LRCK AOUTA Analog Output A

Serial Data SDATA AOUTB Analog Output B

AD0/CS

Serial Clock/DEM1 SCLK/DEM1 VA_HP Headphone Amp Power

Interface Power VL VA_LINE Line Amp Power

SCL/CCLK/DIF1 SCL/CCLK/DIF1 GND Ground

SDA/CDIN/DIF0 SDA/CDIN/DIF0 HP_A Headphone Output A

No Connection N.C. VQ_LINE Line Out Quiescent Voltage

HP Quiescent Voltage VQ_HP REF_GND Reference Gro und

/DEM0 AD0/CS/DEM0 HP_B Headphone Output B

Master Clock MCLK VA Analog Power

Mode Select CP/SA

1 2

2 3 4 5

5 6

6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

FILT+ Positive Voltage Reference

RST 1 Reset (

LRCK 2 Left/Right Clock (

SDATA 3 Serial Audio Data (

AD0/CS (Control Port Mode)

SCLK 5 Serial Clock (

4 Address Bit / Chip Select (

Input

) - The device enters a low power mode and all internal registers are reset to their default settings, including the control port, when low. When high, the control port becomes operational and the PDN bit must be cleared before normal operation will occur. The control port cannot be accessed when Reset is low.

Input

) - Determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be equal to the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period difference. The required relations hip between the Left/Rig ht clock, ser ial clock and serial data is defined by the Mode Contro l 2 (0Bh) regist er when in Con trol Port Mode or by the DIF1-0 pins when in Stand-Alone mode. The options are detailed in Figures 19-29.

Input

) - Two’ s complem ent MSB-firs t serial data is i nput on th is pin. Th e data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is de fined by the Mode C ontrol 2 (0Bh) re giste r when in Con trol Port Mode or by the DIF1-0 pins when in Stand-Alone mode. The options are detailed in Figures 19-29.

Input

) - In Two-Wire mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain in SPI mode until either the part is reset or power is removed.

Input

) - Clocks the individual bits of the serial data into the SDATA pin. The required relations hip be tween th e Left/Ri ght cl ock, serial cloc k and serial dat a is def ined b y the Mode Control 2 (0Bh) register whe n in Control Port Mode or by the DIF1-0 pins when in Stand-Alone mode. The options are detailed in Figures 19-29. The CS43L42 supports both intern al and externa l serial clock gene ration mo des. The Internal Serial Clock Mode eliminates possible clock interference from an external SCLK. Use of the Internal Serial Clock Mode is always preferred.

Internal Serial Clock Mode

derived and synchronous with the master clock and left/right clock. The SCLK/LRCK frequency ratio is either 3 2, 48, or 64 dep ending up on the Mode C ontrol 2 (0Bh) re gister when in Control Port Mode or the DIF1-0 pins when in Stand-Alone mode as shown in Figures 19-29. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK.

External Serial Clock Mode

ever 16 low to h igh tr ansition s are detec ted on t he SC LK pin duri ng any phase of th e LR CK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.

- In the Internal Serial Clock Mode, the serial clock is internally

- The CS43L42 will enter th e Extern al Seria l Clock Mo de when-

26 DS481PP1

CS43L42

DEM0 and DEM1 (Stand-Alone Mode)

4 and 5 De-emphasis Con trol (

15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sam ple rates. (see Figure 30) When using Interna l Seri al C l oc k M ode , Pin5 is available for de-emphasis c ontr ol, DEM1, and all de-emphasis filters are available. When using External Serial Clock Mode, Pin 5 is not available for de-emphasis use and only the 44.1 kHz de-emphasis filter is available. (see Table 9)

Note: De-emphasis is not available in High-Rate Mode.

DEM1 DEMO DESCRIPTION DEMO DESCRIPTION

00 01 10 11

VL 6 Interface Power ( MCLK 7 Master Clock (

sample rate in Base Rate Mode (BR M) and 128x, 192 x, 256x or 38 4x the input s ample rate in High Rate Mode (HRM). Note that some multiplication factors require setting the MCLKDIV bit (see several standard audio sample rates and the required master clock frequencies.

Sample Rate

(kHz)

32 4.0960 6.1440 8.1920 12.2880

44.1 5.6448 8.4672 11.2896 16.9344 48 6.1440 9.2160 12.2880 18.4320 64 8.1920 12.2880 16.3840 24.5760

88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640

Input

) - Selects the app ropriate d igital filter to maintain the standa rd

Internal SCLK

External SCLK

Disabled 0 Disabled

44.1kHz 1 44.1 kHz 48kHz 32kHz

Table 9. Stand Alone De-Emphasis Control

Input

) - Digital interface power supply. Typically 1.8 to 3.3 VDC.

) - Frequency must be ei ther 256x, 384x , 512x, 768x or 1 024x the input

Master Clock DIVIDE ENABLE (mclkdiv)

MCLK (MHz)

HRM

128x 192x 256x* 384x*

). Tables 10 and 11 illustrate

* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).

Table 10. HRM Common Clock Frequencies

Sample Rate

(kHz)

32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 32.7680 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520

* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).

256x 384x 512x 768x* 1024x*

MCLK (MHz)

BRM

Table 11. BRM Common Clock Frequencies

Input

SCL/CCLK (Control Port Mode)

SDA/CDIN (Control Port Mode)

8 Serial Control Interface Clock (

SDA/CDIN.

9 Serial Control Data I/O (

the input data line for the control port interface in SPI mode.

Input/Output

) - Clocks the serial control data into or out of

) - In Two-Wire mode, SDA is a data I/O line. CDIN is

DS481PP1 27

CS43L42

DIF1 and DIF0 (Stand-Alone Mode)

8 and 9 Digital Interface Format (

serial clock and seri al data is de fined by the Digital Interface Format and the options are detailed in Figures 26-29.

DIF1 DIF0 DESCRIPTION FORMAT FIGURE

00 01 10 11

S, up to 24-bit data Left Justified, up to 24-bit data Right Justified, 24-bit Data Right Justified, 16-bit Data

Input

) - The required relationship between the Left/Right clock,

026 127 228 329

Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode)

N.C. 10 No Connection - This pin has no internal connection to the device. CP/SA

VQ_HP 12 Headphone Quiescent Voltage (

REF_GND 13 Reference Ground (

FILT+ 14 Positive Voltage Referen ce (

VQ_LINE 15 Line Out Quiescent Voltage (

HP_A and HP_B 16 and 21 Headphone Outputs (

GND 17 Ground ( VA 18 Analog Power ( VA_LINE 19 Line Amp Power (

11 Mode Select (

mode. When high, the CS43L42 wil l operate in control port mod e. When low, th e CS43L42 will operate in stand-alone mode.

quiescent reference voltage. A capacitor must be co nnected from VQ_HP to analog gro und, as shown in Figure 6. VQ _HP is no t intend ed to s upply externa l current. VQ _HP has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance.

connected to analog ground.

external capacitor is required from FILT+ to analog ground, as shown in Figure 6. The recommended value w ill typically provi de 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance.

erence voltage. A capa citor mus t be connecte d from VQ_L INE to analog ground, as sh own in Figure 6. VQ_LINE is not intended to supply external current. VQ_LINE has a typical source impedance of 250 kΩ and any current drawn from this pin will alter device performance.

the Analog Characteristics specifications table.

Input

) - The Mode Select pin is used to select control port or stand-alone

Output

) - Filter connection for internal headphone amp

Input

) - Ground reference for the internal sampling circuits. Must be

Output

) - Positive reference for internal sampling circui ts. An

Output

) - Filter connectio n for internal line amp quiescent ref-

Output

) - The full scale analog headphone output level is speci fied in

Input

) - Ground Reference. Should be connected to analog ground.

Input

) - Analog power supply. Typically 1.8 to 3.3VDC.

Input

) - Line amplifier power supply. Typically 1.8 to 3.3 VDC.

Note: If the line outputs are not used, connect VA_LINE to VA.

VA_HP 20 Headphone Amp Power (

3.3 VDC.

AOUTA and AOUTB 22 and 23 Analog Outputs (

Characteristics specifications table.

MUTEC 24 Mute Control (

set, muting, power-down or if the master clo ck to left/ri ght clock freq uency rati o is incorrect. This pin is intended to be used as a control for an external mute circuit on the line outputs to prevent the cli cks and po ps that c an occu r in any s ingle s upply sy stem. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.

Output

Input

) - Headphone amplifier power supply. Typically 0.9 to

) - The full scale analog line output level is specified in the Analog

) - The Mute Control pin goes high during power-up initialization, re-

28 DS481PP1

CS43L42

6. APPLICATIONS

6.1 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS43L42 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement with VA, VA_HP, VA_LINE and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin.

6.2 Clock Modes

The CS43L42 operates in one of two clocking modes. Base Rate Mode supports input sample rates up to 50 kHz, and High Rate Mode supports input sample rates up to 100 kHz, see Table 10 and

11. All clock modes use 64x oversampling.

6.3 De-Emphasis

The CS43L42 includes on-chip digital de-emphasis. Figure 30 shows the de-emphasis curve for Fs equal to 44.1 kHz. The fr equency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.

The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.

6.4 Recommended Power-up Sequence

1) Hold RST low until the power supply, master clock and left/right clock are stable. In this state, the control port is reset to its default settings and VQ_HP and VQ_LINE will remain low. Set the CP/SA pin at this time.

2) Bring RST high. The device will remain in a low power state and latch CP/SA, and VQ_HP and VQ_LINE remain low. If CP/SA is high, the control port will be accessible at this time

and the desired register settings can be loaded while keeping the PDN bit set to 1. If CP/SA is low, the device will begin the stand-alone power-up sequence

3) (For Control Port Mode) Once the registers are configured as desired, set the PDN bit to 0, initiating the power-up sequence. This requires

approximately 50 µS when the PopGuard

Transient Control (POR) bit is set to 0. If the POR bit is set to 1, see PopGuard® Transient Control for total power-up timing.

6.5 PopGuard® Transient Control

The CS43L42 uses PopGuard® technology to minimize the effects of output transients during power-up and power-down. This technique minimizes the audio transients commonly produced by single-ended, single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs.

When the device is initially powered-up, the audio outputs, AOUTA, AOUTB, HP_A and HP_B are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 left/right clock cycles later, the outputs reach V

Q_LINE

output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient.

To prevent transients at power-down, the device must first enter its power-down state. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTA, AOUTB, HP_A and HP_B. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once thi s charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on.

and V

respectively, and audio

Q_HP

DS481PP1 29

CS43L42

To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio output s are initially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 220 µF capacitor

and a 16 ohm load on the headphone outputs, the minimum power-down time will be approximately

0.4 seconds. Use of the Mute Control function on the line out-

puts is recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios only limited by the external mute circuit. See the CDB43L42 Datasheet for a suggested mute circuit.

7. CONTROL PORT INTERFACE

The control port is used to load all the internal settings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.

The control port has 2 modes: SPI and Two-Wire, with the CS43L42 operating as a slave device. If Two-Wire operation is desired, AD0/CS should be tied to VL or GND. If the CS43L42 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected.

7.1 SPI Mode

In SPI mode, CS is the CS43L42 chip select signal, CCLK is the control port bit cl ock, C DIN i s the input data line from the microcontroller and the chip address is 0010000. All signals are inputs and data is clocked in on the rising edge of CCLK. Figure 7 shows the operation of the control port in SPI

mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address and must be

0010000. The eighth bit is a read/write indicator

(R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into register designated by the MAP.

The CS43L42 has a MAP auto increment capability, enabled by the INCR bit in the MAP registe r. If INCR is a zero, then the MAP will stay constant for successive writes. If INCR is set to a 1, then MAP will auto increment after each byte is written, allowing block writes of successive registers.

7.2 Two-Wire Mode

In Two-Wire mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 8. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VL or GND as required. The upper 6 bits of the 7 bit address field must be 001000. To communicate with the CS43L42, the LSB of the chip address field, which is the first byte sent to the CS43L42, should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. If the operation is a read, the contents of the register pointed to by the MAP will be output after the chip address.

The CS43L42 has MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.

The Two-Wire mode is compatible with the I2C protocol.

30 DS481PP1

7.3 Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

7.3.1 INCR (AUTO MAP INCREMENT ENABLE)

Default = ‘0’ 0 - Disabled 1 - Enabled

7.3.2 MAP0-3 (MEMORY ADDRESS POINTER)

Default = ‘0000’

CS43L42

SDA

SCL

Start

CCLK

CDIN

001000

CHIP

ADDRESS

0010000

MAP = Memory Address Pointer

R/W

MAP

DATA

MSB

byte 1

Figure 7. Control Port Timing, SPI mode

Note 1

ADDR AD0

R/W

ACK

DATA 1-8

ACK

DATA 1-8

LSB

byte n

ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Figure 8. Control Port Timing, Two-Wire Mode

DS481PP1 31

CS43L42

Figure 9. Base-Rate Stopband Rejection Figure 10. Base-Rate Transition Band

Figure 11. Base-Rate Transition Band (Detail) Figure 12. Base-Rate Passband Ripple

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)

-10

-20

-30

-40

-50

-60

Amplitude dB

-70

-80

-90

-100

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.6 Frequency (normalized to Fs)

Figure 13. High-Rate Stopband Rejection Figure 14. High-Rate Transition Band

32 DS481PP1

CS43L42

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 Frequency (normalized to Fs)

Amplitude dB

0.30

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

Amplitude dB

-0.10

-0.15

-0.20

-0.25

-0.30

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.5 Frequency (normalized to Fs)

Figure 15. H i gh-Rate Transition Band (Detail) Figure 16. H i gh-Rate Passband Ripple

AGND

DS481PP1 33

AGND

3.3 µF

AOUTx

Figure 17. Line Output Test Load

220 µF

HP_x

Figure 18. Headphone Output Test Load

out

CS43L42

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

LSB

Internal SCLK Mode External SCLK Mode

I2S, Up to 24-Bit data and INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

S, Up to 24-Bit data and INT SCLK = 48 Fs if

I MCLK/LRCK = 384 or 192

Figure 19. CS43L42 Control Port Mode - Serial Audio Format 0

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

LSB

Right Channel

+3 +2 +1

MSB

-1 -2 -3 -4

S, up to 24-Bit Data

+5 +4

Data Valid on Rising Edge of SCLK

Right Channel

+3 +2 +1

MSB

-1 -2 -3 -4

+5 +4

LSB

Internal SCLK Mode External SCLK Mode

I2S, 16-Bit data and INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128

S, Up to 24-Bit data and INT SCLK = 48 Fs if

I MCLK/LRCK = 384 or 192

Figure 20. CS43L42 Control Port Mode - Serial Audio Format 1

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Internal SCLK Mode External SCLK Mode

Left Channel

+5 +4

LSB

Left Justified, up to 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Figure 21. CS43L42 Control Port Mode - Serial Audio Format 2

S, up to 24-Bit Data

I Data Valid on Rising Edge of SCLK

Right Channel

+3 +2 +1

MSB

-1 -2 -3 -4

+5 +4

Left Justified, up to 24-Bit Data Data Valid on Rising Edge of SCLK

LSB

34 DS481PP1

CS43L42

LRCK

SCLK

SDATA

Left Channel

23 22 21 20 19 18

32 clocks

65432107

Internal SCLK Mode External SCLK Mode

Right Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Figure 22. CS43L42 Control Port Mode - Serial Audio Format 3

LRCK

SCLK

SDATA

10 6543210987

17 16 17 16

19 18 19 18

Left Channel

15 14 13 12 11 10

6543210987

Right Channel

23 22 21 20 19 18

65432107

Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period

Right Channel

15 14 13 12 11 10

32 clocks

Internal SCLK Mode External SCLK Mode

Right Justified, 20-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4

LRCK

SCLK

SDATA

Internal SCLK Mode External SCLK Mode

Left Channel

15 14 13 12 11 10

32 clocks

6543210987

Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Right Justified, 20-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 40 Cycles per LRCK Period

Right Channel

15 14 13 12 11 10

6543210987

Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period

Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5

DS481PP1 35

CS43L42

LRCK

SCLK

SDATA

17 16 17 16

Left Channel

15 14 13 12 11 10

32 clocks

6543210987

Internal SCLK Mode External SCLK Mode

Right Justified, 18-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Figure 25. CS43L42 Control Port Mode - Serial Audio Format 6

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

LSB

Right Channel

15 14 13 12 11 10

6543210987

Right Justified, 18-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 36 Cycles per LRCK Period

Right Channel

+3 +2 +1

MSB

-1 -2 -3 -4

+5 +4

LSB

Internal SCLK Mode External SCLK Mode

I2S, Up to 24-Bit data and INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

S, Up to 24-Bit data and INT SCLK = 48 Fs if

I MCLK/LRCK = 384 or 192

Figure 26. CS43L42 Stand Alone Mode - Serial Audio Format 0

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Internal SCLK Mode External SCLK Mode

Left Channel

+5 +4

LSB

Left Justified, up to 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Figure 27. CS43L42 Stand Alone Mode - Serial Audio Format 1

S, up to 24-Bit Data

I Data Valid on Rising Edge of SCLK

Right Channel

+3 +2 +1

MSB

-1 -2 -3 -4

+5 +4

Left Justified, up to 24-Bit Data Data Valid on Rising Edge of SCLK

LSB

36 DS481PP1

CS43L42

LRCK

SCLK

SDATA

Left Channel

23 22 21 20 19 18

32 clocks

65432107

Internal SCLK Mode External SCLK Mode

Right Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Figure 28. CS43L42 Stand Alone Mode - Serial Audio Format 2

LRCK

SCLK

SDATA

Left Channel

15 14 13 12 11 10

6543210987

Right Channel

23 22 21 20 19 18

65432107

Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period

Right Channel

15 14 13 12 11 10

6543210987

32 clocks

Internal SCLK Mode External SCLK Mode

Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Figure 29. CS43L42 Stand Alone Mode - Serial Audio Format 3

Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period

DS481PP1 37

CS43L42

Gain

T1=50 µs

0dB

T2 = 15 µs

-10dB

Left Channel

Audio Data

F1 F2

3.183 kHz 10.61 kHz

Figure 30. De-Emphasis Curve

A Channel

Digital

Volume

Control

Frequency

MUTE

AoutA/HP_A

B Channel

Right Channel

Audio Data

Digital

Volume

Control

MUTE

AoutB/HP_B

Figure 31. ATAPI Block Diagram

38 DS481PP1

8. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

CS43L42

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

9. REFERENCES

1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2) CDB43L42 Evaluation Board Datasheet

3) “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.

http://www.semiconductors.philips.com

DS481PP1 39

10. PACKAGE DIMENSIONS

24L TSSOP (4.4 mm BODY) PACKAGE DRAWING

CS43L42

TOP VIEW

SIDE VIEW

SEATING

PLANE

INCHES MILLIMETERS

END VIEW

NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10

A1 0.002 0.004 0.006 0.05 -- 0.15 A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 D 0.303 0.307 0.311 7.70 7.80 7.90 1 E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

∝

0° 4° 8° 0° 4° 8°

∝

JEDEC #: MO-153

Controlling Dimension is Millimeters.

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

40 DS481PP1

• Notes •

Cirrus Logic CS43L42-KZ, CS43L42 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Description

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

1. CHARACTERISTICS/SPECIFICATIONS

ANALOG CHARACTERISTICS (T

POWER AND THERMAL CHARACTERISTICS (GND = 0 V; All voltages with respect to

DIGITAL CHARACTERISTICS (T

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages wit h resp ect to gro un d.)

SWITCHING CHARACTERISTICS (T

Figure 1. External Serial Mode Input Timing Figure 2. Internal Serial Mode Input Timing

Figure 3. Internal Serial Clock Generation

Figure 4. Control Port Timing - Two-Wire Mode

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

Figure 5. Control Port Timing - SPI Mode

2. TYPICAL CONNECTION DIAGRAM

Figure 6. Typical Connection Diagram

3. REGISTER QUICK REFERENCE

4. REGISTER DESCRIPTION

4.1 Power and Muting Control (address 01h)

4.1.1 AUTO-MUTE (AMUTE)

4.1.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

4.1.3 POPGUARD® TRANSIENT CONTROL (POR)

4.1.4 POWER DOWN HEADPHONE AMPLIFIER (PDNHP)

4.1.5 POWER DOWN LINE AMPLIFIER (PDNLN)

4.1.6 POWER DOWN (PDN)

4.2 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA)

4.3 Channel B Analog Headphone Attenuation Control (address 03h) (hVOLB)

Table 1. Example Analog Volume Settings

4.4 Channel A Digital Volume Control (address 04h) (DVOLA)

4.5 Channel B Digital Volume Control (address 05h) (DVOLB)

Table 2. Example Digita l Volume Settings

4.6 Tone Control (address 06h)

4.6.1 BASS BOOST LEVEL (BB)

Table 3. Example Bass Boost Settings

4.6.2 TREBLE BOOST LEVEL (TB)

Table 4. Example Treble Boost Settings

4.7 Mode Control (address 07h)

4.7.1 BASS BOOST CORNER FREQUENCY (BBCF)

4.7.2 TREBLE BOOST CORNER FREQUENCY (TBCF)

4.7.3 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)

4.7.4 DE-EMPHASIS CONTROL (DEM)

4.7.5 DIGITAL VOLUME CONTROL BYPASS (VCBYP)

4.8 Limiter Attack Rate (address 08h) (ARATE)

Table 5. Example Limiter Attack Rate Settings

4.9 Limiter Release Rate (address 09h) (RRATE)

Table 6. Example Limiter Release Rate Settings

4.10 Volume and Mixing Control (address 0Ah)

4.10.1 TONE CONTROL MODE (TC)

4.10.2 TONE CONTROL ENABLE (TC_EN)

4.10.3 PEAK SIGNAL LIMITER ENABLE (LIM_EN)

4.10.4 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

4.11 Mode Control 2 (address 0Bh)

4.11.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

4.11.2 LINE AMPLIFIER GAIN COMPENSATION (LINE)

4.11.3 DIGITAL INTERFACE FORMAT (DIF)

Table 8. Digital Interface Format

5. PIN DESCRIPTION

Table 9. Stand Alone De-Emphasis Control

Table 10. HRM Common Clock Frequencies

Table 11. BRM Common Clock Frequencies

Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode)

6. APPLICATIONS

6.1 Grounding and Power Supply Decoupling

6.2 Clock Modes

6.3 De-Emphasis

6.4 Recommended Power-up Sequence

6.5 PopGuard® Transient Control

7. CONTROL PORT INTERFACE

7.1 SPI Mode

7.2 Two-Wire Mode

7.3 Memory Address Pointer (MAP)

7.3.1 INCR (AUTO MAP INCREMENT ENABLE)

7.3.2 MAP0-3 (MEMORY ADDRESS POINTER)