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CS43L41-KZ
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Cirrus Logic CS43L41-KZ Datasheet

CS43L41
Low Power 24-Bit, 96 kHz DAC with Volume Control

Features

l Complete Stereo DAC System: Inte rpolation,
D/A, Output Analog Filtering
l ATAPI Mixing l 101 dB Dynamic Range l 89 dBFS THD+N l Low Clock Jitter Sensitivity l +2.4 V to +5 V Power Supply l Filtered Line Level Outputs l On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
l Digital Volume Control with Soft Ramp
– 94 dB Attenuation – 1 dB Step Size – Zero Crossing Click-Free Transitions
l 24 mW with 2.4 V supply
I
SCL/CCLK MUTECAD0/CS
SDA/CDIN

Description

The CS43L41 is a complete stereo digital-to-analog sys­tem including digital interpolation, fourth-order delta­sigma digital-to-ana log c onv ers ion , digi tal de -e mph as is, volume control, channel mixing and analog filtering. The advantages of this archi tec ture i nc lud e: id eal di fferent ial linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera­ture and a high tolerance to clock jitter.
The CS43L41 accepts data at aud io sample rates from 2 kHz to 100 kHz, consumes very little po wer and oper­ates over a wide power supply range. These features are ideal for portable DVD, portable MP3, Mini-Disc, and mobile phones.

ORDERING INFORMATION

CS43L41-KZ 16-pin TSSOP, -10 to 70 °C
Control Port
RST
SCLK
LRCK
SDATA
Serial Port
Advanced Product Information
External
Mute Control
Volume ControlInterpolation Filt er Analog Filter
Mixer
Volume ControlInterpolation Filter
÷2
MCLK
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
∆Σ
∆Σ
DAC
DAC
Analog Filter
DS473PP1
AOUTA
AOUTB
SEP ‘99
1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS .................................. ....... ...... ....... ...... ....... ..... 5
ANALOG CHARACTERISTICS................................................................................................ 5
POWER AND THERMAL CHARACTERISTICS . ....... ............................................. ..................7
DIGITAL CHARACTERISTICS................................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ...........................................................................................7
RECOMMENDED OPERATING CONDITIONS.......................................................................7
SWITCHING CHARACTERISTICS .......................................................................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT.........................................................10
2. TYPICAL CONNECTION DIAGRAM .................................................................................... 11
3. REGISTER QUICK REFERENCE .......................................................................................... 14
3.1 MCLK Control (address 00h)............................................................................................14
3.2 Mode Control (address 01h)............................................................................................. 14
3.3 Volume and Mixing Control (address 02h)........................................................................15
3.4 Channel A Volume Control (address 03h) ........................................................................ 15
3.5 Channel B Volume Control (address 04h) ........................................................................ 15
4. REGISTER BIT DESCRIPTION .............................................................................................. 16
4.1 Master Clock Divide Enable..............................................................................................16
4.2 Auto-Mute .........................................................................................................................16
4.3 Digital Interface Format..................................................................................................... 17
4.4 De-emphasis Control ........................................................................................................ 17
4.5 Power On/Off Quiescent Voltage Ramp ........................................................................... 18
4.6 Power Down...................................................................................................................... 18
4.7 Channel A Volume = Channel B Volume.......................................................................... 19
4.8 Soft Ramp or Zero Cross Enable......................................................................................19
4.9 ATAPI Channel Mixing and Muting...................................................................................20
4.10 Mute................................................................................................................................21
4.11 Volume Control ............................................................................................................... 22
CS43L41
5. PIN DESCRIPTION ................................ ....... ...... .................................................................... 23
Analog Power - VA.................................................................................................................. 23
Analog Ground - AGND ..........................................................................................................23
Analog Output - AOUTA and AOUTB..................................................................................... 23
Reference Ground - REF_GND.............................................................................................. 23
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I2C is a registered trademark of Philips Semiconductors. SPI is a registered trademark of International Business Machines Corporation.
Preliminary product inf o rmation describes products whi c h are i n production, but for whi ch f ul l char act er iza t i on da t a i s not yet available. Advance pr odu ct i nfor ­mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or di sk may be pri nted for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.
2 DS473PP1
Confidential Draft
9/23/99
Positive Voltage Reference - FILT+. ............................................. .......................................... 22
Quiescent Voltage - VQ..........................................................................................................22
Master Clock - MCLK .............................................................................................................23
Left/Right Clock - LRCK .........................................................................................................23
Serial Audio Data - SDATA .................................................................................................... 23
Serial Clock - SCLK................................................................................................................ 24
Reset - RST............................................................................................................................ 24
Serial Control Interface Clock - SCL/CCLK........................................................................... 24
Serial Control Data I/O - SDA/CDIN....................................................................................... 24
Address Bit / Chip Select - AD0/CS
Mute Control - MUTEC........................................................................................................... 24
6. APPLICATIONS ..................................................................................................................... 25
6.1 Grounding and Power Supply Decoupling ....................................................................... 25
6.2 Oversampling Modes ....................................................................................................... 25
6.3 Recommended Power-up Sequence ............................................................................... 25
6.4 Use of the Power ON/OFF Quiescent Voltage Ramp ..................................................... 25
7. CONTROL PORT INTERFACE ............................................. ................................................. 26
7.1 SPI Mode ......................................................................................................................... 26
2
C Compatible Mode ...................................................................................................... 26
7.2 I
7.3 Memory Address Pointer (MAP)....................................................................................... 27
........................................................................................ 24
CS43L41
8. PARAMETER DEFINITIONS .................................................................................................. 33
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33
Dynamic Range...................................................................................................................... 33
Interchannel Isolation ............................................................................................................. 33
Interchannel Gain Mismatch................................................................................................... 33
Gain Error............................................................................................................................... 33
Gain Drift ................................................................................................................................ 33
9. REFERENCES .......................... ....... ...... ....... ...... ....... ...... ...... ......................................... ..... ... 3 3
10. PACKAGE DIMENSIONS .................................................................................................... 34
DS473PP1 3

LIST OF FIGURES

Figure 1. External Serial Mode Input Timing .................................................................................9
Figure 2. Internal Serial Mode Input Timing .................................................................................. 9
Figure 3. Internal Serial Clock Generation .................................................................................... 9
Figure 4. I
Figure 5. SPI Control Port Timing ...............................................................................................12
Figure 6. Typical Connection Diagram ........................................................................................13
Figure 7. SPI Mode Control Port Formatting ............................................................................... 28
Figure 8. I
Figure 9. Base-Rate Stopband Rejection ....................................................................................29
Figure 10. Base-Rate Transition Band ..........................................................................................29
Figure 11. Base-Rate Transition Band (Detail) .............................................................................29
Figure 12. Base-Rate Passband Ripple ........................................................................................29
Figure 13. High-Rate Stopband Rejection ..................................................................................... 29
Figure 14. High-Rate Transition Band ...........................................................................................29
Figure 15. High-Rate Transition Band (Detail) .............................................................................. 30
Figure 16. High-Rate Passband Ripple .........................................................................................30
Figure 17. Output Test Load .........................................................................................................30
Figure 18. Maximum Loading ........................................................................................................30
Figure 19. Power vs. Sample Rate (VA = 5V) ...............................................................................30
Figure 20. CS43L41 Format 0 (I Figure 21. CS43L41 Format 1 (I
Figure 22. CS43L41 Format 2 .......................................................................................................31
Figure 23. CS43L41 Format 3 .......................................................................................................32
Figure 24. CS43L41 Format 4 .......................................................................................................32
Figure 25. CS43L41 Format 5 .......................................................................................................32
Figure 26. CS43L41 Format 6 .......................................................................................................33
Figure 27. De-Emphasis Curve .....................................................................................................33
Figure 28. ATAPI Block Diagram ..................................................................................................33
2
C Control Port Timing ................................................................................................ 10
2
C Mode Control Port Formatting ................................................................................28
2
S) .............................................................................................. 31
2
S) .............................................................................................. 31
CS43L41

LIST OF TABLES

Table 1. Master Clock Divide Enable ...............................................................................................16
Table 2. Auto-Mute Enable...............................................................................................................16
Table 3. Digital Interface Formats .................................................................................................... 17
Table 4. De-emphasis Filter Configurations .....................................................................................17
Table 5. Power On/Off Ramp Enable...............................................................................................18
Table 6. Power Down Enable ........................................................................................................... 18
Table 7. A=B Volume Control Enable............................................................................................... 19
Table 8. Soft Ramp and Zero Cross Enable.....................................................................................20
Table 9. ATAPI Decode....................................................................................................................20
Table 10. Mute Enable .....................................................................................................................21
Table 11. Digital Volume Settings ....................................................................................................22
Table 12. Common Clock Frequencies ............................................................................................24
4 DS473PP1

1. CHARACTERISTICS AND SPECIFICATIONS

CS43L41

ANALOG CHARACTERISTICS (T

Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load R
C
= 10 pF (see Figure 17)),
L
Parameter
= 25 °C; Logic "1" = VA; Logic "0" = AGND;
A
= 10 k
L
Base-rate Mode High-Rate Mode
Symbol Min Typ Max Min Typ Max Unit
Ω,
Dynamic Performance for VA = 5 V
Specified Temperature Range T Dynamic Range (Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit unweighted
A-Weighted
Total Harmonic Distortion + Noise (Note 1)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
A
THD+N
-10 - 70 -10 - 70 °C
92 96
-
-
-
-
-
-
-
-
97
101
95 99
-89
-77
-37
-88
-75
-35
-
-
-
-
-84
-72
-32
-
-
-
91 95
96
100
-
-
-
-
-
-
-
-
94 98
-89
-74
-36
-89
-73
-34
-
-
-
-
-84
-69
-31
-
-
-
dB dB dB dB
dB dB dB dB dB dB
Dynamic Performance for VA = 2.4 V
Specified Temperature Range T Dynamic Range (Note 1)
18 to 24-Bit
unweighted
A-Weighted
16-Bit unweighted
A-Weighted
Total Harmonic Distortion + Noise (Note 1)
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
Interchannel Isolation (1 kHz) - 100 - - 100 - dB
A
THD+N
-10 - 70 -10 - 70 °C
TBD TBD
-
-
-
-
-
-
-
-
92 95 91 94
-91
-72
-32
-90
-71
-31
-
-
-
-
TBD TBD TBD
-
-
-
TBD TBD
-
-
-
-
-
-
-
-
91 95 90 94
-89
-71
-31
-88
-70
-30
-
-
-
-
TBD TBD TBD
-
-
-
dB dB dB dB
dB dB dB dB dB dB
Notes: 1. One-half LSB of triangular PDF dither is added to data.
DS473PP1 5
CS43L41
ANALOG CHARACTERISTICS (Continued)
Parameters Symbol Min Typ Max Units
Analog Output
Full Scale Output Voltage 0.63•VA 0.7•VA 0.77•VA Vpp Quiescent Voltage V Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C AC-Load Resistance (Note 2) R Load Capacitance (Note 2) C
Parameter
Symbol Min Typ Max Min Ty p Max Unit
Q
L L
Base-rate Mode High-Rate Mode
Combined Digital and On-chip Analog Filter Response (Note 3)
Passband (Note 4)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner Frequency Response 10 Hz to 20 kHz -.02 - +.08 -0.06 - 0 dB StopBand .5465 - - .577 - - Fs StopBand Attenuation (Note 5) 50 - - 55 - - dB Group Delay tgd - 9/Fs - - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz
0 - 20 kHz
De-emphasis Error Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
0
-
0
-
--±0.36/Fs
-
-
-
-
-
-
-
-
-
-0.5•VA- VDC
3--k
--100pF
.4535
-
.4998
-
-
+.2/-.1
+.05/-.14
+0/-.22
­0 0
--±1.39/Fs
-
-
-
±0.23/Fs--
(Note 6)
.4621 .4982
Ω
-
dB dB dB
Fs Fs Fs
s s
Notes: 2. Refer to Figure 18.
3. Filter response is guarant e ed by de sig n.
4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9-16) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
6. De- em pha si s is not availab le in High - Rate Mod e.
6 DS473PP1

POWER AND THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units
Power Supplies
Power Supply Current normal operation VA = 5 V power-down state
Power Dissipation (Note 7) VA = 5 V normal operation
power-down
Power Supply Current normal operation VA = 2.4V power-down state
Power Dissipation (Note 7) VA = 2.4 V normal operation
power-down Package Thermal Resistance Power Supply Rejection Ratio (1 kHz) (Note 8)
(60 Hz)
Notes: 7. Refer to Figure 19.
8. Valid with the recommended capacitor values on FILT+ and V
I
A
I
A
I
A
I
A
θ
JA
PSRR -
CS43L41
-
-
-
-
-
-
-
-
-110-°C/Watt
-
as shown in Figure 1.
Q
15 60
75
0.3 10
30
24
0.07
60 40
17
-
85
-
TBD
-
TBD
-
-
-
mA
µ
A
mW mW
mA
µ
A
mW mW
dB dB

DIGITAL CHARACTERISTICS (T

= 25°C; VA = 2.28V - 5.5V)
A
Parameters Symbol Min Typ Max Units
High-Level Input Voltage VA = 5 V
VA = 2.4 V
Low-Level Input Voltage VA = 5 V
VA = 2.4 V
Input Leakage Current I
V
IH
2.0
2.0
V
IL
-
-
in
--±10
-
-
-
-
-
-
0.8
0.8
V V
V V
µ
A Input Capacitance - 8 - pF Maximum MUTEC Drive Current - 3 - mA

ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Max Units
DC Power Supply VA -0.3 6.0 V Input Current, Any Pin Except Supplies I Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T
in
IND
A
stg
-±10mA
-0.3 VA+0.4 V
-55 125 °C
-65 150 °C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units
DC Power Supply VA 2.28 5.0 5.5 V
DS473PP1 7
CS43L41
1
1

SWITCHING CHARACTERISTICS (T

Logic 1 = VA, C
= 20pF)
L
= -10 to 70°C; VA = 2.4V - 5.5V; Inputs: Logic 0 = 0V,
A
Parameters Symbol Min Typ Max Units
Input Sample Rate Fs 2 - 100 kHz MCLK Pulse Width High MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width Low MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - 1000 ns
External SCLK Mode
LRCK Duty Cycle (External SCLK only) 40 50 60 % SCLK Pulse Width Low t SCLK Pulse Width High t SCLK Period MCLK / LRCK = 512, 256 or 384 t
SCLK Period MCLK / LRCK = 128 or 192 t
SCLK rising to LRCK edge delay t SCLK rising to LRCK edge setup time t SDATA valid to SCLK rising setup time t SCLK rising to SDATA hold time t
sclkl
sclkh
sclkw
sclkw
slrd
slrs
sdlrs
sdh
20 - - ns 20 - - ns
1
---------------------­128()Fs
1
-----------------­64()Fs
--ns
--ns
20 - - ns 20 - - ns 20 - - ns 20 - - ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only) (Note 9) - 50 - % SCLK Period (Note 10) t
SCLK rising to LRCK edge t
sclkw
sclkr
---------------­SCLK
--
--ns
tsclkw
----------------- ­2
µ
s
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192
sdlrs
t
sdh
t
sdh
1
----------------------10+ 512()Fs
----------------------15+ 512()Fs
1
----------------------15+ 384()Fs
--ns
--ns
--ns
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% ±1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK ratio. (See Figures 20-26)
8 DS473PP1
LRCK
SCLK
t
slrd
t
slrs
t
sclkl
t
sclkh
CS43L41
SDATA
LRCK
SDATA
*INTERNAL SCLK
*The SCLK pulses shown are internal to the CS43L41.
t
sdlrs
t
sdh
Figure 1. External Serial Mode Input Timing
t
sclkr
t
sclkw
t
sdlrstsdh
Figure 2. Internal Serial Mode Input Timing
LRCK
MCLK
*INTERNAL SCLK
SDATA
1
N 2
N
Figure 3. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS43L41.
N equals MCLK divided by SCLK
DS473PP1 9

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, CL = 30 pF)
Parameter Symbol Min Max Unit
I2C® Compatible Mode
SCL Clock Frequency f
Rising Edge to Start t
RST Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling (Note 11) t SDA Setup time to SCL Rising t Rise Time of Both SDA and SCL Lines t Fall Time of Both SDA and SCL Lines t Setup Time for Stop Condition t
scl
irs
buf
hdst
low high sust
hdd
sud
r f
susp
CS43L41
-100kHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs 0-µs
250 - ns
-1µs
-300ns
4.7 - µs
Notes: 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t
SDA
SCL
irs
Stop Start
t
buf
t
t
hdst
low
t
hdd
t
high
t
sud
Repeated
Start
t
sust
t
hdst
t
f
t
r
Figure 4. I2C Control Port Timing
Stop
t
susp
10 DS473PP1
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, CL = 30 pF)
Parameter Symbol Min Max Unit
SPI® Mode
CCLK Clock Frequency f
Rising Edge to CS Falling t
RST CCLK Edge to CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CS
Falling (Note 12) t
CCLK Low Time t CCLK High Time t CDIN to CCLK Rising Setup Time t CCLK Rising to DATA Hold Time (Note 13) t Rise Time of CCLK and CDIN (Note 14) t Fall Time of CCLK and CDIN (Note 14) t
sclk
srs
spi csh css
scl
sch dsu
dh
r2 f2
CS43L41
-6MHz 500 - ns 500 - ns
1.0 - µs
20 - ns 66 - ns 66 - ns 40 - ns 15 - ns
-100ns
-100ns
Notes: 12. t
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F
only needed before first falling edge of CS after RST rising edge. t
spi
< 1 MHz
SCK
RST
CS
CCLK
CDIN
t
srs
t
t
css
spi
tr2t
t
t
sch
scl
f2
= 0 at all other times.
spi
t
csh
t
t
dsu
dh
Figure 5. SPI Control Port Timing
DS473PP1 11
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