l 24 Bit Conversion
l Up to 192 kHz Sample Rates
l 120 dB Dynamic Range
l -100 dB THD+N
l Advanced Dynamic-Element Matching
l Low Clock Jitter Sensitivity
l Digital De-emphasis for 32 kHz, 44.1 kHz and
48 kHz
l External Reference Input
I
SCLK
LRCK
SDATA
SERIAL INTERFACE
AND FORMAT SELECT
Description
The CS4396 is a complete high performance 24-bit
48/96/192 kHz ste reo digital-to-analog conversio n system. The device includes a digital interpolation filter
followed by a oversampled multi-bit delta-sigma modulator which drives dynamic-element-matching (DEM)
selection logic. The out put from the DEM blo ck controls
the input to a multi-element switched capacitor DAC/lowpass filter, with fully-differential outputs. This multi-bit architecture feat ures signific antly lowe r out-of-ba nd noise
and jitter sensitivity than traditional 1-bit designs, and the
advanced DEM g uarantees low noise a nd distortion at
all signal levels.
ORDERING INFORMATION
CS4396-KS-10° to 70° C 28-pin Plastic SOIC
CDB4397Evaluation Board
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
“The I2C-Bus Specification: Vers ion 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
Preliminary product info rmation describes products which are in production, but for which full characteriza t i on da t a is not yet available. Advance produ ct i nfor mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” withou t warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document i s the propert y of Cirru s Logic, Inc. and implie s no licen se under patent s, copyri ghts, trademarks, or tr ade secrets. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pri or wri tt en consen t of Ci rrus Logic, Inc. Items from any Cirrus Logi c websi te or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2DS288PP1
TABLE OF FIGURES
CS4396
Figure 1. Serial Audio Input Timing ........................................................................... 8
Figure 2. I
Figure 3. SPI Control Port Timing ........................................................................... 10
2. Performance limited by 16-bit qu an ti za ti on noi se.
4DS288PP1
ANALOG CHARACTERISTICS (Continued)
CS4396
ParameterSymbolVD = 3 VVD = 5 V
Power Supplies
Supply Currentnormal operation
VA = 5 Vnormal operation
power-down state
Power Dissipation normal operation
VA = 5 Vpower-down
Power Supply Rejection Ratio (1 kHz)(Note 3)
(120 Hz)
ParameterSymbolMin
MinTypMax MinTypMax
I
A
I
D
ID + I
A
PSRR-
-
20
-
TBD
-
60
--TBD
0.3
60
-
40
TBD
TBD
TBD---TBD
-
20
-
TBD
-
-
30
0.3
-
-
60
-
-
40
TypMax
TBD
TBD
TBD-mW
Unit
mA
mA
-
-
-
µ
mW
dB
dB
Unit
A
Analog Output
Full Scale Differential Output VoltageTBD1.4VREFTBDVpp
Common Mode Voltage-0.5VREF-VDC
Interchannel Gain Mismatch-0.1-dB
Gain Drift-100-ppm/°C
Differential DC Offset-2.0TBDmV
AC-Load ResistanceR
Load CapacitanceC
Interchannel Isolation(1 kHz)-90-dB
L
L
1--k
--100pF
Ω
Notes: 3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing
the capacitance will also increase the PSRR.
DS288PP15
CS4396
ANALOG CHARACTERISTICS (Continued)
ParameterSymbolMinTypMaxUnit
Combined Digital and On-chip Analog Filter Response - Single Speed Mode
Passband(Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-.020-+0.015dB
Passband Ripple--±0.0001dB
StopBand.5465--Fs
StopBand Attenuation(Note 5)102--dB
Group Delay(Note 6)tgd-37/Fs-s
De-emphasis Error(Note 7)
Fs = 32 kHz
(Relative to 1 kHz)Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response - Double Speed Mode
Passband(Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz-0.017-0.035dB
Passband Ripple--±0.0008dB
StopBand.570--Fs
StopBand Attenuation(Note 5)82--dB
Group Delaytgd-20/Fs-s
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode
Passband(Note 4)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz0-+0.015dB
Passband Ripple--±0.00065dB
StopBand0.635--Fs
StopBand Attenuation(Note 5)83--dB
Group Delaytgd-11/Fs-s
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
-
0.470
0.492
±0.10
±0.10
±0.13
0.448
0.486
0.385
0.472
dB
dB
dB
Fs
Fs
Fs
Fs
Fs
Fs
Notes: 4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 7-18) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 1.4 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.570 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.635 Fs to 1.3 Fs.
6. Group Delay for Fs=48 kHz 37/48 kHz=770µs
7. De-emphasis is avai lab le only in Si ngl e Spee d Mode.
6DS288PP1
CS4396
DIGITAL CHARACTERISTICS (T
= 25°C; VD = 3.0V - 5.25V)
A
ParametersSymbol Min TypMaxUnits
High-Level Input VoltageVD = 5 V
VD = 3 V
Low-Level Input VoltageVD = 5 V
VD = 3 V
Input Leakage CurrentI
V
IH
V
IL
in
2.0
2.0
-
-
-
-
-
-
-
-
0.8
0.8
--±10µA
V
V
V
V
Input Capacitance-8-pF
Maximum MUTEC Drive Current-3-mA
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)
ParameterSymbol Min MaxUnit
DC Power Supply: Positive Analog
Positive Digital
Reference Voltage
Input Current, Any Pin Except SuppliesI
Digital Input VoltageV
Ambient Operating Temperature (power applied)T
Storage TemperatureT
WARNING: Oper ati on at or be yond these limits may r es ul t in perm anent damage to the dev ice. No rm al operation
is not guaranteed at these extremes.
VA
VD
VREF
in
IND
A
stg
-0.3
-0.3
-0.3
6.0
6.0
VA
V
V
V
-±10mA
-0.3(VD)+0.4V
-55125°C
-65150°C
RECOMMENDED OPERATING CONDITIONS
ParameterSymbol Min TypMaxUnit
DC Power Supply: Positive Digital
Positive Analog
Reference Voltage
Specified Temperature RangeT
VD
VA
VREF
(DGND = 0V; all voltages with respect to ground)
3.0
4.75
TBD
A
-10-70°C
3.3
5.0
5.0
5.25
5.25
VA
V
V
V
DS288PP17
CS4396
SWITCHING CHARACTERISTICS (T
1 = VD = 5.25 to 3.0 Volts; C
=20pF)
L
= -10 to 70°C; Logic 0 = AGND = DGND; Logic
A
ParameterSymbol Min TypMaxUnit
Input Sample Rate (Single-speed mode)
(Double-speed mode)
(Quad-speed mode)
Fs
Fs
Fs
16
50
100
-
-
-
50
100
200
kHz
kHz
kHz
LRCK Duty Cycle455055%
MCLK Frequency (Single-speed 256 Fs,
Double speed 128 Fs or Quad-speed 64 Fs)
MCLK Frequency (Single-speed 384 Fs,
Double speed 192 Fs or Quad-speed, 96 Fs
MCLK Frequency (Single-speed 512 Fs,
Double speed 256 Fs or Quad-speed, 128 Fs
MCLK Frequency (Single-speed 768 Fs,
Double speed 384 Fs or Quad-speed, 192 Fs
4.096
6.144
8.192
12.288
-12.8MHz
-19.2MHz
-25.6MHz
-38.4MHz
MCLK Duty Cycle405060%
SCLK Frequency (Single-speed mode)
(Double-speed mode)
(Quad-speed mode)
SCLK rising to LRCK edge delayt
SCLK rising to LRCK edge setup timet
SDATA valid to SCLK rising setup timet
SCLK rising to SDATA hold timet
Start Condition Hold Time (prior to first clock pulse)t
Clock Low timet
Clock High Timet
Setup Time for Repeated Start Conditiont
SDA Hold Time from SCL Falling(Note 8)t
SDA Setup time to SCL Risingt
Rise Time of Both SDA and SCL Linest
Fall Time of Both SDA and SCL Linest
Setup Time for Stop Conditiont
scl
irs
buf
hdst
low
high
sust
hdd
sud
r
f
susp
-100KHz
500-ns
4.7-µs
4.0-µs
4.7-µs
4.0-µs
4.7-µs
0-µs
250-ns
-1µs
-300ns
4.7-µs
CS4396
Notes: 8. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t
SDA
SCL
irs
StopStart
t
buf
t
hdst
t
low
t
hdd
t
high
t
sud
Repeated
Start
t
t
sust
hdst
t
f
t
r
Figure 2. I2C Control Port Timing
Stop
t
susp
DS288PP19
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