CIRRUS LOGIC CS4396 Service Manual

CS4396

24-Bit, 192 kHz D/A Converter for Digital Audio

Features

l 24 Bit Conversion l Up to 192 kHz Sample Rates l 120 dB Dynamic Range l -100 dB THD+N l Advanced Dynamic-Element Matching l Low Clock Jitter Sensitivity l Digital De-emphasis for 32 kHz, 44.1 kHz and

48 kHz

l External Reference Input

SCLK LRCK

SDATA

SERIAL INTERFACE

AND FORMAT SELECT

Description

The CS4396 is a complete high performance 24-bit 48/96/192 kHz ste reo digital-to-analog conversio n system. The device includes a digital interpolation filter followed by a oversampled multi-bit delta-sigma modulator which drives dynamic-element-matching (DEM) selection logic. The out put from the DEM blo ck controls the input to a multi-element switched capacitor DAC/lowpass filter, with fully-differential outputs. This multi-bit architecture feat ures signific antly lowe r out-of-ba nd noise and jitter sensitivity than traditional 1-bit designs, and the advanced DEM g uarantees low noise a nd distortion at all signal levels.

ORDERING INFORMATION

CS4396-KS -10° to 70° C 28-pin Plastic SOIC CDB4397 Evaluation Board

SOFT MUTE

DE-EMPHASIS

FILTER

INTERPOLATION

MCLK

CLOCK

DIVIDER

(AD0/CS)

INTERPOLATION

HARDWARE MODE CONTROL

M3 M2

(AD1/CDIN) (SCL/CCLK)

Advance Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

FILTER

(CONTROL PORT)

M1 M0

(SDA/CDOUT)

MULTI-BIT

∆Σ

MODULATOR

MULTI-BIT

∆Σ

MODULATOR

RESET MUTEC MUTE

DYNAMIC ELEMENT

MATCHING

LOGIC

DYNAMIC ELEMENT

MATCHING

LOGIC

FILT+

SWITCHED

CAPACITOR-DAC

AND FILTER

SWITCHED

CAPACITOR-DAC

AND FILTER

VOLTAGE REFERENCE

VREF CMOUTFILT-

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

AOUTL+ AOUTL-

AOUTR+ AOUTR-

JUL ‘99

DS288PP1

1.0 CHARACTERISTICS/SPECIFICATIONS ..................................................................... 4

ANALOG CHARACTERISTICS................................................................................... 4

Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz ...................... 4

Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz .................... 4

Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz ..................... 4

ANALOG CHARACTERISTICS................................................................................... 5

Power Supplies .................................................................................................... 5

Analog Output ...................................................................................................... 5

Combined Digital and On-chip Analog Filter Response - Single Speed Mode .... 6

Combined Digital and On-chip Analog Fi lte r Respon se - Double Spe ed Mod e ... 6

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode ..... 6

DIGITAL CHARACTERISTICS.................................................................................... 7

ABSOLUTE MAXIMUM RATINGS.............................................................................. 7

RECOMMENDED OPERATING CONDITIONS.......................................................... 7

SWITCHING CHARACTERISTICS ........................................................ ...... ....... ...... .. 8

SWITCHING CHARACTERISTICS - CONTROL PORT ............................................. 9

2C®

SPI Mode ........................................................................................................... 10

2.0 TYPICAL CONNECTION DIAGRAM .......................................................................... 11

3.0 REGISTER DESCRIPTION ........................................................................................ 12

3.1 Differential DC offset calibration ........................................................................ 12

3.2 Soft Mute ........................................................................................................... 12

3.3 Mode Select ....................................................................................................... 13

3.4 Power DowN ...................................................................................................... 13

4.0 PIN DESCRIPTION ..................................................................................................... 14

5.0 APPLICATIONS .......................................................................................................... 19

5.1 Recommended Power-up Sequence ................................................................. 19

6.0 CONTROL PORT INTERFACE .................................................................................. 20

6.1 SPI Mode ........................................................................................................... 20

6.2 I

C Mode ........................................................................................................... 20

6.2 Memory Address Pointer (MAP) ........................................................................ 20

7.0 PARAMETER DEFINITIONS ...................................................................................... 26

8.0 REFERENCES ............................................................................................................ 26

9.0 PACKAGE DIMENSIONS ........................................................................................... 27

CS4396

Mode ............................................................................................................ 9

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

“The I2C-Bus Specification: Vers ion 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com

Preliminary product info rmation describes products which are in production, but for which full characteriza t i on da t a is not yet available. Advance produ ct i nfor mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” withou t warranty of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document i s the propert y of Cirru s Logic, Inc. and implie s no licen se under patent s, copyri ghts, trademarks, or tr ade secrets. No part of this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the pri or wri tt en consen t of Ci rrus Logic, Inc. Items from any Cirrus Logi c websi te or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2 DS288PP1

TABLE OF FIGURES

CS4396

Figure 1. Serial Audio Input Timing ........................................................................... 8

Figure 2. I

Figure 3. SPI Control Port Timing ........................................................................... 10

Figure 4. Typical Connection Diagram - Hardware Mode (Control Port Mode) ....... 11

Figure 5. Control Port Timing, I

Figure 6. Control Port Timing, SPI mode ................................................................ 21

Figure 7. Single-speed Transition Band .................................................................. 23

Figure 8. Single-speed Stopband Rejection ............................................................ 23

Figure 9. Single-speed Transition Band .................................................................. 23

Figure 10.Single-speed Frequency Response ......................................................... 23

Figure 11.Double-speed Stopband .......................................................................... 23

Figure 12.Double-speed Transition Band ................................................................. 23

Figure 13.Double-speed Transition Band ................................................................. 23

Figure 14.Double-speed Frequency Response ........................................................ 23

Figure 15.Quad-speed Stopband Rejection ............................................................. 24

Figure 16.Quad-speed Transition Band ................................................................... 24

Figure 17.Quad-speed Transition Band ................................................................... 24

Figure 18.Quad-speed Frequency Response .......................................................... 24

Figure 19.De-Emphasis Curve ................................................................................. 24

Figure 20. Format 0, Left Justified ............................................................................ 25

Figure 21. Format 1, I

Figure 22. Format 2, Right Justified, 16-Bit Data ..................................................... 25

Figure 23.Format 3, Right Justified, 24-Bit Data ...................................................... 25

C Control Port Timing .............................................................................. 9

C Mode ................................................................. 21

S ............................. ...................................... ....................... 25

DS288PP1 3

1.0 CHARACTERISTICS/SPECIFICATIONS

CS4396

ANALOG CHARACTERISTICS (T

Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R

Parameter Symbol Min T y p Max Unit

= 25 °C; Logic "1" = VD = 5 V; VA = 5V; Logic "0" = DGND;

= 1 kΩ, CL = 10 pF)

Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz

Dynamic Range (Note 1)

24-Bit unweighted

A-Weighted 16-Bit unweighted (Note 2) A-Weighted

Total Harmonic Distortion + Noise (Note 1)

24-Bit 0 dB

-20 dB

-60 dB 16-Bit 0 dB (Note 2) -20 dB

-60 dB

THD+N

TBD TBD

117 120

95 98

-100

-97

-57

-95

-75

-35

TBD TBD TBD

dB dB dB dB

dB dB dB dB dB dB

Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz

Dynamic Range (Note 1)

24-Bit unweighted

A-Weighted 40 kHz bandwidth unweighted 16-Bit unweighted (Note 2) A-Weighted

Total Harmonic Distortion + Noise (Note 1)

24-Bit 0 dB

-20 dB

-60 dB 16-Bit 0 dB (Note 2) -20 dB

-60 dB

THD+N

TBD TBD TBD

117 120 114

92 98

-100

-97

-57

-95

-75

-35

TBD TBD TBD

dB dB dB dB dB

dB dB dB dB dB dB

Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz

Dynamic Range (Note 1)

24-Bit unweighted

A-Weighted 40 kHz bandwidth unweighted 16-Bit unweighted (Note 2) A-Weighted

Total Harmonic Distortion + Noise (Note 1)

24-Bit 0 dB

-20 dB

-60 dB 16-Bit 0 dB (Note 2) -20 dB

-60 dB

THD+N

TBD TBD TBD

117 120 114

92 98

-100

-97

-57

-95

-75

-35

TBD TBD TBD

dB dB dB dB dB

dB dB dB dB dB dB

Notes: 1. Triangular PDF dithered data.

2. Performance limited by 16-bit qu an ti za ti on noi se.

4 DS288PP1

ANALOG CHARACTERISTICS (Continued)

CS4396

Parameter Symbol VD = 3 V VD = 5 V

Power Supplies

Supply Current normal operation VA = 5 V normal operation

power-down state

Power Dissipation normal operation VA = 5 V power-down

Power Supply Rejection Ratio (1 kHz) (Note 3)

(120 Hz)

Parameter Symbol Min

Min Typ Max Min Typ Max

ID + I

PSRR -

TBD

--TBD

0.3 60

TBD TBD

TBD---TBD

TBD

0.3

Typ Max

TBD TBD

TBD-mW

Unit

mA mA

dB dB

Unit

Analog Output

Full Scale Differential Output Voltage TBD 1.4VREF TBD Vpp Common Mode Voltage - 0.5VREF - VDC

Notes: 3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing

the capacitance will also increase the PSRR.

DS288PP1 5

CS4396

6 DS288PP1

CS4396

DIGITAL CHARACTERISTICS (T

= 25°C; VD = 3.0V - 5.25V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage VD = 5 V

VD = 3 V

Low-Level Input Voltage VD = 5 V

VD = 3 V

Input Leakage Current I

2.0

0.8

--±10µA

V V

Input Capacitance - 8 - pF Maximum MUTEC Drive Current - 3 - mA

ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)

Parameter Symbol Min Max Unit

DC Power Supply: Positive Analog

Positive Digital

Reference Voltage Input Current, Any Pin Except Supplies I Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T

WARNING: Oper ati on at or be yond these limits may r es ul t in perm anent damage to the dev ice. No rm al operation is not guaranteed at these extremes.

VREF

IND

stg

-0.3

6.0

6.0 VA

V V V

-±10mA

-0.3 (VD)+0.4 V

-55 125 °C

-65 150 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

DC Power Supply: Positive Digital

Positive Analog Reference Voltage

Specified Temperature Range T

VREF

(DGND = 0V; all voltages with respect to ground)

3.0

4.75 TBD

-10 - 70 °C

3.3

5.0

5.25

5.25 VA

V V V

DS288PP1 7

CS4396

SWITCHING CHARACTERISTICS (T

1 = VD = 5.25 to 3.0 Volts; C

=20pF)

= -10 to 70°C; Logic 0 = AGND = DGND; Logic

Parameter Symbol Min Typ Max Unit

Input Sample Rate (Single-speed mode)

(Double-speed mode)

(Quad-speed mode)

Fs Fs Fs

16 50

100

50 100 200

kHz kHz

kHz LRCK Duty Cycle 45 50 55 % MCLK Frequency (Single-speed 256 Fs,

Double speed 128 Fs or Quad-speed 64 Fs)

MCLK Frequency (Single-speed 384 Fs,

Double speed 192 Fs or Quad-speed, 96 Fs

MCLK Frequency (Single-speed 512 Fs,

Double speed 256 Fs or Quad-speed, 128 Fs

MCLK Frequency (Single-speed 768 Fs,

Double speed 384 Fs or Quad-speed, 192 Fs

4.096

6.144

8.192

12.288

-12.8MHz

-19.2MHz

-25.6MHz

-38.4MHz

MCLK Duty Cycle 40 50 60 % SCLK Frequency (Single-speed mode)

(Double-speed mode)

(Quad-speed mode) SCLK rising to LRCK edge delay t SCLK rising to LRCK edge setup time t SDATA valid to SCLK rising setup time t SCLK rising to SDATA hold time t

slrd slrs

sdlrs

sdh

256×Fs 128×Fs

64×Fs 20 - - ns 20 - - ns 20 - - ns 20 - - ns

Hz Hz Hz

LRCK

sclkl

sdh

sclkh

SCLK

SDATA

slrd

sdlrs

slrs

Figure 1. Serial Audio Input Timing

8 DS288PP1

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF)

Parameter Symbol Min Max Unit

I2C® Mode

SCL Clock Frequency f RST

Rising Edge to Start t

Bus Free Time Between Transmissions t

Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling (Note 8) t SDA Setup time to SCL Rising t Rise Time of Both SDA and SCL Lines t Fall Time of Both SDA and SCL Lines t Setup Time for Stop Condition t

scl

irs

buf

hdst

low high sust

hdd

sud

r f

susp

-100KHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs 0-µs

250 - ns

-1µs

-300ns

4.7 - µs

CS4396

Notes: 8. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

RST

SDA

SCL

irs

Stop Start

buf

hdst

low

hdd

high

sud

Repeated

Start

sust

hdst

Figure 2. I2C Control Port Timing

Stop

susp

DS288PP1 9

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF)

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency f RST

Rising Edge to CS Falling t

CCLK Edge to CS

High Time Between Transmissions t

CS CS

Falling to CCLK Edge t CCLK Low Time t CCLK High Time t CDIN to CCLK Rising Setup Time t CCLK Rising to DATA Hold Time (Note 10) t Rise Time of CCLK and CDIN (Note 11) t Fall Time of CCLK and CDIN (Note 11) t CCLK Falling to CDOUT valid t

Falling (Note 9) t

sclk

srs spi

csh

css

scl sch dsu

r2 f2

-6MHz 500 - ns 500 - ns

1.0 - µs 20 - ns 66 - ns 66 - ns 40 - ns 15 - ns

-100ns

45 ns

CS4396

Notes: 9. t

10. Data must be held for sufficient time to bridge the transition time of CCLK.

11. For F

only needed before first falling edge of CS after RST rising edge. t

spi

< 1 MHz

SCK

RST

srs

spi

css

scl

sch

CCLK

CDIN

dsu

= 0 at all other times.

spi

csh

Figure 3. SPI Control Port Timing

10 DS288PP1

2.0 TYPICAL CONNECTION DIAGRAM

1 µF

0.1 µF

0.1 µf

1.0 µF

CS4396

+5V

Analog

Mode

Select

Audio

Data

Processor

External Clock

4 3

M0 M1

M2 M3

LRCK

SCLK

SDATA

MUTE

RST

MCLK

C/H

CS4396

DGND

AOUTL-

AOUTL+

MUTEC

AOUTR-

AOUTR+

CMOUT

AGND

VREF

FILT+

FILT-

0.1 µf 10 µf

Analog

Conditioning

Analog

Conditioning

0.1 µf 10 µf

+5V

Analog

Figure 4. Typical Connection Diagram - Hardware Mode (Control Port Mode)

DS288PP1 11

CS4396

3.0 REGISTER DESCRIPTION

3.1 DIFFERENTIAL DC OFFSET CALIBRATION

Mode Control Register (address 01h)

76543210

CAL MUTE M4 M3 M2 M1 M0 PDN

Access:

R/W in I2C and SPI.

Default:

0 - Disabled

Function:

Enabling this function will initiate a calibration to minimize the differential DC offset. This function will be automatically reset following completion of the calibration sequence.

CAL MODE

0 Disabled : CAL complete 1 Enabled : CAL initiated

Table 1.

3.2 SOFT MUTE

Mode Control Register (address 01h)

76543210

CAL

MUTE

M4 M3 M2 M1 M0 PDN

Access:

R/W in I2C and SPI.

Default:

0 - Enabled

Function:

The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias voltage on the outputs will be retained and MUTEC

The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The MUTEC

MUTE

0 Enabled 1 Disabled

MODE

Table 2.

will go low at the completion of the ramp period.

will go high immediately on disabling of MUTE.

12 DS288PP1

CS4396

3.3 MODE SELECT

Mode Control Register (address 01h)

76543210

CAL MUTE

Access:

R/W in I2C and SPI.

Default:

00000

Function:

The Mode Select pins determine the operational mode of the device as detailed in Tables 7-10. The options include:

Selection of the Digital Interface Format which determines the required relationship between the Left/Right clock, serial clock and serial data as detailed in Figures 20-23

Selection of the standard 15µs/50µs digital de-emphasis filter response, Figure 28, which requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates.

Selection of the appropriate clocking mode to match the input sample rates.

M4 M3 M2 M1 M0 PDN

3.4 POWER DOWN

Mode Control Register (address 01h)

76543210

CAL MUTE

M4 M3 M2 M1 M0 PDN

Access:

R/W in I2C and SPI.

Default:

1 - Powered Down

Function:

The analog and digital sections will be placed into a power-down mode when this function is enabled. This bit must be cleared to resume normal operation.

PDN MODE

0 Disabled 1 Enabled

Table 3.

DS288PP1 13

4.0 PIN DESCRIPTION

CS4396

Reset RST See Description M4(AD0/CS See Description M3(AD1/CDIN) FILT- Reference Ground See Description M2(SCL/CCLK) CMOUT Common ModeS Voltage See Description M0(SDA/CDOUT) AOUTL- Differential Output

Digital Ground DGND AOUTL+ Differential Output

Digital Power VD VA Analog Power Digital Power VD AGND Analog Ground

Digital Ground DGND AOUTR+ Differential Output

Master Clock MCLK AOUTR- Differential Output

Serial Clock SCLK AGND Analog Ground

Left/Right Clock LRCK MUTEC

Serial Data SDATA C/H

See Description M1 MUTE

Reset - RST

Pin 1, Input Function:

The device enters a low power mode and all internal state machines registers are reset when low. When high, the device will be in a normal operation mode .

) FILT+ Reference Filter

2 3 4 5

5 6

6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VREF Voltage Reference

Mute Control Control port/Hardware select Soft Mute

RST

0 1

Digital Ground - DGND

Pins 6 and 9, Inputs Function:

Digital Power - VD

Pins 7 and 8, Input Function:

Master Clock - MCLK

Pin 10, Input Function:

Enabled Normal operation mode

Digital ground reference.

Digital power supply. Typically 5.0 to 3.0 VDC.

The master clock frequency must be either 256x, 384x, 512x or 768x the input sample rate in Single Speed Mode; either 128x, 192x 256x or 384x the input sample rate in Double Speed Mode; or 64x, 96x 128x or 192x the input sample rate in Quad Speed Mode. Tables 4-6 illustrate the standard audio sample rates and the required master clock frequencies.

DESCRIPTION

14 DS288PP1

CS4396

Sample Rate

(kHz)

32 8.1920 12.2880 16.3840 24.5760

44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640

Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Frequencies

Sample Rate

(kHz)

64 8.1920 12.2880 16.3840 24.5760

88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640

Table 5. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies

Sample Rate

(kHz)

176.4 11.2896 16.9344 22.5792 33.8688 192 12.2880 18.4320 24.5760 36.8640

Table 6. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies

Serial Clock - SCLK

256x 384x 512x 768x

128x 192x 256x 384x

64x 96x 128x 192x

MCLK (MHz)

Pin 11, Input Function:

Clocks individual bits of serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by either the Mode Control Byte in Control Port Mode or the M0 - M4 pins in Hardware Mode. The options are detailed in Figures 20-23

Left/Right Clock - LRCK

Pin 12, Input Function:

The Left/Right clock determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures 20-23

Serial Audio Data - SDATA

Pin 13, Input Function:

Two’s complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are detailed inin Figures 20-23

Soft Mute - MUTE

Pin 15, Input Function:

The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-

DS288PP1 15

CS4396

cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias voltage on the outputs will be retained and MUTEC

The converter analog outputs will mute when enabled. The bias voltage on the outputs will be retained and MUTEC

will go active during the mute period.

will go active at the completion of the ramp period.

will release immediately on setting MUTE = 1.

Mute

0 1

Control Port / Hardware Mode Select - C/H

Enabled Normal operation mode

DESCRIPTION

Pin 16, Input Function:

Determines if the device will operate in either the Hardware Mode or Control Port Mode.

C/H

0 1

Mute Control - MUTEC

Hardware Mode Enabled Control Port Mode Enabled

DESCRIPTION

Pin 17, Output Function:

The

Mute Control pin goes low during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks

Analog Ground - AGND

Pins 18 and 21, Inputs Function:

Analog ground refer ence.

and pops.

Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- , AOUTL+

Pins 19, 20, 23 and 24, Outputs Function:

The full scale differential analog output level is specified in the Analog Characteristics specifications table.

Analog Power - VA

Pin 22, Input Function:

Power for the analog and reference circuits. Typically 5VDC.

16 DS288PP1

Common Mode Voltage - CMOUT

Pin 25, Output Function:

Filter connection for internal bias voltage, typically 50% of VREF. Capacitors must be connected from CMOUT to analog ground, as shown in Figure 4. CMOUT has a typical source impedence of 25 kΩ and any current drawn from this pin will alter device performance

Reference Ground - FILT-

Pin 26, Input Function:

Ground reference for the internal sampling circuits. Must be connected to analog ground.

Reference Filter - FILT+

Pin 27, Output Function:

Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog ground, as shown in Figure 4. The recommended values will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 120 Hz. FILT+ is not intended to supply external current.

CS4396

Voltage Reference Input- VREF

Pin 28, Input Function:

Analog voltage reference. Typically 5VDC.

HARDWARE MODE Mode Select - M0, M1, M2, M3, M4

Pins 2, 3, 4, 5 and 14, Inputs Function:

The Mode Select pins determine the operational mode of the device as detailed in Tables 7-10. The options include;

Selection of the Digital Interface Format which determines the required relationship between the Left/Right clock, serial clock and serial data as detailed in Figures 20-23

Selection of the appropriate clocking mode to match the input sample rates.

CONTROL PORT MODE Address Bit 0 / Chip Select - AD0 / CS

Pin 2, Input Function:

In I2C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.

DS288PP1 17

Address Bit 1 / Control Data Input - AD1/CDIN

Pin 3, Input Function:

In I2C mode, AD1 is a chip address bit. CDIN is the control data input line for the control port interface in SPI mode.

Serial Control Interface Clock - SCL/CCLK

Pin 4, Input Function:

In I2C mode, SCL clocks the serial control data into or from SDA/CDOUT. In SPI mode, CCLK clocks the serial data into AD1/CDIN and out of SDA/CDOUT.

Serial Control Data I/O - SDA/CDOUT

Pin 5, Input/Output Function:

In I2C mode, SDA is a data input/output. CDOUT is the control data output for the control port interface in SPI mode.

M1 - Mode Select

CS4396

Pin 14, Input Function:

This pin is not used in Control Port Mode and must be terminated to ground.

18 DS288PP1

5.0 APPLICATIONS

5.1 Recommended Power-up Sequence

1. Hold RST low until the power supplies, master, and left/right clocks are stable.

2. Bring RST high.

CS4396

DS288PP1 19

CS4396

6.0 CONTROL PORT INTERFACE

The control port is used to load all the internal settings of the CS4396. The operation of the control port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.

The control port has 2 modes: SPI and I2C, with the CS4396 operating as a slave device in both modes. If I2C operation is desired, AD0/CS should be tied to VD or DGND. If the CS4396 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected.

6.1 SPI Mode

In SPI mode, CS is the CS4396 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller, CDOUT is the data output and the chip address is 0010000. The data is clocked on the rising edge of CCLK.

Figure 5 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W). The next 8 bits form the Memory Address Pointer (MAP), which is set to 01h. The next 8 bits are the data which will be placed into the register designated by the MAP.

6.2 I2C Mode

In I2C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 2. There is no CS pin. Pins AD0 and AD1 form the partial chip address and should be tied to VD or DGND as required. The 7-bit address field, which is the first byte sent to the CS4396, must be 00100(AD1)(AD0) where (AD1) and (AD0) match the setting of the AD0 and AD1 pins. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then foll owed by the dat a to be written. If the operat ion is a read, then the contents of the register pointed to by the MAP will be output after the chip address.

For more information on I2C, please see “The I2C-Bus Specification: Version 2.0”, listed in the References

section.

Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved Reserved Reserved MAP2 MAP1 MAP0

00000001

INCR (Auto MAP Increment Enable) MAP0-2 (Memory Address Pointer)

Default = ‘0’ Default = ‘001’ 0 - Disabled 1 - Enabled

20 DS288PP1

CS4396

DS288PP1 21

CS4396

M4 M1

(DIF1)

00 0 00 1 01 0 01 1

(DIF0)

DESCRIPTION FORMAT FIGURE

Left Justified, up to 24-bit data

S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data

020 121 222 323

Table 7. Single Speed (16 to 50 kHz) Digital Interface Format Options

M4 M3

(DEM1)

00 0 00 1 01 0 01 1

(DEM0)

DESCRIPTION FIGURE

32 kHz De-Emphasis

44.1 kHz De-Emphasis 48 kHz De-Emphasis De-Emphasis Disabled

Table 8. Single Speed (16 to 50 kHz) De-Emphasis Options

M4 M3 M2 M1 M0 DESCRIPTION

11100 11101 11110 11111

Left Justified up to 24-bit data, Format 0

S up to 24-bit data, Format 1 Right Justified 16-bit data, Format 2 Right Justified 24-bit data, Format 3

Table 9. Double Speed (50 to 100 kHz) Sample Rate Mode Opt ions

M4 M3 M2 M1 M0 DESCRIPTION

11000 11001 11010 11011

Left Justified up to 24-bit data, Format 0

S up to 24-bit data, Format 1 Right Justified 16-bit data, Format 2 Right Justified 24-bit data, Format 3

Table 10. Quad (100 to 200 kHz) Sample Rate Mode Options

19 19 19

22 DS288PP1

-20

-40

-60

-80

-100

Amplitude dB

-120

-140

-160

0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.6

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.570.58 0.59 0.6

Frequency (normalized to Fs)

Figure 7. Single-speed Transition Band Figure 8. Single-speed Stopband Rejection

CS4396

-20

-40

-60

-80

-100

Amplitude dB

-120

-140

-160

0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1

Freque ncy (normali z ed to Fs)

-1

-2

-3

-4

-5

-6

Amplitude dB

-7

-8

-9

-10

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52

Frequency (normal i zed to Fs)

0.1

0.08

0.06

0.04

0.02 0

-0.02

Amplitude dB

-0.04

-0.06

-0.08

-0.1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45

Frequency (normal i z ed to Fs)

Figure 9. Single-speed Transition Band Figure 10. Single-speed Frequency Response

-20

-40

-60

-80

Amplitude dB

-100

-120

-140

0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1

Freque ncy (normali z ed to Fs)

DS288PP1 23

CS4396

24 DS288PP1

CS4396

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

Right Channel

LSB

DS288PP1 25

7.0 PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

CS4396

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

8.0 REFERENCES

1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2) CDB4397 Evaluation Board Datasheet

3) “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.

http://www.semiconductors.philips.com

26 DS288PP1

9.0 PACKAGE DIMENSIONS

28L SOIC (300 MIL BODY) PACKAGE DRAWING

CS4396

SEATING

PLANE

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.093 0.104 2.35 2.65

A1 0.004 0.012 0.10 0.30

B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.697 0.713 17.70 18.10 E 0.29G10

0.299 7.40 7.60

e 0.040 0.060 1.02 1.52

H 0.394 0.419 10.00 10.65

L 0.016 0.050 0.40 1.27

∝

0° 8° 0° 8°

JEDEC #: MS-013

∝

DS288PP1 27

CIRRUS LOGIC CS4396 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Description

TABLE OF CONTENTS

TABLE OF FIGURES

1.0 CHARACTERISTICS/SPECIFICATIONS

ANALOG CHARACTERISTICS (T

Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz

Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz

Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz

ANALOG CHARACTERISTICS (Continued)

Power Supplies

Analog Output

DIGITAL CHARACTERISTICS (T

ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)

RECOMMENDED OPERATING CONDITIONS

SWITCHING CHARACTERISTICS (T

Figure 1. Serial Audio Input Timing

SWITCHING CHARACTERISTICS - CONTROL PORT

Figure 2. I2C Control Port Timing

Figure 3. SPI Control Port Timing

2.0 TYPICAL CONNECTION DIAGRAM

Figure 4. Typical Connection Diagram - Hardware Mode (Control Port Mode)

3.0 REGISTER DESCRIPTION

3.1 DIFFERENTIAL DC OFFSET CALIBRATION

3.2 SOFT MUTE

3.3 MODE SELECT

3.4 POWER DOWN

4.0 PIN DESCRIPTION

Reset - RST

Digital Ground - DGND

Digital Power - VD

Master Clock - MCLK

Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Frequencies

Table 5. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies

Table 6. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies

Serial Clock - SCLK

Left/Right Clock - LRCK

Serial Audio Data - SDATA

Soft Mute - MUTE

Control Port / Hardware Mode Select - C/H

Mute Control - MUTEC

Analog Ground - AGND

Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- , AOUTL+

Analog Power - VA

Common Mode Voltage - CMOUT

Reference Ground - FILT-

Reference Filter - FILT+

Voltage Reference Input- VREF

Address Bit 1 / Control Data Input - AD1/CDIN

Serial Control Interface Clock - SCL/CCLK

Serial Control Data I/O - SDA/CDOUT

M1 - Mode Select

5.0 APPLICATIONS

5.1 Recommended Power-up Sequence

6.0 CONTROL PORT INTERFACE

6.1 SPI Mode

6.2 I2C Mode

Memory Address Pointer (MAP)

Table 9. Double Speed (50 to 100 kHz) Sample Rate Mode Opt ions

Figure 7. Single-speed Transition Band Figure 8. Single-speed Stopband Rejection

Figure 9. Single-speed Transition Band Figure 10. Single-speed Frequency Response

7.0 PARAMETER DEFINITIONS

8.0 REFERENCES

9.0 PACKAGE DIMENSIONS

28L SOIC (300 MIL BODY) PACKAGE DRAWING