Cirrus Logic CS4360-KZ, CS4360-BZ, CDB4360 Datasheet

CS4360

24-Bit, 192 kHz 6 Channel D/A Converter

Features

l 24-Bit Conversion
l 102 dB Dynamic Range
l -90 dB THD+N
l +3 V to +5 V Power Supply
l Digital Volume Control with Soft Ramp

– 119 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions

l Low Power Consumption

– 105 mW with 3 V supply

l ATAPI Mixing
l Low Clock Jitter Sensitivity
l Popguard Technology

and Pops

I

®

for Control of Clicks

Description

The CS4360 is a c omplete 6-channel digital-to-analo g
system including d igital in terpolati on, four th-ord er delta­sigma digital-to-ana log c onv ers ion , digi tal de -e mph as is,
volume control, channel mixing and analog filtering. The
advantages of this archi tec ture i nc lud e: id eal di fferent ial
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera­ture and a high tolerance to clock jitter.

The CS4360 accepts data at audio sa mple rates from
4 kHz to 200 kHz, consumes very little po wer and oper­ates over a wide power supply range. These features are
ideal for cost-sensitive, multi-channel audio systems in­cluding DVD players, A/V receivers, set-top boxes,
digital TVs and VCRs, mini-component systems, and
mixing consoles.

ORDERING INFORMATION

CS4360-KS -10 to 70 °C 28-pin SOIC
CS4360-BS -40 to 85 °C 28-pin SOIC
CS4360-KZ -10 to 70 °C 28-pin TSSOP
CS4360-BZ -40 to 85 °C 28-pin TSSOP
CDB4360 Evaluation Board

DIF0/SDA/CDIN M1/AD0/CS

Interpolation Filter

Interpolation Filter

Interpolation Filter

RST

VLS

SCLK

LRCK

SD I N1

SD I N2

SD I N3

MCLK

DIF1/SCL/CCLK

Serial P ort

2

÷

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

M2

VLC

MUTEC1 MUTEC2 MUTEC3

Control Port

VD

Volume ControlInterpolation Filter Analog Filter AO UT A1

Mixe r

Volume Control

Volume ControlInterpolation Filter Analog Filter AO UT A2

Mixe r

Volume Control

Volume ControlInterpolation Filter Analog Filter AO UT A3

Mixe r

Volume Control

VA

GND

GND

Mute Control

∆Σ

DAC

∆Σ

DAC

∆Σ

DAC

∆Σ

DAC

∆Σ

DAC

∆Σ

DAC

External

Analog Filter

Analog Filter

Analog Filter

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2001

(All Rights Reserved)

AO UTB1

AO UTB2

AO UT B3

VQ

FILT+

FEB ‘01

DS517PP1

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS............................. ...... ....... ...... ....... ...... ....... ..... 5

ANALOG CHARACTERISTICS................................................................................................ 5

POWER AND THERMAL CHARACTERISTICS . ....... ...................................... ....... ...... ....... ..... 7

DIGITAL CHARACTERISTICS................................................................................................. 7

ABSOLUTE MAXIMUM RATINGS ...........................................................................................7

RECOMMENDED OPERATING CONDITIONS.......................................................................8

SWITCHING CHARACTERISTICS ....... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ..................9

SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT ....................10

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ...............................11

2. TYPICAL CONNECTION DIAGRAM....................................................................................... 12

3. REGISTER QUICK REFERENCE ...........................................................................................13

4. REGISTER DESCRIPTIONS...................................................................................................14

4.1 Mode Control 1 (address 01h)......................................................................................... 14

4.1.1 Auto-mute (AMUTE) ......................................................................................................14

4.1.2 Digital Interface Format (DIF) ........................................................................................14

4.1.3 De-Emphasis Control (DEM) .........................................................................................15

4.1.4 Functional Mode (FM)....................................................................................................15

4.2 Invert Signal (address 02h).............................................................................................15

4.2.1 Invert Signal Polarity (INV_xx).......................................................................................15

4.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h)
Mixing Control Pair 2 (Channels A2 & B2) (address 04h)

Mixing Control Pair 3 (Channels A3 & B3) (address 05h).............................................15

4.3.1 ATAPI Channel Mixing and Muting (ATAPI) ..................................................................16

4.4 Volume Control (addresses 06h - 0Bh)............................................................................ 16

4.4.1 Mute (MUTE) ................................................................................................................16

4.4.2 Volume Control (xx_VOL).............................................................................................17

4.5 Mode Control 2 (address 0Dh)........................................................................................17

4.5.1 Soft Ramp and Zero Cross Control (SZC).....................................................................17

4.5.2 Control Port Enable (CPEN).......................................................................................... 18

4.5.3 Power Down (PDN)........................................................................................................18

4.5.4 Popguard® Transient Control (POPG) ......................................................................... 18

4.5.5 Freeze Controls (FREEZE)............................................................................................18

4.5.6 Master Clock Divide Enable (MCLKDIV) .......................................................................18

4.5.7 Single Volume Control (SNGLVOL)...............................................................................19

4.6 Revision Register (Read Only) (address 0Dh)...............................................................19

CS4360

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Preliminary product inf o rmation describes products whi ch are i n production, but for whi c h ful l characterization data i s not yet available. Advance p roduct infor­mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warran t y , pa tent infringement, an d limitation of liability. No re s p onsibility is assumed b y Cirrus Logic, Inc. for the use of this informa tion, including
use of this inf orma t i on as the basis for manufacture or sale o f a ny i t e ms, nor for infringements of paten t s or other rights of third parties. This docum ent is the
property of Cirrus Logic, Inc. a nd by furni shing th is i nformati on, Cir rus L ogic, In c. grant s no l icense, express or i mpli ed under any patent s, mask work righ ts,
copyrights, trademarks, trad e secrets o r ot her i ntellect ual pro pert y right s of Cirrus L ogic, I nc. Ci rrus L ogic, In c., cop yright owner of the in forma tion co ntaine d
herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is gi ven for simi lar inf ormat ion con tai ned on a ny Cirru s Logic we bsite or disk. T his consent does not extend to othe r
copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,
Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com

2 DS517PP1

.

CS4360

4.6.1 Revision Indicator (REV) [Read Only] ........................................................................... 19

5. PIN DESCRIPTION..................................................... ...... ...... ....... ...... ....... ...... ....... ...... .......... 20

6. APPLICATIONS ...................................................................................................................... 23

6.1 Grounding and Power Supply Decoupling........................................................................ 23

6.2 Oversampling Modes........................................................................................................ 23

6.3 Recommended Power-up Sequence................................................................................ 23

6.4 Popguard® Transient Control........................................................................................... 23

7. CONTROL PORT INTERFACE........................... ....... ...... ...... ....... ...... ....... ...... ....... ...... .......... 24

7.1 Enabling the Control Port ................................................................................................. 24

7.2 Format Selection .............................................................................................................. 24

7.3 Two-Wire Format.............................................................................................................. 24

7.3.1 Writing in Two-Wire Format ................................................................................. 24

7.3.2 Reading in Two-Wire Format............................................................................... 25

7.4 SPI Format ....................................................................................................................... 25

7.4.1 Writing in SPI ....................................................................................................... 25

7.5 Memory Address Pointer (MAP)...................................................................................... 26

7.5.1 INCR (Auto Map Increment Enable).............................................................................. 26

7.5.2 MAP (Memory Address Pointer).................................................................................... 26

8. PARAMETER DEFINITIONS................................................................................................... 32

Total Harmonic Distortion + Noise (THD+N) .......................................................................... 32

Dynamic Range...................................................................................................................... 32

Interchannel Isolation ............................................................................................................. 32

Interchannel Gain Mismatch................................................................................................... 32

Gain Error............................................................................................................................... 32

Gain Drift ................................................................................................................................ 32

9. REFERENCES......................................................................................................................... 32

10. PACKAGE DIMENSIONS ..................................................................................................... 33

LIST OF FIGURES

Figure 1. Serial Mode Input Timing ............................................................................................... 9

Figure 2. Control Port Timing - Two-Wire Format ....................................................................... 10

Figure 3. Control Port Timing - SPI Format ................................................................................. 11

Figure 4. Typical Connection Diagram ........................................................................................ 12

Figure 5. Control Port Timing, Two-Wire Format ........................................................................ 25

Figure 6. Control Port Timing, SPI Format .................................................................................. 25

Figure 7. Base-Rate Stopband Rejection .................................................................................... 27

Figure 8. Base-Rate Transition Band .......................................................................................... 27

Figure 9. Base-Rate Transition Band (Detail) ............................................................................. 27

Figure 10. Base-Rate Passband Ripple ........................................................................................ 27

Figure 11. High-Rate Stopband Rejection .................................................................................... 27

Figure 12. High-Rate Transition Band ........................................................................................... 27

Figure 13. High-Rate Transition Band (Detail) .............................................................................. 28

Figure 14. High-Rate Passband Ripple ......................................................................................... 28

Figure 15. Output Test Load ......................................................................................................... 28

Figure 16. Maximum Loading ........................................................................................................ 28

Figure 17. CS4360 Format 0 - Left Justified upto 24-bit Data ....................................................... 29

Figure 18. CS4360 Format 1 - I

Figure 19. CS4360 Format 2 - Right Justified 16-bit Data ............................................................ 29

Figure 20. CS4360 Format 3 - Right Justified 24-bit Data ............................................................ 29

Figure 21. CS4360 Format 4 - Right Justified 20-bit Data ............................................................ 30

2

S upto 24-bit Data ...................................................................... 29

DS517PP1 3

Figure 22. CS4360 Format 5 - Right Justified 18-bit Data ............................................................30

Figure 23. De-Emphasis Curve .....................................................................................................30

Figure 24. ATAPI Block Diagram ..................................................................................................31

LIST OF TABLES

Table 1. Digital Interface Formats - Control Port Mode....................................................................14

Table 2. ATAPI Decode....................................................................................................................16

Table 3. Example Digital Volume Settings ....................................................................................... 17

Table 4. Digital Interface Formats - Stand Alone Mode....................................................................21

Table 5. Mode Selection...................................................................................................................21

Table 6. Single-Speed Mode Common Clock Frequencies..............................................................22

Table 7. Double-Speed Mode Common Clock Frequencies ............................................................22

Table 8. Quad-Speed Mode Common Clock Frequencies............................................................... 22

CS4360

4 DS517PP1

CS4360

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; for Single-Speed Mode,

Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz; for Double-Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz,
MCLK = 12.288 MHz; for Quad-Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz; Measure­ment Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R

VA = VD = VLS = VLC),

VA = 5 V VA = 3 V

Parameter

Symbol Min Typ Max Min Typ Max Unit

CS4360-KS/-KZ Dynamic Performance (Note 1)

Specified Temperature Range T
Dynamic Range (Note 2)

unweighted

A-Weighted

40 kHz Bandwidth A-Weighted
Total Harmonic Distortion + Noise (Note 2)

0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 102 - - 102 - dB

A

THD+N -

-10 - 70 -10 - 70 °C

TBD
TBD

-

-

-

-

CS4360-BS/-BZ Dynamic Performance (Note 3)

Specified Temperature Range T
Dynamic Range (Note 2)

unweighted

A-Weighted

40 kHz Bandwidth A-Weighted
Total Harmonic Distortion + Noise (Note 2)

0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 102 - - 102 - dB

A

THD+N -

-40 - 85 -40 - 85 °C

TBD
TBD

-

-

-

-

= 10 kΩ, CL = 10 pF (see Figure 15).

L

99
102
100

-91

-79

-39

99
102
100

-91

-79

-39

-

-

-

TBD

-

-

-

-

-

TBD

-

-

TBD
TBD

-

-

-

-

TBD
TBD

-

-

-

-

94
97
97

-91

-74

-34

94
97
97

-91

-74

-34

-

-

-

TBD

-

-

-

-

-

TBD

-

-

dB
dB
dB

dB
dB
dB

dB
dB
dB

dB
dB
dB

Notes: 1. CS4360-KS/-KZ parts are tested at 25 °C.

2. One-half LSB of triangular PDF dither is added to data.

3. CS4360-BS/-BZ parts are tested at the extremes of the specified temperature range and Min/Max
performance numbers are guaranteed across the specified temperature range, T
taken at 25 °C.

. Typical numb ers are

A

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Unit

Combined Digital and On-chip Analog Filter Response - Single-Speed Mode (Note 4)

Passband (Note 5)

to -0.05 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -.02 - +.035 dB
StopBand .5465 - - Fs

DS517PP1 5

0
0

-

-

.4535
.4998

Fs
Fs

CS4360

Parameter Symbol Min Typ Max Unit

StopBand Attenuation (Note 6) 50 - - dB
Group Delay tgd - 9/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s

De-emphasis Error (Relative to 1 kHz) Fs = 32 kHz
Control Port Mode Fs = 44.1 kHz
(Note 7) Fs = 48 kHz

Fs = 32 kHz

Stand-Alone Mode Fs = 44.1 kHz

Fs = 48 kHz

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode (Note 4)

Passband (Note 5)

to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB
StopBand .577 - - Fs
StopBand Attenuation (Note 6) 55 - - dB
Group Delay tgd - 4/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - ±0.23/Fs - s

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode (Note 4)

Passband (Note 5)

to -3 dB corner 0 - .25 Fs

Frequency Response 10 Hz to 20 kHz -0.7 - 0 dB
Group Delay tgd - 1.5/Fs - s

-

-

-

-

-

-

0
0

-

-

-

-

-

-

-

-

+.2/-.1

+.05/-.14

+0/-.22
+1.5/-0

+.05/-.14

+.2/-.4

.4621
.4982

dB
dB
dB
dB
dB
dB

Fs
Fs

Parameters Symbol Min Typ Max Units

Analog Output

Full Scale Output Voltage 0.60•VA0.66•VA0.72•V
Quiescent Voltage V
Quiescent Pin External Load I

Q

Q

- 0.5•V

A

--TBDVDC

-VDC

Vpp

A

Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
AC-Load Resistance (Note 8) R
Load Capacitance C
Output Impedance Z

L
L

OUT

3--kΩ

--100pF

- 100 - Ω

Notes: 4. F il t er r es po nse is gu ar a nte ed by de sig n.

5. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 - 12) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

6. For Single-Speed Mode, the Measurement Bandwidth is .5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is .577 Fs to 1.4 Fs.

7. De-emphasis is available onl y in Si ngl e-Sp eed Mode.

8. Refer to Figure 16.

6 DS517PP1

CS4360

POWER AND THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current normal operation, All Supplies = 5 V
(Note 9)

All Supplies = 3 V

Interface current (Note 10)

power-down state (all supplies) (Note 11)

I
I
I

I
I
I
I

LS
LC

pd

A
D
A
D

Power Dissipation (Note 9)
All Supplies = 5 V normal operation

power-down (Note 11)

All Supplies = 3 V normal operation

power-down (Note 11)

Package Thermal Resistance SOIC (-KS & -BS)

TSSOP (-KZ & -BZ)

Power Supply Rejection Ratio (1 kHz) (Note 12)

(60 Hz)

θ

JA

θ

JC

θ

JA

θ

JC

PSRR
PSRR

Notes: 9. Current consumption is directly proportional to Fs. Typ and Max values are based on highest FS

10. I

11. Power down mode is defined as RST

measured with no external loading on pin 12 (SDA).

LC

= Low with all clock and data lines held static.

12. Valid with the recommended capacitor values on FILT+ and V

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

as shown in Figure 4.

CM

22
25
21
14

0.002

0.002

0.016

235

0.080
105

0.048

TBD
TBD
TBD
TBD

60
40

-

-

-

-

-

-

-

TBD

-

TBD

-

-

-

-

-

-

-

°C/Watt
°C/Watt
°C/Watt
°C/Watt

mA
mA
mA
mA
mA
mA
mA

mW
mW
mW
mW

dB
dB

DIGITAL CHARACTERISTICS (For -KS & -KZ parts T

= -10 to +70°C; for -BS & -BZ parts TA = -40

A

to +85°C; VD = 2.0 V - 5.5 V, VLC = VLS = 1.8 V - 5.5 V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage Serial Audio Data Port

Control Port

Low-Level Input Voltage Serial Audio Data Port

Control Port

Input Leakage Current I

V

IH

V

IH

V

IL

70%
70%

-

-

in

--±10µA

-

-

-

-

-

-

20%
20%

VLS

VLC
VLS

VLC

Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 3 - mA
MUTEC High-Level Output Voltage V
MUTEC Low-Level Output V oltage V

OH

OL

VA V

0V

DS517PP1 7

CS4360

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog power

Digital power

Serial Audio Data Interface power

Control Port Interface power

Input Current, Any Pin Except Supplies I

Digital Input Voltage Serial audio data interface

Control port interface
Ambient Operating Temperature (power applied) T
Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

DC Power Supply Analog Power

Digital Power

Serial Audio Data Interface Power (No te 13)

Control Port Interface Power (Note 14)

13. Applies to pins 2, 3, 4, 5, 6, and 7.

14. Applies to pins 10, 11, 12, and 13.

VA

VD
VLS
VLC

V

IND_S

V

IND_C

VLS
VLC

in

A

stg

VA

VD

-0.3

-0.3

-0.3

-0.3

- ±10 mA

-0.3

-0.3

-55 125 °C

-65 150 °C

2.7

2.0

1.8

1.8

5
5
5
5

6.0

6.0

6.0

6.0

VLS + 0.4
VLC + 0.4

5.5
VA

5.5

5.5

V
V
V
V

V
V

V
V
V
V

8 DS517PP1

CS4360

SWITCHING CHARACTERISTICS (For -KS & -KZ parts T

-40 to +85°C; VLS = 1.7 V to 5.5 V; Inputs: Logic 0 = 0 V, Logic 1 = VLS CL = 20 pF)

Parameters Symbol Min Typ Max Units

Input Sample Rate Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode
LRCK Duty Cycle 45 50 55 %
MCLK Duty Cycle 405060%
SCLK Frequency

SCLK Frequency Note 15
SCLK rising to LRCK edge delay t

SCLK rising to LRCK edge setup time t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t

Notes: 15. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.

F

s

F

s

F

s

slrd
slrs

sdlrs

sdh

= -10 to +70°C; for -BS & -BZ parts TA =

A

4

50

100

-

­20 - - ns
20 - - ns
20 - - ns
20 - - ns

-

-

-

-MCLK/2Hz

-MCLK/4Hz

50
100
200

kHz
kHz
kHz

LRCK

SCLK

SDATA

t

slrd

t

sdlrs

t

slrs

t

sclkl

t

sdh

t

sclkh

Figure 1. Serial Mode Input Timing

DS517PP1 9

CS4360

SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT

(Note 16) (For -KS & -KZ parts T

Inputs: Logic 0 = GND, Logic 1 = VLC, C

Parameter Symbol Min Max Unit

SCL Clock Frequency f

Rising Edge to Start t

RST
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 17) t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling (Note 18) t

= -10 to +70°C; for -BS & -BZ parts TA = -40 to +85°C; VLC = 1.7 V - 5.5 V;

A

=30pF)

L

buf

hdst

low
high
sust

hdd
sud

rc

fc

susp

ack

scl

irs

, t
, t

-100kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

rc
fc

-1µs

-300ns

4.7 - µs

- (Note 19) ns

Notes: 16. The Two-Wire Format is compatible with the I

17. Data must be held for sufficient time to bridge the transition time, t

18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

19. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.

5

------------ -------- ­256 Fs×

5

------------ -------- ­128 Fs×

RST

t

irs

Stop Start

SDA

SCL

t

buf

t

hdst

t

low

t

high

t

hdd

t

sud

2

C protocol.

t

ack

, of SCL.

fc

5

------------ -----­64 Fs×

Repeated

Start

t

sust

t

t

hdst

Stop

rd

t

rc

t

fd

t

fc

t

susp

Figure 2. Control Port Timing - Two-Wire Format

10 DS517PP1

CS4360

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(For -KS & -KZ parts TA = -10 to +70°C; for -BS & -BZ parts TA = -40 to +85°C; VLC = 1.7 V - 5.5 V; Inputs: Logic
0 = GND, Logic 1 = VLC, C

CCLK Clock Frequency f

Rising Edge to CS Falling t

RST
CCLK Edge to CS

High Time Between Transmissions t

CS

Falling to CCLK Edge t

CS

Falling (Note 20) t

CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 21) t
Rise Time of CCLK and CDIN (Note 22) t
Fall Time of CCLK and CDIN (Note 22) t

=30pF)

L

Parameter Symbol Min Max Unit

sclk

srs

spi
csh
css

scl
sch
dsu

dh

r2

f2

-6MHz
500 - ns
500 - ns

1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns

-100ns

-100ns

Notes: 20. t

21. Data must be held for sufficient time to bridge the transition time of CCLK.

22. For F

only needed before first falling edge of CS after RST rising edge. t

spi

< 1 MHz.

SCK

RST

CS

CCLK

CDIN

t

srs

t

t

css

spi

tr2t

t

t

scl

sch

f2

t

t

dsu

dh

Figure 3. Control Port Timing - SPI Format

= 0 at all other times.

spi

t

csh

DS517PP1 11

2. TYPICAL CONNECTION DIAGRAM

CS4360

+3 V to +5 V *

+1.8 V to +5 V *

Configuration

Digital

Audio

Source

µ C/

Mode

1 µF

0.1 µF

+

0.1 µF

7

MCLK

6

LRCK1

5

SCLK1

2

LRCK2

3

SCLK2

4

SDIN1

4

SDIN2

4

SDIN3

4

SDIN4

1

VLS

10

RST

11

DIF1/SCL/CCLK

12

DIF0/SDA/CDIN

13

M1/AD0/CS

15

M2

22

VA

CS4360

8

VD

AOUT1A

AOUT1B

MUTEC1

AOUT2A

AOUT2B

MUTEC2

AOUT3A

AOUT3B

0.1 µF

27

+

3.3 µF

26

+

3.3 µF

28

24

+

3.3 µF

23

+

3.3 µF

25

20

+

3.3 µF

19

+

3.3 µF

10 k

10 k

10 k

10 k

10 k

10 k

+

560

560

560

560

560

560

1 µF

Ω

Ω

Ω

Ω

Ω

Ω

+3 V to +5 V *

* All supplies can be tied together

Ω

C

C

C

C

C

C

OPTIONAL

CIRCUIT

OPTIONAL

CIRCUIT

OPTIONAL

CIRCUIT

Ω

Ω

Ω

Ω

Ω

MUTE

MUTE

MUTE

R

L

R

L

R

L

R

L

R

L

R

L

AOUTA1

AOUTB1

AOUTA2

AOUTB2

AOUTA3

AOUTB3

FILT+

VQ

18

16

0.1 µ

+

3.3 µF

F

R

+560

C =

L

π

560)

Fs(R

4

L

15

F

+

3.3 µF

0.1 µ

+1.8 V to +5 V *

0.1 µF

14

VLC

GND

9

MUTEC3

GND

21

Figure 4. Typical Connection Diagram

12 DS517PP1

CS4360

3. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

1h Mode Control 1 AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0

default

2h Invert Signal Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

default

3h Mixing Control P1 Reserved Reserved Reserved Reserved P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0

default

4h Mixing Control P2 Reserved Reserved Reserved Reserved P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0

default

5h Mixing Control P3 Reserved Reserved Reserved Reserved P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0

default

6h Volume Control A1 A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0

default

7h Volume Control B1 B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0

default

8h Volume Control A2 A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0

default

9h Volume Control B2 B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0

default

0Ah Volume Control A3 A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0

default

0Bh Volume Control B3 B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0

default

0Ch Mode Control 2 SZC1 SZC0 CPEN PDN POPG FREEZE MCLKDIV SNGLVOL

default

0Dh Revision Indicator Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0

default

10000000

00000000

00001001

00001001

00001001

00000000

00000000

00000000

00000000

00000000

00000000

10

0000XXXX

0

11000

DS517PP1 13

CS4360

4. REGISTER DESCRIPTIONS

Note: All registers are read/write in Two-Wire mode and write only in SPI, unless otherwise noted.

4.1 Mode Control 1 (address 01h)

76543210

AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0

10000000

4.1.1 AUTO-MUTE (AMUTE)

Default = 1

0 - Disabled
1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. The quiescent voltage on the output will be retained
and the Mute Control pin will go active during the mute period. The muting function is affected, similar
to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.

4.1.2 DIGITAL INTERFACE FORMAT (DIF)

Default = 000

- Format 0 (Left Justified, up to 24-bit data)

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Fi gu res 17- 22.

DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE

000
001
010
011
100
101
110
111

Table 1. Digital In terface Formats - Control Port Mode

Left Justified, up to 24-bit data,

2

I

S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved

017
118
219
320
421
522

14 DS517PP1

4.1.3 DE-EMPHASIS CONTROL (DEM)

Default = 00

00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz

Function:

Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re­sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 23)

Note: De-emphasis is only available in Single-Speed Mode.

4.1.4 FUNCTIONAL MODE (FM)

Default = 00

00 - Single-Speed Mode (2 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Reserved

CS4360

Function:

Selects the required range of input sample rates.

4.2 Invert Signal (address 02h)

76543210

Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

00000000

4.2.1 INVERT SIGNAL POLARITY (INV_XX)

Default = 0

0 - Disabled
1 - Enabled

Function:

When enabled, these bits invert the signal polarity for each of their respective channels.

4.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h)
Mixing Control Pair 2 (Channels A2 & B2) (address 04h)
Mixing Control Pair 3 (Channels A3 & B3) (address 05h)

76543210

Reserved Reserved Reserved Reserved PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0

00001001

DS517PP1 15

4.3.1 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

Default = 1001 - AOUTAx = L, AOUTBx = R (Stereo)

Function:

The CS4360 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 2 and Figure 24 for additional information.

Note: All mixing functions occur prior to the digital volume control. Mixing only occurs in channel pairs.

ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx

0000 MUTE MUTE
0001 MUTE R
0010 MUTE L
0011 MUTE [(L+R)/2]
0100 R MUTE
0101 R R
0110 R L
0111 R [(L+R)/2]
1000 L MUTE
1001 L R
1010 L L
1011 L [(L+R)/2]
1100[(L+R)/2] MUTE
1101[(L+R)/2] R
1110[(L+R)/2] L
1111[(L+R)/2][(L+R)/2]

Table 2. ATAPI Decode

CS4360

4.4 Volume Control (addresses 06h - 0Bh)

76543210

xx_MUTE xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0

00001001

4.4.1 MUTE (MUTE)

Default = 0

0 - Disabled
1 - Enabled

Function:

The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output
will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero
Cross bits. The MUTEC pin will go active during the mute period if the Mute function is enabled for
both channels in the pair.

16 DS517PP1

CS4360

4.4.2 VOLUME CONTRO L (XX_VOL)

Default = 0

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments
from 0 to -119 dB. Volume settings are decoded as shown in Table 3. The volume changes are im­plemented as dictated by the Soft Ramp and Zero Cross bits. All volume settings less than -119 dB
are equivalent to enabling the MUTE bit.

Binary Code Decimal Value Volume Setting

0001010 0 dB
0010100 -20 -20 dB
0101000 -40 -40 dB

0111100 -60 -60 dB

1011010 -90 -90 dB

Tab l e 3. Example Digital Volume Settings

4.5 Mode Control 2 (address 0Dh)

76543210

SZC1 SZC0 CPEN PDN POPG FREEZE MCLKDIV SNGLVOL

10011000

4.5.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10

00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp and Zero Cross

Function:

Immediate Change

When Immediate Change is selected all level changes will be implemented immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon­itored and implemented for each channel.

Soft Ramp

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods.

Soft Ramp and Zero Cross

Soft Ramp and Zero Cross dictates that signal level changes, either by attenuation changes or mut­ing, will occur in 1/8 dB steps and will be implemented on successive signal zero crossings. The 1/8
dB level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms to

21.3 ms at 48 kHz sample rate) if the signal does not encounter zero crossings. The zero cross func­tion is independently monitored and implemented for each channel.

DS517PP1 17

4.5.2 CONTROL PORT ENABLE (CPEN)

Default = 0

0 - Disabled
1 - Enabled

Function:

The Control Port will become active and reset to the default settings when this function is enabled.

4.5.3 POWER DOWN (PDN)

Default = 1

0 - Disabled
1 - Enabled

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the

control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation in Control Port mode can occur.

4.5.4 POPGUA RD® TRANSIE NT CONTROL (POPG)

CS4360

Default = 1

0 - Disabled
1 - Enabled

Function:

The PopGuard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to
the quiescent voltage during power-on or power-off when this function is enabled. Please see section

6.4 for implementation details.

4.5.5 FREEZE CONTROLS (FREEZE)

Default = 0

0 - Disabled
1 - Enabled

Function:

This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To make multiple changes in the control port registers take effect simulta­neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

4.5.6 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0

0 - Disabled
1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all
other internal circuitry.

18 DS517PP1

CS4360

4.5.7 SINGLE VOLUME CONTROL (SNGLVOL)

Default = 0

0 - Disabled
1 - Enabled

Function:

The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel
Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.

4.6 Revision Register (Read Only) (address 0Dh)

76543210

Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0

0000XXXX

4.6.1 REVISION INDICATOR (REV) [READ ONLY]

Default = none

0001 - Revision A
0010 - Revision B
0011 - Revision C
etc.

Function:

This read-only register indicates the revision level of the device.

DS517PP1 19

5. PIN DESCRIPTION

CS4360

Serial Audio Power VLS MUTEC1 Mute Control 1

Serial Data Input 1 SDIN1 AOUTA1 Analog Output A1
Serial Data Input 2 SDIN2 AOUTB1 Analog Output B1
Serial Data Input 3 SDIN3 MUTEC2 Mute Control 2

Serial Clock SCLK AOUTA2 Analog Output A2

Left/Right Clock LRCK AOUTB2 Analog Output B2

Master Clock MCLK VA Analog Power

Digital Power VD GND Ground

Ground GND AOUTA3 Analog Output A3

Reset RST

DIF1 / SCL/ CCLK DIF1/SCL/CCLK MUTEC3 Mute Control 3

DIF0 / SDA / CDIN DIF0/SDA/CDIN VQ Quiescent Voltage

Mode1 / AD0 / CS

M1/AD0/CS FILT+ Positive Voltage Reference

1

1
2

2
3
4
5

5
6

6
7
8
9
10
11
12
13

Control Port Power VLC M2 Mode 2

Pin Name # Pin Description

VLS

SDIN1
SDIN2
SDIN3

SCLK
LRCK

MCLK

VD

GND

RST

VLC

FILT+

Serial Audio Interface Power (

1

face. Refer to the Recommended Operating Conditions for appropriate voltages. Applies to pins 2-7.
Serial Audio Data Input (

2

AOUT1x, SDIN2 corresponds to AOUT2x and SDIN3 corresponds to AOUT3x.

3
4

Serial Clock (

5

Left / Right Clock (

6

audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
Master Clock (

7

several standard audio sample rates and the required master clock frequency.

8 Digital Power (

ing Conditions for appropriate voltages.
Ground (

9

21

Reset (

10

settings when low. The control port cannot be accessed when Reset is low.
Control Port Interface Power (

14

vides power for bidirectional control port pins. Refer to the Recommended Operating Conditions for
appropriate voltages. Applies to pins 10-13 and 15.

Positive Voltage Reference (

16

Requires the capacitive decoupling to GND as shown in the Typical Connection Diagr am.

Input

) - Serial clock for the serial audio interface.

Input

Input

) - Clock source for the delta-sigma modulator and digital filters. Table 6 illustrates

Input

) - Positive power supply for the digital section. Refer to the Recommended Operat-

Input

) - Ground reference. Should be connected to analog ground.

Input

) - The device enters a low power mode and all internal registers are reset to their default

Input

Input

) - Input for two’s complement serial audio data. SDIN1 corresponds to

) - Determines which channel, Left or Right, is currently active on the serial

Input

Output

28
27
26

25
24
23
22
21
20
19

AOUTB3 Analog Output B3

18
17
16
1514

) - Determines the required signal level for the serial audio inter-

) - Determines the requir ed s ignal level for the contro l p ort a nd pro-

) - Positive reference voltage for the internal sampling circuits.

20 DS517PP1

CS4360

VQ

VA

AOUTA1
AOUTB1
AOUTA2
AOUTB2
AOUTA3
AOUTB3

MUTEC1
MUTEC2
MUTEC3

Control Port
Definitions

SCL/CCLK

SDA/CDIN

AD0/CS

Stand-Alone
Definitions

DIF1
DIF0

M1
M2

17 Quiescent Voltage (

coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance. However, VQ can be used
to bias the analog circuitry assuming there is no AC signal component and the DC current is less than
the maximum specified in the Analog Characteristics and Specifications section.

22 Analog Power (

ating Conditions for appropriat e voltages.
Analog Outputs (

19

tics specifications table.

20

Output

) - Filter connection for internal quiescent voltage. VQ must be capacitively

Input

) - Positive power supply for the analog section. Refer to the Recommended Oper-

Output

) - The full scale analog line output level is specified in the Analog Characteris-

23
24
26
27

18

Mute Control (
power-down or if the master cloc k to left/ri ght clock frequen cy ratio is incorrec t. This pin is intende d to be

25

used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single

28

supply system. The use of an external mute circuit is not mandatory but may be desired for designs
requiring the absolute minimum in extraneous clicks and pops.

Serial Control Port Clock (

11

resistor to the logic interface voltage in Two-Wire mode as shown in the Typical Connection Diagram.
Serial Control Data (

12

pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the
input data line for the control port interface in SPI format.

Address Bit 0 (Two-Wire) / Control Port Chip Select (SPI) (

13

Two-Wire format; CS

Digital Interface Format (

11

and serial data is defined by the Digital Interface Format selection. Refer to Table 4.

12

Output

) - The Mute Control pin goes high during power-up initialization, reset, muting,

Input

) - Serial clock for the serial control port. Requires an external pull-up

Input/Output

is the chip select signal for SPI format.

) - SDA is a data I/O line in Two-Wire format and requires an external

Input/Output

Input

) - The required relationship between the Left/Right clock, serial clock

) - AD0 is a chip address pin

DIF1 DIF0 DESCRIPTION

0 0 Left Justified, up to 24-bit data
01

2

I

S, up to 24-bit data
1 0 Right Justified, 16-bit data
1 1 Right Justified, 24-bit data

Table 4. Digital Interface Formats - Stand Alone Mode

13

Mode Selection (

15

Input

) - Determines the operational mode of the device as detailed in Table 5.

M2 M1 MODE

0 0 Single-Speed without de-emphasis (4 to 50 kHz sample rates)
0 1 Single-Speed with de-emphasis (32 to 48 kHz sample rates)
1 0 Double-Speed (50 to 100 kHz sample rates)
1 1 Quad-Speed (100 to 200 kHz sample rates)

Table 5. Mode Selection

DS517PP1 21

CS4360

.

Sample Rate

(kHz)

32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 32.7680 45.1584
48 12.2880 18.4320 24.5760 36.8640 49.1520

256x 384x 512x 768x 1024x*

MCLK (MHz)

* Requires MCLKDIV bit = 1

Table 6 . Si ngle-Speed Mode Common Clock Frequencies

Sample Rate

(kHz)

64 8.1920 12.2880 16.3840 24.5760 32.7680

88.2 11.2896 16.9344 22.5792 33.8688 45.1584
96 12.2880 18.4320 24.5760 36.8640 49.1520

128x 192x 256x 384x 512x*

MCLK (MHz)

* Requires MCLKDIV bit = 1

Table 7. Do uble-Speed Mode Common Clock Frequencies

Sample Rate

(kHz)

176.4 11.2896 16.9344 22.5792 33.8688 45.1584
192 12.2880 18.4320 24.5760 36.8640 49.1520

64x 96x 128x 192x 256x*

MCLK (MHz)

* Requires MCLKDIV bit = 1

Table 8. Qua d- Speed Mode Common Clock Frequencies

22 DS517PP1

CS4360

6. APPLICATIONS

6.1 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS4360
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figure 4 shows the recommended power arrange­ment with VA, VD, VLS and VLC connected to
clean supplies. Decoupling capacitors should be lo­cated as close to the device package as possible. If
desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be placed on each supply pin.

6.2 Oversampling Modes

The CS4360 operates in one of three oversampling
modes based on the input sample rate. Mode selec­tion is determined by the FM pins in Stand-Alone
mode or the FM bits in Control Port mode. Single­Speed mode supports input sample rates up to 50
kHz and uses a 128x oversampling ratio. Double­Speed mode supports input sample rates up to 100
kHz and uses an oversampling ratio of 64x. Quad­Speed mode supports input sample rates up to 200
kHz and uses an oversampling ratio of 32x.

6.3 Recommended Power-up Sequence

1. Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, the
control port is reset to its default settings and VQ
will remain low.

2. Bring RST high. The device will remain in a low

power state with VQ low and will initiate the
Stand-Alone power-up sequence. The control port
will be accessible at this time. If Control P ort oper­ation is desired, write the CPEN bit prior to the
completion of the Stand-Alone power-up se­quence, approximately 512 LRCK cycles in Sin­gle-Speed Mode (1024 LRCK cycles in Double­Speed Mode, and 2048 LRCK cycles in Quad­Speed Mode). Writing this bit will halt the Stand-

Alone power-up sequence and initialize the control
port to its default settings. The desired register set­tings can be loaded while keeping the PDN bit set
to 1.

3. If Control Port Mode is selected via the CPEN
bit, set the PDN bit to 0 whic h will initiate the po w­er-up sequence, which requires approximately

50 µS when the POPG bit is set to 0. If the POPG
bit is set to 1, see Section 6.4 for total power-up
timing.

6.4 Popguard® Transient Control

The CS4360 uses a novel technique to minimize
the effects of output transients during power-up
and power-down. This technique, when used with
external DC-blocking capacitors in series with the
audio outputs, minimizes the audio transients com­monly produced by single-ended single-supply
converters.

When the device is initially powered-up, the audio
outputs, AOUTAx and AOUTBx, are clamped to
GND. Following a delay of approximately 1000
sample periods, each output begins to ramp toward
the quiescent voltage. Approximately 10,000
left/right clock cycles later, t he outputs reach VQ
and audio output begins. This gradual voltage
ramping allows time for the external DC-blocking
capacitor to charge to the quiescent voltage, mini­mizing the power-up transient.

To prevent transients at power-down, the device
must first enter its power-down state. When this oc­curs, audio output ceases and the internal output
buffers are disconnected from AOUTAx and
AOUTBx. In their place, a soft-start current sink is
substituted which allows the DC-blocking capaci­tors to slowly discharge. Once this charge is dissi­pated, the power to the device may be turned off
and the system is ready for the next power-on.

To prevent an audio transient at the next power-on,
it is necessary to ensure that the DC-blocking ca­pacitors have fully discharged before turning off

DS517PP1 23

CS4360

the power or exiting the power-down state. If not, a
transient will occur when the audio output s are ini­tially clamped to GND. The time that the device
must remain in the power-down state is related to
the value of the DC-blocking capacitance. For ex­ample, with a 3.3 µF capacitor, the minimum pow-

er-down time will be approximately 0.4 seconds.
Use of the Mute Control function is recommended

for designs requiring the absolute minimum in ex­traneous clicks and pops. Also, use of the Mute
Control function can enable the system designer to
achieve idle channel noise/signal-to-noise ratios
which are only limited by the external mute circuit.
See the CDB4360 data sheet for a suggested mute
circuit.

7. CONTROL PORT INTERFACE

The control port is used to load all the internal set­tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob­lems, the control port pins should remain static if
no operation is required.

The CS4360 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written, allowing block reads or writes of succes­sive registers.

7.1 Enabling the Control Port

On the CS4360 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CPEN bit. This
is done by performing a Two-Wire or SPI write.
Once the control port is enabled, these pins are ded­icated to control port functionality.

To prevent audible artifacts the CPEN bit (see Sec­tion 4.5.2) should be set prior to the completion of
the Stand-Alone power-up sequence, approximate­ly 512 LRCK cycles in Single-Speed Mode (1024

LRCK cycles in Double-Speed Mode, and 2048
LRCK cycles in Quad-Speed Mode). Writing this
bit will halt the Stand-Alone power-up sequence
and initialize the control port to i ts d efaul t s ettings.
Note, the CPEN bit can be set any time after RST
goes high; however, setting this bit after the St and­Alone power-up sequence has completed can cause
audible artifacts.

7.2 Format Selection

The control port has 2 formats: SPI and Two-Wire,
with the CS4360 operating as a slave device.

If Two-Wire operation is desired, AD0/CS should
be tied to VLS or GND. If the CS4360 ever detects
a high to low transition on AD0/CS after power-up
and after the control port is activated, SPI format
will be selected.

7.3 Two-Wire Format

In Two-Wire Format, SDA is a bidirectional data
line. Data is clocked into and out of the part by the
clock, SCL, with a clock to data relationship as
shown in Figure 5. The receiving device should
send an acknowledge (ACK) after each byte re­ceived. There is no CS pin. Pin AD0 form the par­tial chip address and should be tied to VLS or GND
as required. The upper 6 bits of the 7 bit address
field must be 001000.

Note, MCLK is required during all two-wire trans­actions. The Two-Wire format is compatible with
the I2C protocol. Please see reference 2 for further
details.

7.3.1 Writing in Two-Wire Format

To communicate with the CS4360, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then fol­lowed by the data to be written. To write multiple
registers, continue providing a clock and data,

24 DS517PP1

SDA

SCL

001000

ADDR
AD0

R/W

ACK

DATA
1-8

Note 1

ACK

DATA
1-8

CS4360

ACK

Start

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Figure 5. Control Port Timing, Two-Wire Format

waiting for the CS4360 to acknowledge between
each byte. To end the transaction, send a STOP
condition.

7.3.2 Reading in Two-Wire Format

To communicate with the CS4360, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (high for a r ead). The c ontents of the reg­ister pointed to by the MAP will be output after the
chip address. To read multiple registers, continue
providing a clock and issue an ACK after each
byte. To end the transaction, send a STOP condi­tion.

7.4 SPI Format

In SPI format, CS is the CS4360 chip select signal,
CCLK is the control port bit cl ock, C DIN i s the in­put data line from the microcontroller and the chip
address is 0010000. CS, CCLK and CDIN are all

Stop

inputs and data is clocked in on the rising edge of
CCLK.

Note that the CS4360 is write-only when in SPI
format.

7.4.1 Writing in SPI

Figure 6 shows the operation of the control port in
SPI format. To write to a register, bring CS low.
The first 7 bits on CDIN form the chip address and
must be 0010000. The eighth bit is a read/write in­dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
MAP. To write multiple registers, keep CS low and
continue providing clocks on CCLK. End the read
transaction by setting CS high.

CS

CCLK

CHIP

ADDRESS

CDIN

DS517PP1 25

0010000

MAP = Memory Address Pointer

Figure 6. Control Port Timing, SPI Format

R/W

MAP

MSB

byte 1

DATA

LSB

byte n

7.5 Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

7.5.1 INCR (AUTO MAP INCREMENT ENABLE)

Default = ‘0’

0 - Disabled
1 - Enabled

7.5.2 MAP (MEMORY ADDRESS POIN TER)

Default = ‘0000’

CS4360

26 DS517PP1

CS4360

Figure 7. Base-Rate Stopband Rejection Figure 8. Base-Rate Transition Band

Figure 9. Base-Rate Transition Band (Detail) Figure 10. Base-Rate Passband Ripple

Figure 11. High-Rate Stopband Rejection Figure 12. High-Rate Transition Band

DS517PP1 27

CS4360

100

50

75

25

2.5

51015

Safe Operating

Region

Capacitive Load -- C (pF)

L

Resistive Load -- R (kΩ)

L

125

3

20

Figure 16. Maximum Loading

Figure 13. H i gh-Rate Transition Band (D etail) Figure 14. High-Rate Passband Ripple

3.3 µF

AOUTx

+

V

out

AGND

R

L

Figure 15. Output Test Load

C

L

28 DS517PP1

CS4360

LRCK

SCLK

SDINx +3 +2 +1

B-1-2-3-4-5

MS

Left Channel

+5 +4

Figure 17. CS4360 Format 0 - Left Justified up to 24-bit Data

LRCK

SCLK

SDINx +3 +2 +1LSB+5 +4

MSB-1

-2 -3 -4 -5

Left Channel

Figure 18. CS4360 Format 1 - I2S up to 24-bit Data

LRCK

SCLK

Left Channel

LSB

MSB-1

MSB-1

-2 -3 -4

-2 -3 -4

Right Channel

+3 +2 +1

+5 +4

Right Channel

+3 +2 +1LSB+5 +4

Right Channel

B

LS

SDINx

LRCK

SCLK

SDINx

15 14 13 12 11 10

32 clocks

6543210987

15 14 13 12 11 10

6543210987

Figure 19. CS4360 Format 2 - Right Justified 16-bit Data

Left Channel

0

23 22 21 20 19 18

32 clocks

65432107

23 22 21 20 19 18

Right Channel

65432107

Figure 20. CS4360 Format 3 - Right Justified 24-bit Data

DS517PP1 29

CS4360

LRCK

SCLK

SDINx

10 6543210987

17 16 17 16

19 18 19 18

Left Channel

15 14 13 12 11 10

32 clocks

6543210987

15 14 13 12 11 10

Figure 21. CS4360 Format 4 - Right Justified 20-bit Data

LRCK

SCLK

SDINx

10

17 16 17 16

Left Channel

15 14 13 12 11 10

32 clocks

6543210987

15 14 13 12 11 10

Figure 22. CS4360 Format 5 - Right Justified 18-bit Data

Gain

dB

Right Channel

Right Channel

6543210987

0dB

-10dB

T1=50 µs

T2 = 15 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 23. De-Emphasis Curve

Frequency

30 DS517PP1

A

Left Channel

Audio Data

Right Channel

Audio Data

A Channel

Σ

B Channel

Figure 24. ATAPI Block Diagram

Volume

Control

& Mute

Volume

Control
& Mute

CS4360

Aout

AoutB

DS517PP1 31

8. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
affect the measurement. This measurement technique has been accepted by the Audio Engineering So­ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

CS4360

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

9. REFERENCES

1) “How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters” by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2) CDB4360 Evaluation Board Datasheet

2

3) “The I
http://www.semiconductors.philips.com

C Bus Specification: Version 2.0” Philips Semiconductors, December 1998.

32 DS517PP1

10.PACKAGE DIMENSIONS

28L SOIC (300 MIL BODY) PACKAGE DRAWING

1

b

CS4360

HE

c

D

SEATING

PLANE

e

A

A1

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A 0.093 0.098 0.104 2.35 2.50 2.65

A1 0.004 0.008 0.012 0.10 0.20 0.30

b 0.013 0.017 0.020 0.33 0.42 0.51
C 0.009 0.011 0.013 0.23 0.28 0.32
D 0.697 0.705 0.713 17.70 17.90 18.10

E 0.291 0.295 0.299 7.40 7.50 7.60

e 0.040 0.050 0.060 1.02 1.27 1.52
H 0.394 0.407 0.419 10.00 10.34 10.65

L 0.016 0.026 0.050 0.40 0.65 1.27

∝

0° 4° 8° 0° 4° 8°

JEDEC #: MS-013

Controlling Dimension is Millimeters

∝

L

DS517PP1 33

CS4360

28L TSSOP (4.4 mm BODY) PACKAGE DRAWING

N

1

23

TOP VIEW

D

E

e

2

b

SIDE VIEW

A2

A1

A

SEATING

PLANE

L

INCHES MILLIMETERS

1

E1

END VIEW

NOTE

DIM MIN NOM MAX MIN NOM MAX

A----0.47----1.20
A1 0.002 0.004 0.006 0.05 0.10 0.15
A2 0.03150 0.035 0.04 0.80 0.90 1.00

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.378 BSC 0.382 BSC 0.386 BSC 9.60 BSC 9.70 BSC 9.80 BSC 1

E 0.248 0.2519 0.256 6.30 6.40 6.50
E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.029 0.50 0.60 0.75

∝

0° 4° 8° 0° 4° 8°

∝

JEDEC #: MO-153

Controlling Dimension is Millimeters.

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

34 DS517PP1

• Notes •