Cirrus Logic CS4360-KZ, CS4360-BZ, CDB4360 Datasheet

CS4360

24-Bit, 192 kHz 6 Channel D/A Converter

Features

l 24-Bit Conversion
l 102 dB Dynamic Range
l -90 dB THD+N
l +3 V to +5 V Power Supply
l Digital Volume Control with Soft Ramp

– 119 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions

l Low Power Consumption

– 105 mW with 3 V supply

l ATAPI Mixing
l Low Clock Jitter Sensitivity
l Popguard Technology

and Pops

I

®

for Control of Clicks

Description

The CS4360 is a c omplete 6-channel digital-to-analo g
system including d igital in terpolati on, four th-ord er delta­sigma digital-to-ana log c onv ers ion , digi tal de -e mph as is,
volume control, channel mixing and analog filtering. The
advantages of this archi tec ture i nc lud e: id eal di fferent ial
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera­ture and a high tolerance to clock jitter.

The CS4360 accepts data at audio sa mple rates from
4 kHz to 200 kHz, consumes very little po wer and oper­ates over a wide power supply range. These features are
ideal for cost-sensitive, multi-channel audio systems in­cluding DVD players, A/V receivers, set-top boxes,
digital TVs and VCRs, mini-component systems, and
mixing consoles.

ORDERING INFORMATION

CS4360-KS -10 to 70 °C 28-pin SOIC
CS4360-BS -40 to 85 °C 28-pin SOIC
CS4360-KZ -10 to 70 °C 28-pin TSSOP
CS4360-BZ -40 to 85 °C 28-pin TSSOP
CDB4360 Evaluation Board

DIF0/SDA/CDIN M1/AD0/CS

Interpolation Filter

Interpolation Filter

Interpolation Filter

RST

VLS

SCLK

LRCK

SD I N1

SD I N2

SD I N3

MCLK

DIF1/SCL/CCLK

Serial P ort

2

÷

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

M2

VLC

MUTEC1 MUTEC2 MUTEC3

Control Port

VD

Volume ControlInterpolation Filter Analog Filter AO UT A1

Mixe r

Volume Control

Volume ControlInterpolation Filter Analog Filter AO UT A2

Mixe r

Volume Control

Volume ControlInterpolation Filter Analog Filter AO UT A3

Mixe r

Volume Control

VA

GND

GND

Mute Control

∆Σ

DAC

∆Σ

DAC

∆Σ

DAC

∆Σ

DAC

∆Σ

DAC

∆Σ

DAC

External

Analog Filter

Analog Filter

Analog Filter

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2001

(All Rights Reserved)

AO UTB1

AO UTB2

AO UT B3

VQ

FILT+

FEB ‘01

DS517PP1

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS............................. ...... ....... ...... ....... ...... ....... ..... 5

ANALOG CHARACTERISTICS................................................................................................ 5

POWER AND THERMAL CHARACTERISTICS . ....... ...................................... ....... ...... ....... ..... 7

DIGITAL CHARACTERISTICS................................................................................................. 7

ABSOLUTE MAXIMUM RATINGS ...........................................................................................7

RECOMMENDED OPERATING CONDITIONS.......................................................................8

SWITCHING CHARACTERISTICS ....... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ..................9

SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT ....................10

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ...............................11

2. TYPICAL CONNECTION DIAGRAM....................................................................................... 12

3. REGISTER QUICK REFERENCE ...........................................................................................13

4. REGISTER DESCRIPTIONS...................................................................................................14

4.1 Mode Control 1 (address 01h)......................................................................................... 14

4.1.1 Auto-mute (AMUTE) ......................................................................................................14

4.1.2 Digital Interface Format (DIF) ........................................................................................14

4.1.3 De-Emphasis Control (DEM) .........................................................................................15

4.1.4 Functional Mode (FM)....................................................................................................15

4.2 Invert Signal (address 02h).............................................................................................15

4.2.1 Invert Signal Polarity (INV_xx).......................................................................................15

4.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h)
Mixing Control Pair 2 (Channels A2 & B2) (address 04h)

Mixing Control Pair 3 (Channels A3 & B3) (address 05h).............................................15

4.3.1 ATAPI Channel Mixing and Muting (ATAPI) ..................................................................16

4.4 Volume Control (addresses 06h - 0Bh)............................................................................ 16

4.4.1 Mute (MUTE) ................................................................................................................16

4.4.2 Volume Control (xx_VOL).............................................................................................17

4.5 Mode Control 2 (address 0Dh)........................................................................................17

4.5.1 Soft Ramp and Zero Cross Control (SZC).....................................................................17

4.5.2 Control Port Enable (CPEN).......................................................................................... 18

4.5.3 Power Down (PDN)........................................................................................................18

4.5.4 Popguard® Transient Control (POPG) ......................................................................... 18

4.5.5 Freeze Controls (FREEZE)............................................................................................18

4.5.6 Master Clock Divide Enable (MCLKDIV) .......................................................................18

4.5.7 Single Volume Control (SNGLVOL)...............................................................................19

4.6 Revision Register (Read Only) (address 0Dh)...............................................................19

CS4360

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Preliminary product inf o rmation describes products whi ch are i n production, but for whi c h ful l characterization data i s not yet available. Advance p roduct infor­mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warran t y , pa tent infringement, an d limitation of liability. No re s p onsibility is assumed b y Cirrus Logic, Inc. for the use of this informa tion, including
use of this inf orma t i on as the basis for manufacture or sale o f a ny i t e ms, nor for infringements of paten t s or other rights of third parties. This docum ent is the
property of Cirrus Logic, Inc. a nd by furni shing th is i nformati on, Cir rus L ogic, In c. grant s no l icense, express or i mpli ed under any patent s, mask work righ ts,
copyrights, trademarks, trad e secrets o r ot her i ntellect ual pro pert y right s of Cirrus L ogic, I nc. Ci rrus L ogic, In c., cop yright owner of the in forma tion co ntaine d
herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is gi ven for simi lar inf ormat ion con tai ned on a ny Cirru s Logic we bsite or disk. T his consent does not extend to othe r
copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,
Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com

2 DS517PP1

.

CS4360

4.6.1 Revision Indicator (REV) [Read Only] ........................................................................... 19

5. PIN DESCRIPTION..................................................... ...... ...... ....... ...... ....... ...... ....... ...... .......... 20

6. APPLICATIONS ...................................................................................................................... 23

6.1 Grounding and Power Supply Decoupling........................................................................ 23

6.2 Oversampling Modes........................................................................................................ 23

6.3 Recommended Power-up Sequence................................................................................ 23

6.4 Popguard® Transient Control........................................................................................... 23

7. CONTROL PORT INTERFACE........................... ....... ...... ...... ....... ...... ....... ...... ....... ...... .......... 24

7.1 Enabling the Control Port ................................................................................................. 24

7.2 Format Selection .............................................................................................................. 24

7.3 Two-Wire Format.............................................................................................................. 24

7.3.1 Writing in Two-Wire Format ................................................................................. 24

7.3.2 Reading in Two-Wire Format............................................................................... 25

7.4 SPI Format ....................................................................................................................... 25

7.4.1 Writing in SPI ....................................................................................................... 25

7.5 Memory Address Pointer (MAP)...................................................................................... 26

7.5.1 INCR (Auto Map Increment Enable).............................................................................. 26

7.5.2 MAP (Memory Address Pointer).................................................................................... 26

8. PARAMETER DEFINITIONS................................................................................................... 32

Total Harmonic Distortion + Noise (THD+N) .......................................................................... 32

Dynamic Range...................................................................................................................... 32

Interchannel Isolation ............................................................................................................. 32

Interchannel Gain Mismatch................................................................................................... 32

Gain Error............................................................................................................................... 32

Gain Drift ................................................................................................................................ 32

9. REFERENCES......................................................................................................................... 32

10. PACKAGE DIMENSIONS ..................................................................................................... 33

LIST OF FIGURES

Figure 1. Serial Mode Input Timing ............................................................................................... 9

Figure 2. Control Port Timing - Two-Wire Format ....................................................................... 10

Figure 3. Control Port Timing - SPI Format ................................................................................. 11

Figure 4. Typical Connection Diagram ........................................................................................ 12

Figure 5. Control Port Timing, Two-Wire Format ........................................................................ 25

Figure 6. Control Port Timing, SPI Format .................................................................................. 25

Figure 7. Base-Rate Stopband Rejection .................................................................................... 27

Figure 8. Base-Rate Transition Band .......................................................................................... 27

Figure 9. Base-Rate Transition Band (Detail) ............................................................................. 27

Figure 10. Base-Rate Passband Ripple ........................................................................................ 27

Figure 11. High-Rate Stopband Rejection .................................................................................... 27

Figure 12. High-Rate Transition Band ........................................................................................... 27

Figure 13. High-Rate Transition Band (Detail) .............................................................................. 28

Figure 14. High-Rate Passband Ripple ......................................................................................... 28

Figure 15. Output Test Load ......................................................................................................... 28

Figure 16. Maximum Loading ........................................................................................................ 28

Figure 17. CS4360 Format 0 - Left Justified upto 24-bit Data ....................................................... 29

Figure 18. CS4360 Format 1 - I

Figure 19. CS4360 Format 2 - Right Justified 16-bit Data ............................................................ 29

Figure 20. CS4360 Format 3 - Right Justified 24-bit Data ............................................................ 29

Figure 21. CS4360 Format 4 - Right Justified 20-bit Data ............................................................ 30

2

S upto 24-bit Data ...................................................................... 29

DS517PP1 3

Figure 22. CS4360 Format 5 - Right Justified 18-bit Data ............................................................30

Figure 23. De-Emphasis Curve .....................................................................................................30

Figure 24. ATAPI Block Diagram ..................................................................................................31

LIST OF TABLES

Table 1. Digital Interface Formats - Control Port Mode....................................................................14

Table 2. ATAPI Decode....................................................................................................................16

Table 3. Example Digital Volume Settings ....................................................................................... 17

Table 4. Digital Interface Formats - Stand Alone Mode....................................................................21

Table 5. Mode Selection...................................................................................................................21

Table 6. Single-Speed Mode Common Clock Frequencies..............................................................22

Table 7. Double-Speed Mode Common Clock Frequencies ............................................................22

Table 8. Quad-Speed Mode Common Clock Frequencies............................................................... 22

CS4360

4 DS517PP1

CS4360

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; for Single-Speed Mode,

Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz; for Double-Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz,
MCLK = 12.288 MHz; for Quad-Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz; Measure­ment Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load R

VA = VD = VLS = VLC),

VA = 5 V VA = 3 V

Parameter

Symbol Min Typ Max Min Typ Max Unit

CS4360-KS/-KZ Dynamic Performance (Note 1)

Specified Temperature Range T
Dynamic Range (Note 2)

unweighted

A-Weighted

40 kHz Bandwidth A-Weighted
Total Harmonic Distortion + Noise (Note 2)

0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 102 - - 102 - dB

A

THD+N -

-10 - 70 -10 - 70 °C

TBD
TBD

-

-

-

-

CS4360-BS/-BZ Dynamic Performance (Note 3)

Specified Temperature Range T
Dynamic Range (Note 2)

unweighted

A-Weighted

40 kHz Bandwidth A-Weighted
Total Harmonic Distortion + Noise (Note 2)

0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 102 - - 102 - dB

A

THD+N -

-40 - 85 -40 - 85 °C

TBD
TBD

-

-

-

-

= 10 kΩ, CL = 10 pF (see Figure 15).

L

99
102
100

-91

-79

-39

99
102
100

-91

-79

-39

-

-

-

TBD

-

-

-

-

-

TBD

-

-

TBD
TBD

-

-

-

-

TBD
TBD

-

-

-

-

94
97
97

-91

-74

-34

94
97
97

-91

-74

-34

-

-

-

TBD

-

-

-

-

-

TBD

-

-

dB
dB
dB

dB
dB
dB

dB
dB
dB

dB
dB
dB

Notes: 1. CS4360-KS/-KZ parts are tested at 25 °C.

2. One-half LSB of triangular PDF dither is added to data.

3. CS4360-BS/-BZ parts are tested at the extremes of the specified temperature range and Min/Max
performance numbers are guaranteed across the specified temperature range, T
taken at 25 °C.

. Typical numb ers are

A

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Unit

Combined Digital and On-chip Analog Filter Response - Single-Speed Mode (Note 4)

Passband (Note 5)

to -0.05 dB corner

to -3 dB corner
Frequency Response 10 Hz to 20 kHz -.02 - +.035 dB
StopBand .5465 - - Fs

DS517PP1 5

0
0

-

-

.4535
.4998

Fs
Fs

CS4360

Parameter Symbol Min Typ Max Unit

StopBand Attenuation (Note 6) 50 - - dB
Group Delay tgd - 9/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s

De-emphasis Error (Relative to 1 kHz) Fs = 32 kHz
Control Port Mode Fs = 44.1 kHz
(Note 7) Fs = 48 kHz

Fs = 32 kHz

Stand-Alone Mode Fs = 44.1 kHz

Fs = 48 kHz

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode (Note 4)

Passband (Note 5)

to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB
StopBand .577 - - Fs
StopBand Attenuation (Note 6) 55 - - dB
Group Delay tgd - 4/Fs - s
Passband Group Delay Deviation 0 - 20 kHz - ±0.23/Fs - s

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode (Note 4)

Passband (Note 5)

to -3 dB corner 0 - .25 Fs

Frequency Response 10 Hz to 20 kHz -0.7 - 0 dB
Group Delay tgd - 1.5/Fs - s

-

-

-

-

-

-

0
0

-

-

-

-

-

-

-

-

+.2/-.1

+.05/-.14

+0/-.22
+1.5/-0

+.05/-.14

+.2/-.4

.4621
.4982

dB
dB
dB
dB
dB
dB

Fs
Fs

Parameters Symbol Min Typ Max Units

Analog Output

Full Scale Output Voltage 0.60•VA0.66•VA0.72•V
Quiescent Voltage V
Quiescent Pin External Load I

Q

Q

- 0.5•V

A

--TBDVDC

-VDC

Vpp

A

Interchannel Gain Mismatch - 0.1 - dB
Gain Drift - 100 - ppm/°C
AC-Load Resistance (Note 8) R
Load Capacitance C
Output Impedance Z

L
L

OUT

3--kΩ

--100pF

- 100 - Ω

Notes: 4. F il t er r es po nse is gu ar a nte ed by de sig n.

5. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 - 12) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

6. For Single-Speed Mode, the Measurement Bandwidth is .5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is .577 Fs to 1.4 Fs.

7. De-emphasis is available onl y in Si ngl e-Sp eed Mode.

8. Refer to Figure 16.

6 DS517PP1

CS4360

POWER AND THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current normal operation, All Supplies = 5 V
(Note 9)

All Supplies = 3 V

Interface current (Note 10)

power-down state (all supplies) (Note 11)

I
I
I

I
I
I
I

LS
LC

pd

A
D
A
D

Power Dissipation (Note 9)
All Supplies = 5 V normal operation

power-down (Note 11)

All Supplies = 3 V normal operation

power-down (Note 11)

Package Thermal Resistance SOIC (-KS & -BS)

TSSOP (-KZ & -BZ)

Power Supply Rejection Ratio (1 kHz) (Note 12)

(60 Hz)

θ

JA

θ

JC

θ

JA

θ

JC

PSRR
PSRR

Notes: 9. Current consumption is directly proportional to Fs. Typ and Max values are based on highest FS

10. I

11. Power down mode is defined as RST

measured with no external loading on pin 12 (SDA).

LC

= Low with all clock and data lines held static.

12. Valid with the recommended capacitor values on FILT+ and V

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

as shown in Figure 4.

CM

22
25
21
14

0.002

0.002

0.016

235

0.080
105

0.048

TBD
TBD
TBD
TBD

60
40

-

-

-

-

-

-

-

TBD

-

TBD

-

-

-

-

-

-

-

°C/Watt
°C/Watt
°C/Watt
°C/Watt

mA
mA
mA
mA
mA
mA
mA

mW
mW
mW
mW

dB
dB

DIGITAL CHARACTERISTICS (For -KS & -KZ parts T

= -10 to +70°C; for -BS & -BZ parts TA = -40

A

to +85°C; VD = 2.0 V - 5.5 V, VLC = VLS = 1.8 V - 5.5 V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage Serial Audio Data Port

Control Port

Low-Level Input Voltage Serial Audio Data Port

Control Port

Input Leakage Current I

V

IH

V

IH

V

IL

70%
70%

-

-

in

--±10µA

-

-

-

-

-

-

20%
20%

VLS

VLC
VLS

VLC

Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 3 - mA
MUTEC High-Level Output Voltage V
MUTEC Low-Level Output V oltage V

OH

OL

VA V

0V

DS517PP1 7

CS4360

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog power

Digital power

Serial Audio Data Interface power

Control Port Interface power

Input Current, Any Pin Except Supplies I

Digital Input Voltage Serial audio data interface

Control port interface
Ambient Operating Temperature (power applied) T
Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

DC Power Supply Analog Power

Digital Power

Serial Audio Data Interface Power (No te 13)

Control Port Interface Power (Note 14)

13. Applies to pins 2, 3, 4, 5, 6, and 7.

14. Applies to pins 10, 11, 12, and 13.

VA

VD
VLS
VLC

V

IND_S

V

IND_C

VLS
VLC

in

A

stg

VA

VD

-0.3

-0.3

-0.3

-0.3

- ±10 mA

-0.3

-0.3

-55 125 °C

-65 150 °C

2.7

2.0

1.8

1.8

5
5
5
5

6.0

6.0

6.0

6.0

VLS + 0.4
VLC + 0.4

5.5
VA

5.5

5.5

V
V
V
V

V
V

V
V
V
V

8 DS517PP1

CS4360

SWITCHING CHARACTERISTICS (For -KS & -KZ parts T

-40 to +85°C; VLS = 1.7 V to 5.5 V; Inputs: Logic 0 = 0 V, Logic 1 = VLS CL = 20 pF)

Parameters Symbol Min Typ Max Units

Input Sample Rate Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode
LRCK Duty Cycle 45 50 55 %
MCLK Duty Cycle 405060%
SCLK Frequency

SCLK Frequency Note 15
SCLK rising to LRCK edge delay t

SCLK rising to LRCK edge setup time t
SDATA valid to SCLK rising setup time t
SCLK rising to SDATA hold time t

Notes: 15. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.

F

s

F

s

F

s

slrd
slrs

sdlrs

sdh

= -10 to +70°C; for -BS & -BZ parts TA =

A

4

50

100

-

­20 - - ns
20 - - ns
20 - - ns
20 - - ns

-

-

-

-MCLK/2Hz

-MCLK/4Hz

50
100
200

kHz
kHz
kHz

LRCK

SCLK

SDATA

t

slrd

t

sdlrs

t

slrs

t

sclkl

t

sdh

t

sclkh

Figure 1. Serial Mode Input Timing

DS517PP1 9

CS4360

SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT

(Note 16) (For -KS & -KZ parts T

Inputs: Logic 0 = GND, Logic 1 = VLC, C

Parameter Symbol Min Max Unit

SCL Clock Frequency f

Rising Edge to Start t

RST
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 17) t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling (Note 18) t

= -10 to +70°C; for -BS & -BZ parts TA = -40 to +85°C; VLC = 1.7 V - 5.5 V;

A

=30pF)

L

buf

hdst

low
high
sust

hdd
sud

rc

fc

susp

ack

scl

irs

, t
, t

-100kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

rc
fc

-1µs

-300ns

4.7 - µs

- (Note 19) ns

Notes: 16. The Two-Wire Format is compatible with the I

17. Data must be held for sufficient time to bridge the transition time, t

18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

19. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.

5

------------ -------- ­256 Fs×

5

------------ -------- ­128 Fs×

RST

t

irs

Stop Start

SDA

SCL

t

buf

t

hdst

t

low

t

high

t

hdd

t

sud

2

C protocol.

t

ack

, of SCL.

fc

5

------------ -----­64 Fs×

Repeated

Start

t

sust

t

t

hdst

Stop

rd

t

rc

t

fd

t

fc

t

susp

Figure 2. Control Port Timing - Two-Wire Format

10 DS517PP1

CS4360

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(For -KS & -KZ parts TA = -10 to +70°C; for -BS & -BZ parts TA = -40 to +85°C; VLC = 1.7 V - 5.5 V; Inputs: Logic
0 = GND, Logic 1 = VLC, C

CCLK Clock Frequency f

Rising Edge to CS Falling t

RST
CCLK Edge to CS

High Time Between Transmissions t

CS

Falling to CCLK Edge t

CS

Falling (Note 20) t

CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 21) t
Rise Time of CCLK and CDIN (Note 22) t
Fall Time of CCLK and CDIN (Note 22) t

=30pF)

L

Parameter Symbol Min Max Unit

sclk

srs

spi
csh
css

scl
sch
dsu

dh

r2

f2

-6MHz
500 - ns
500 - ns

1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns

-100ns

-100ns

Notes: 20. t

21. Data must be held for sufficient time to bridge the transition time of CCLK.

22. For F

only needed before first falling edge of CS after RST rising edge. t

spi

< 1 MHz.

SCK

RST

CS

CCLK

CDIN

t

srs

t

t

css

spi

tr2t

t

t

scl

sch

f2

t

t

dsu

dh

Figure 3. Control Port Timing - SPI Format

= 0 at all other times.

spi

t

csh

DS517PP1 11