Cirrus Logic CS4348 User Manual

PCM

Serial

Interface

Multibit

Modulator

Interpolation

Filter

Internal
Voltage

Reference

Switched

Capacitor

DAC and

Filter

Serial Audio

Input

Right
Output

Left
Output

Switched

Capacitor

DAC and

Filter

De-emphasis

Multibit

Modulator

Interpolation

Filter

3.3 V or 5 V

CS4344/5/8

10-Pin, 24-Bit, 192 kHz Stereo D/A Converter

Features

 Multi-bit Delta-Sigma Modulator

 24-bit Conversion

 Automatically Detects Sample Rates up to

192 kHz.

 105 dB Dynamic Range

 -90 dB THD+N

 Low Clock-Jitter Sensitivity

 Single +3.3 or +5 V Power Supply

 Filtered Line-Level Outputs

 On-chip Digital De-emphasis

 Popguard

 Small 10-pin TSSOP Package

®

Technology

Description

The CS4344 family members (CS4344, CS4345, and
CS4348) are complete, stereo digital-to-analog output
systems including interpolation, multibit D/A conversion
and output analog filtering in a 10-pin package. The
CS4344 family supports major audio data interface for­mats. Individual devices differ only in the supported
interface format.

The CS4344 family is based on a fourth-order multibit
delta-sigma modulator with a linear analog low-pass fil­ter. This family also includes autospeed mode detection
using both sample rate and master clock ratio as a
method of auto-selecting sampling rates between 2 kHz
and 200 kHz.

The CS4344 family contains on-chip digital deempha­sis, operates from a single +3.3 V or +5 V power supply,
and requires minimal support circuitry. These features
are ideal for DVD players & recorders, digital televi­sions, home theater and set top box products, and
automotive audio systems.

The CS4344 family is available in a 10-pin TSSOP
package in both Commercial (-10 to +85 °C) and Auto­motive grades (-40 to +85 °C). See Section 8. “Ordering

Information” on page 23 for complete details.

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2013

(All Rights Reserved)

JUL ‘13

DS613F2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS .............................................................................................................................. 4

2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5

SPECIFIED OPERATING CONDITIONS ............................................................................................... 5

ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 5

DAC ANALOG CHARACTERISTICS .....................................................................................................6

DAC ANALOG CHARACTERISTICS - ALL MODES ............................................................................. 6

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 7

DIGITAL INPUT CHARACTERISTICS ................................................................................................... 8

POWER AND THERMAL CHARACTERISTICS ................................................................................... 8

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE ...................................................... 9

3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 11

4. APPLICATIONS ................................................................................................................................... 12

4.1 Master Clock ................................................................................................................................... 12

4.2 Serial Clock .................................................................................................................................... 12

4.2.1 External Serial Clock Mode ................................................................................................... 12

4.2.2 Internal Serial Clock Mode .................................................................................................... 12

4.3 De-Emphasis .................................................................................................................................. 15

4.4 Initialization and Power-Down ........................................................................................................ 15

4.5 Output Transient Control ................................................................................................................ 15

4.5.1 Power-Up .............................................................................................................................. 15

4.5.2 Power-Down .......................................................................................................................... 15

4.6 Grounding and Power Supply Decoupling ......................................................................................17

4.7 Analog Output and Filtering ............................................................................................................ 17

5. FILTER PLOTS ..................................................................................................................................... 18

6. PARAMETER DEFINITIONS ................................................................................................................ 21

7. PACKAGE DIMENSIONS .................................................................................................................... 22

8. ORDERING INFORMATION ................................................................................................................ 23

8.1 Functional Compatibility ................................................................................................................. 23

8.2 Selection Guide .............................................................................................................................. 23

9. REVISION HISTORY ............................................................................................................................ 24

CS4344/5/8

2

CS4344/5/8

LIST OF FIGURES

Figure 1.Output Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 2.Maximum Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 3.External Serial Mode Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 4.Internal Serial Mode Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5.Internal Serial Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6.Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 7.CS4344 Data Format (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 8.CS4345 Data Format (Left Justified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 9.CS4348 Data Format (Right Justified 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.De-Emphasis Curve (Fs = 44.1kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 11.CS4344/5/8 Initialization and Power-down Sequence . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.Single-Speed Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.Single-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 14.Single-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 15.Single-Speed Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 16.Double-Speed Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 17.Double-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 18.Double-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 19.Double-Speed Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 20.Quad-Speed Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 21.Quad-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 22.Quad-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 23.Quad-Speed Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3

1. PIN DESCRIPTIONS

SDIN AOUTR

DEM

/SCLK VA

LRCK GND

MCLK AOUTL

VQ FILT+

1

2

3

4

5

6

7

8

9

10

Pin Name # Pin Description

SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

/SCLK

DEM

LRCK

MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

VQ 5 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

FILT+

AOUTL

GND 8 Ground (Input) - ground reference.

VA 9 Analog Power (Input) - Positive power for the analog and digital sections.

AOUTR

2 De-Emphasis/External Serial Clock Input (Input) - used for deemphasis filter control or external serial

clock input.

3 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio

data line.

6 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling

circuits.

7 Left Channel Analog Output (Output) - The full scale analog output level is specified in the Analog Char-

acteristics specification table.

10 Right Channel Analog Output (Output) - The full scale analog output level is specified in the Analog

Characteristics specification table.

CS4344/5/8

4

CS4344/5/8

2. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltage
and T

= 25C.)

A

SPECIFIED OPERATING CONDITIONS

(AGND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Nom Max Units

DC Power Supply VA 4.75

3.00

Specified Temperature Range -CZZ

-DZZ

T

A

-10

-40

5.0

3.3

5.25

3.47

-

-

+70
+85

V
V

C
C

ABSOLUTE MAXIMUM RATINGS

(AGND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply VA -0.3 6.0 V
Input Current, Any Pin Except Supplies I
Digital Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T

in

IND

op

stg

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

-±10mA

-0.3 VA+0.4 V

-55 125 °C

-65 150 °C

5

CS4344/5/8

DAC ANALOG CHARACTERISTICS

(Full-Scale Output Sine Wave, 997 Hz (Note 1), Fs = 48/96/192 kHz; Test load RL = 3 k, CL = 10 pF (Figure 1).
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)

5V Nom 3.3V Nom

Parameter

Dynamic Performance for CS4344/5/8-CZZ (-10 to 70°C)

Dynamic Range 18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Dynamic Performance for CS4344/5-DZZ (-40 to 85°C)

Dynamic Range 18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Min Typ Max Min Typ Max Unit

99
96
90
87

-

-

-

-

-

-

95
92
86
83

-

-

-

-

-

-

105
102

96
93

-90

-82

-42

-90

-73

-33

105
102

96
93

-90

-82

-42

-90

-73

-33

-

-

-

-

-85

-76

-36

-84

-67

-27

-

-

-

-

-82

-72

-32

-82

-63

-23

97
94
90
87

93
90
86
83

103
100

96
93

-

-

-

-

-

-

-

-

-

-

-

-

-90

-80

-40

-90

-73

-33

103
100

96
93

-90

-80

-40

-90

-73

-33

-85

-74

-34

-84

-67

-27

-82

-70

-30

-82

-63

-23

-

-

-

-

-

-

-

-

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

dB
dB
dB
dB

dB
dB
dB
dB
dB
dB

Notes:

1. One LSB of triangular PDF dither added to data.

DAC ANALOG CHARACTERISTICS - ALL MODES

Parameter Symbol Min Typ Max Unit

Interchannel Isolation (1 kHz) - 100 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 0.25 dB

Gain Drift - 100 - ppm/°C

Analog Output

Full Scale Output Voltage 0.60•VA 0.65•VA 0.70•VA Vpp

Quiescent Voltage V

Max DC Current draw from an AOUT pin I

Max Current draw from VQ I

Max AC-Load Resistance (see Figure 2 on page 8)R

Max Load Capacitance (see Figure 2 on page 8)C

Output Impedance Z

Q

OUTmax

Qmax

L

L

OUT

6

-0.5•VA-VDC

-10-A

- 100 - A

-3-k

- 100 - pF

- 100 - 

CS4344/5/8

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam­ple rate by multiplying the given characteristic by Fs.) See

Parameter Symbol Min Typ Max Unit

Combined Digital and On-chip Analog Filter Response—Single-Speed Mode

(Note 6)

Passband (Note 2) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -.175 - +.01 dB

StopBand .5465 - - Fs

StopBand Attenuation (Note 3) 50 - - dB

Group Delay tgd - 10/Fs - s

De-emphasis Error (Note 5) Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

0
0

-

-

-

-

-

-

-

-

.35

.4992

+1.5/+0

+.05/-.25

-.2/-.4

Fs
Fs

dB
dB
dB

Combined Digital and On-chip Analog Filter Response—Double-Speed Mode

Passband (Note 2) to +0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -.15 - +.15 dB

StopBand .5770 - - Fs

StopBand Attenuation (Note 3) 55 - - dB

Group Delay tgd - 5/Fs - s

0
0

-

-

.22

.501

Fs
Fs

Combined Digital and On-chip Analog Filter Response—Quad-Speed Mode

Passband (Note 2) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz -.12 - +0 dB

StopBand 0.7 - - Fs

StopBand Attenuation (Note 3) 51 - - dB

Group Delay tgd - 2.5/Fs - s

0
0

-

-

0.110

0.469

Fs
Fs

Notes:

2. Response is clock dependent and will scale with Fs.

3. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.

4. Refer to Figure 2.

5. De-emphasis is available only in Single-Speed Mode.

6. Amplitude vs. Frequency plots of this data are available in “Filter Plots” on page 18.

7

CS4344/5/8

AOUTx

AGND

3.3 µF

V

out

R

L

C

L

100

50

75

25

2.5

51015

Safe Operating

Region

Capacitive Load -- C (pF)

L

Resistive Load -- R (k)

L

125

3

20

DIGITAL INPUT CHARACTERISTICS

Parameters Symbol Min Typ Max Units

High-Level Input Voltage (% of VA) V
Low-Level Input Voltage (% of VA) V
Input Leakage Current (Note 7) I

IH

IL

in

Input Capacitance - 8 - pF

60% - - V

- - 30% V

--±10A

7. Iin for LRCK is ±20 A max.

POWER AND THERMAL CHARACTERISTICS

5 V Nom 3.3 V Nom

Parameters Symbol Min Typ Max Min Typ Max Units

Power Supplies

Power Supply Current normal operation

(Note 8) power-down state (Note 9)

Power Dissipation normal operation

power-down state(Note 9)
Package Thermal Resistance 
Power Supply Rejection Ratio (Note 8) (1 kHz)

(60 Hz)

8. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Variance between speed modes is small.

9. Power down mode is defined when all clock and data lines are held static.

10. Valid with the recommended capacitor values on VQ and FILT+
agram in Section 3.

I

A

I

A

JA

PSRR -

-

-

-

-

22

220
110

1.1

30

-

150

-

-

-

-

-

16

100

53

0.33

21

-

69

-

-95- -95-°C/Watt
50

-

40

-

-

as shown in the typical connection di-

-

-

50
40

-

-

mA

A

mW
mW

dB
dB

Figure 1. Output Test Load

8

Figure 2. Maximum Loading

CS4344/5/8

10

9

SCLK

----------------

tsclkw

2

------------------

10

9

512Fs

----------------------10+

10

9

512Fs

----------------------15+

10

9

384Fs

----------------------15+

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE

Parameters Symbol Min Typ Max Units

MCLK Frequency 0.512 - 50 MHz

MCLK Duty Cycle 45 - 55 %

Input Sample Rate All MCLK/LRCK ratios combined

(Note 11) 256x, 384x, 1024x

256x, 384x
512x, 768x

1152x

128x, 192x

64x, 96x

128x, 192x

External SCLK Mode

LRCK Duty Cycle (External SCLK only) 45 50 55 %

SCLK Pulse Width Low t

SCLK Pulse Width High t

SCLK Duty Cycle 45 50 55 %

SCLK rising to LRCK edge delay t

SCLK rising to LRCK edge setup time t

SDIN valid to SCLK rising setup time t

SCLK rising to SDIN hold time t

Internal SCLK Mode

LRCK Duty Cycle (Internal SCLK only) (Note 12) -50-%

Fs 2

sclkl

sclkh

slrd

slrs

sdlrs

sdh

200

2
84
42
30
50

100
168

50

134

67

34
100
200
200

20 - - ns

20 - - ns

20 - - ns

20 - - ns

20 - - ns

20 - - ns

kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz

SCLK Period (Note 13) t

SCLK rising to LRCK edge t

SDIN valid to SCLK rising setup time t

SCLK rising to SDIN hold time

MCLK / LRCK =1152, 1024, 512, 256, 128, or 64

SCLK rising to SDIN hold time

MCLK / LRCK = 768, 384, 192, or 96

11. Not all sample rates are supported for all clock ratios. See Table 1, “Common Clock Frequencies,” on

page 12 for supported ratio’s and frequencies.

12. In Internal SCLK Mode, the Duty Cycle must be 50%

13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on part type and MC­LK/LRCK ratio. (See Figures 7-9)

sclkw

sclkr

sdlrs

t

sdh

t

sdh

--ns

--ns

--ns

--ns

--ns

1/2 MCLK Period.

9

Figure 3. External Serial Mode Input Timing

sclkh

t

slrs

t

slrd

t

sdlrs

t

sdh

t

sclkl

t

SDATA

SCLK

LRCK

SDATA

*INTERNAL SCLK

LRCK

sclkw

t

sdlrstsdh

t

sclkr

t

The SCLK pulses shown are internal to the CS4344/5/8.

SDATA

LRCK

MCLK

*INTERNAL SCLK

1

N
2

N

* The SCLK pulses shown are internal to the CS4344/5/8.
N equals MCLK divided by SCLK

CS4344/5/8

10

Figure 4. Internal Serial Mode Input Timing

Figure 5. Internal Serial Clock Generation

3. TYPICAL CONNECTION DIAGRAM

DEM/SCLK

8

Audio

Data

Processor

External Clock

MCLK

AGND

AOUTR

CS4344
CS4345
CS4348

SDIN

LRCK

VA

AOUTL

3

1

2

4

9

0.1 µF

+

1µF

7

Left Audio

Output

10

Right Audio

Output

+3.3 V to +5 V

3.3 µF

10 k



C

470

+

R + 470

C=

4Fs(R 470)

R

ext

3.3 µF

10 k



C

470



+

R

ext

ext

ext

+

0.1 µF

10

µF

+

*3.3

µF

6

VQ

FILT+

5

Note*

Note* = This circuitry is intended for applications where the
CS4344/5/8 connects directly to an unbalanced output of
the design. For internal routing applications please see the
DAC analog output characteristics for loading limitations.

For best 20 kHz response

µF*10

*Popguard ramp can be adjusted by
selecting this capacitor value to be

3.3 µF to give 250 ms ramp time
or 10 µF to give a 420 ms ramp
time.

or

CS4344/5/8

Figure 6. Typical Connection Diagram

11

CS4344/5/8

4. APPLICATIONS

The CS4344 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2
and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN).
The Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial
Clock (SCLK) clocks audio data into the input data buffer. The CS4344/5/8 differ in serial data formats as shown in

Figures 7–9.

4.1 Master Clock

MCLK/LRCK must be an integer ratio, as shown in Table 1. The LRCK frequency is equal to Fs, the fre­quency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and
speed mode is detected automatically during the initialization sequence by counting the number of MCLK
transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are
set to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the required
MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and
SCLK must be synchronous.

MCLK (MHz)

LRCK

(kHz)

32 - ---8.1920 12.2880 - - 32.7680 36.8640

44.1
48
64

88.2
96

128

176.4
192

Mode QSM DSM SSM

64x 96x 128x 192x 256x 384x 512x 768x 1024x 1152x

- ---11. 2 8 9 6 16.9344 22.5792 33.8680 45.1580 -

- ---12.2880 18.4320 24.5760 36.8640 49.1520 -

- - 8.1920 12.2880 - - 32.7680 49.1520 - -

- - 11.2896 16.9344 22.5792 33.8680 - - - -

- - 12.2880 18.4320 24.5760 36.8640 - - - -

8.1920 12.2880 - - 32.7680 49.1520 - - - -

11.2896 16.9344 22.5792 33.8680 - - - - - -

12.2880 18.4320 24.5760 36.8640 - - - - - -

Table 1. Common Clock Frequencies

4.2 Serial Clock

The serial clock controls the shifting of data into the input data buffers. The CS4344 family supports both
external and internal serial clock generation modes. Refer to Figures 7–9 for data formats.

4.2.1 External Serial Clock Mode

The CS4344 family will enter the External Serial Clock Mode when 16 low to high transitions are detected
on the DEM
rial Clock Mode and deemphasis filter cannot be accessed. The CS4344 family will switch to Internal Se­rial Clock Mode if no low to high transitions are detected on the DEM
of LRCK. Refer to Figure 11.

/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Se-

4.2.2 Internal Serial Clock Mode

In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and
LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation
in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode al­lows access to the digital deemphasis function. Refer to Figures 7–11 for details.

12

/SCLK pin for 2 consecutive frames

LRCK

SCLK

Left Channel

Right Channel

SDATA +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4 -5

+3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4

Internal SCLK Mode External SCLK Mode

I²S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
I²S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
I²S, Up to 24-Bit data and INT SCLK = 72 Fs if
MCLK/LRCK = 1152

I²S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK

LRCK

SCLK

Left Channel

Right Channel

SDATA +3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4 -5

+3 +2 +1

LSB

+5 +4

MSB

-1 -2 -3 -4

Internal SCLK Mode External SCLK Mode

Left-Justified, up to 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152

Left-Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK

CS4344/5/8

Figure 7. CS4344 Data Format (I2S)

Figure 8. CS4345 Data Format (Left Justified)

13

CS4344/5/8

LRCK

SCLK

Left Channel

Right Channel

SDATA

6543210987

15 14 13 12 11 10

6543210987

15 14 13 12 11 10

32 clocks

Internal SCLK Mode External SCLK Mode

Right Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152

Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period

Figure 9. CS4348 Data Format (Right Justified 16)

14

4.3 De-Emphasis

Gain

dB

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kHz 10.61 kHz

The CS4344 family includes on-chip digital deemphasis. Figure 10 shows the deemphasis curve for Fs
equal to 44.1 kHz. The frequency response of the deemphasis curve will scale proportionally with changes
in sample rate, Fs.

CS4344/5/8

The deemphasis filter is active (inactive) if the DEM

/SCLK pin is low (high) for 5 consecutive falling edges

of LRCK. This function is available only in the internal serial clock mode

.

Figure 10. De-Emphasis Curve (Fs = 44.1kHz)

4.4 Initialization and Power-Down

The Initialization and Power-down sequence flow chart is shown in Figure 11. The CS4344 family enters the
Power-Down State upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the
internal voltage reference, multi-bit digital-to-analog converters and switched-capacitor low-pass filters are pow­ered down. The device will remain in the Power-down mode until MCLK and LRCK are present. Once MCLK and
LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK fre­quency ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters
and switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, VQ.

4.5 Output Transient Control

The CS4344 family uses Popguard ® technology to minimize the effects of output transients during power­up and power-down. This technique eliminates the audio transients commonly produced by single-ended
single-supply converters when it is implemented with external DC-blocking capacitors connected in series
with the audio outputs. To make best use of this feature, it is necessary to understand its operation.

4.5.1 Power-Up

When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to VQ which
is initially low. After MCLK is applied, the outputs begin to ramp with VQ towards the nominal quiescent
voltage. This ramp takes approximately 250 ms with a 3.3 µF cap connected to VQ (420 ms with a 10 µF
connected to VQ) to complete. The gradual voltage ramping allows time for the external DC-blocking ca­pacitors to charge to VQ, effectively blocking the quiescent DC voltage. Once valid LRCK and SDIN are
supplied (and SCLK if used) approximately 2000 sample periods later audio output begins.

4.5.2 Power-Down

To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn­ing off the power. To accomplish this, MCLK should be stopped for a period of about 250 ms for a 3.3 µF
cap connected to VQ (420 ms for a 10 µF cap connected to VQ) before removing power. During this time
voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this time
period has passed a transient will occur when the VA supply drops below that of VQ. There is no minimum
time for a power cycle; power may be re-applied at any time.

15

CS4344/5/8

USER: Apply Power

Wait State

USER: Apply LRCK

MCLK/LRCK Ratio Detection

USER: Applied SCLK

USER: Remove

LRCK

USER: change

MCLK/LRCK ratio

SCLK mode = internal

SCLK mode = external

Normal Operation

De-emphasis

available

Analog Output

is Generated

Normal Operation

De-emphasis

not available

Analog Output

is Generated

USER: change

MCLK/LRCK ratio

USER: Remove

MCLK

USER: Remove

LRCK

USER: Remove

MCLK

USER: Apply MCLK

Power-Down State

VQ and outputs low

VQ and outputs

ramp down

VQ and outputs

ramp down

VQ and outputs ramp up

USER: No SCLK

When changing clock ratio or sample rate, it is recommended that zero data (or near zero data) be present on
SDIN for at least 10 LRCK samples before the change is made. During the clocking change, the DAC outputs will
always be in a zero data state. If no zero audio is present at the time of switching, a slight click or pop may be
heard as the DAC output automatically goes to its zero data state.

16

Figure 11. CS4344/5/8 Initialization and Power-down Sequence

4.6 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS4344 family requires careful attention to power supply and
grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement
with VA connected to a clean +3.3 V or +5 V supply. For best performance, decoupling and filter capacitors
should be located as close to the device package as possible with the smallest capacitors closest.

4.7 Analog Output and Filtering

The analog filter present in the CS4344 family is a switched-capacitor filter followed by a continuous time
low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 12 - 19. The
recommended external analog circuitry is shown in the “Typical Connection Diagram” on page 11.

CS4344/5/8

17

5. FILTER PLOTS

Figure 12. Single-Speed Stopband Rejection Figure 13. Single-Speed Transition Band

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

-0.25

-0. 2

-0.15

-0. 1

-0.05

0

0.05

Frequency (normalized to Fs)

Amplitude dB

Figure 14. Single-Speed Transition Band Figure 15. Single-Speed Passband Ripple

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

5

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

Frequency (normalized to Fs)

Amplitude dB

CS4344/5/8

18

CS4344/5/8

Figure 16. Double-Speed Stopband Rejection Figure 17. Double-Speed Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

- 10

- 9

- 8

- 7

- 6

- 5

- 4

- 3

- 2

- 1

0

1

Frequency (normalized to Fs)

Amplitude dB

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

-0. 2

-0. 1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Frequency (normalized to Fs)

Amplitude dB

Figure 18. Double-Speed Transition Band Figure 19. Double-Speed Passband Ripple

19

CS4344/5/8

Figure 20. Quad-Speed Stopband Rejection Figure 21. Quad-Speed Transition Band

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

-1. 5

-1

-0. 5

0

Frequency (normalized to Fs)

Amplitude dB

Figure 22. Quad-Speed Transition Band Figure 23. Quad-Speed Passband Ripple

0

-10

-20

-30

-40

-50

Amplitude (dB)

-60

-70

-80

-90

-100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

-5

-10

-15

-20

-25

Amplitude (dB)

-30

-35

-40

-45

-50

0.4 0.45 0.5 0.55 0.6 0.65 0.7

Frequency(normalized to Fs)

Frequency(normalized to Fs)

0

-10

-20

-30

Amplitude (dB)

-40

-50

-60

0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75
Frequency(normalized to Fs)

20

6. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measure­ment to full scale. This technique ensures that the distortion components are below the noise level and
do not affect the measurement. This measurement technique has been accepted by the Audio Engineer­ing Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

CS4344/5/8

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

21

7. PACKAGE DIMENSIONS

10LD TSSOP (3 mm BODY) PACKAGE DRAWING

E

N

1

23

e

b

A1

A2

A

D

SEATING

PLANE

E1

1

L

SIDE VIEW

END VIEW

TOP VIEW



L1

c

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.0433 -- -- 1.10
A1 0 -- 0.0059 0 -- 0.15
A2 0.0295 -- 0.0374 0.75 -- 0.95

b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5

c 0.0031 -- 0.0091 0.08 -- 0.23

D -- 0.1181 BSC -- -- 3.00 BSC -- 2

E -- 0.1929 BSC -- -- 4.90 BSC -­E1 -- 0.1181 BSC -- -- 3.00 BSC -- 3

e -- 0.0197 BSC -- -- 0.50 BSC --

L 0.0157 0.0236 0.0315 0.40 0.60 0.80

L1 -- 0.0374 REF -- -- 0.95 REF --



0° -- 8° 0° -- 8°

CS4344/5/8

Notes:

22

Controlling Dimension is Millimeters

1. Reference document: JEDEC MO-187

2. D does not include mold flash or protrusions which is 0.15 mm max. per side.

3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side.

4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.

5. Exceptions to JEDEC dimension.

CS4344/5/8

8. ORDERING INFORMATION

Product Description Package Pb-Free Grade Temp Range Container Order #

CS4344

CS4345

CS4348 Commercial -10 to +70 °C CS4348-CZZ

24-Bit, 192 kHz

Stereo D/A

Converter

10-TSSOP Yes

Commercial -10 to +70 °C

Automotive -40 to +85 °C CS4344-DZZ

Commercial -10 to +70 °C CS4345-CZZ

Automotive -40 to +85 °C CS4345-DZZ

Tube

or

Tape and Reel

8.1 Functional Compatibility

CS4334-KS  CS4344-CZZ

CS4344-CZZ

CS4335-KS

CS4338-KS

CS4334-BS

CS4334-DS

 CS4345-CZZ

 CS4348-CZZ

 CS4344-DZZ

 CS4344-DZZ

8.2 Selection Guide

The CS4344 family differs by Serial Audio format as follows:

• CS4344 — 16- to 24-bit, I²S

• CS4345 — 16- to 24-bit, Left-Justified

• CS4348 — 16-bit, Right-Justified

23

9. REVISION HISTORY

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to

www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con­sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP­ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE­VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA­TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.

Release Changes

-Updated passband and frequency response specifications in “Combined Interpolation & On-chip Analog Filter

Response” on page 7

F1

-Updated PSRR specification

-Updated VIH specification

-Updated figures in “Filter Plots” on page 18

-Removed references to CS4346 throughout.

-Updated Footnote 1 about dither in “DAC Analog Characteristics” on page 6.

F2

-Updated the “SCLK rising to LRCK edge” unit froms to ns in “Switching Characteristics - Serial Audio Interface”

on page 9.

CS4344/5/8

24