CIRRUS LOGIC CS42L51 Service Manual

CS42L51

Low Power, Stereo CODEC with Headphone Amp

DIGITAL to ANALOG FEATURES

! 98 dB Dynamic Range (A-wtd) ! -86 dB THD+N ! Headphone Amplifier - GND Centered

– On-Chip Charge Pump Provides -VA_HP – No DC-Blocking Capacitor Required – 46 mW Power Into Stereo 16 Ω @ 1.8 V – 88 mW Power Into Stereo 16 Ω @ 2.5 V – -75 dB THD+N

! Digital Signal Processing Engine

– Bass & Treble Tone Control, De-Emphasis – PCM + ADC Mix w/Independent Vol Control – Master Digital Volume Control – Soft Ramp & Zero Cross Transitions

! Beep Generator

– Tone Selections Across Two Octaves – Separate Volume Control – Programmable On & Off Time Intervals – Continuous, Periodic or One-Shot Beep

Selections

! Programmable Peak-Detect and Limiter ! Pop and Click Suppression

ANALOG to DIGITAL FEATURES

! 98 dB Dynamic Range (A-wtd) ! -88 dB THD+N ! Analog Gain Controls

– +32 dB or +16 dB MIC Pre-Amplifiers – Analog Programmable Gain Amplifier

(PGA)

! +20 dB Digital Boost ! Programmable Automatic Level Control (ALC)

– Noise Gate for Noise Suppression – Programmable Threshold and

Attack/Release Rates

! Independent Channel Control ! Digital Volume Control ! High-Pass Filter Disable for DC Measurements ! Stereo 3:1 Analog Input MUX ! Dual MIC Inputs

– Programmable, Low Noise MIC Bias Levels – Differential MIC Mix for Common Mode

Noise Rejection

! Very Low 64 Fs Oversampling Clock Reduces

Power Consumption

Serial Audio

Input

Hardware

Mode or I

SPI Software

Mode

Control Data

Reset

Serial Audio

Output

1.8 V to 3.3 V

C &

Level Translator

1.8 V to 2.5 V 1.8 V to 2.5 V

Beep

Generator

PCM Serial Interface

Configuration

Advance Product Information

http://www.cirrus.com

High Pass

Filters

1.8 V to 2.5 V

Digital Signal

Processing

Engine

ALC

Volume

Controls

MUX

Multibit

∆Σ Modulator

Multibit

Oversampling

ADC

Multibit

Oversampling

ADC

Switched

Capacitor DAC

and Filter

Switched

Capacitor DAC

and Filter

MUX

PGA

MUX

PGA

Headphone Amp - GND

MUX

Centered

Charge

Pump

+32 dB

MIC Bias

Left HP Out

Right HP Out

Stereo Input 1 Stereo Input 2

Stereo Input 3 / Mic Input 1 & 2

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

SEPTEMBER '05

DS679A2

CS42L51

SYSTEM FEATURES

! 24-bit Converters ! 4 kHz to 96 kHz Sample Rate ! Multi-bit Delta Sigma Architecture ! Low Power Operation

– Stereo Playback: 12.93 mW @ 1.8 V – Stereo Record and Playback: 20.18 mW @

1.8 V

! Variable Power Supplies

– 1.8 V to 2.5 V Digital & Analog – 1.8 V to 3.3 V Interface Logic

! Power Down Management

– ADC, DAC, CODEC, MIC Pre-Amplifier,

PGA

! Software Mode (I²C & SPI™ Control) ! Hardware Mode (Stand-Alone Control) ! Digital Routing/Mixes:

– Analog Out = ADC + Digital In – Digital Out = ADC + Digital In – Internal Digital Loopback – Mono Mixes

! Flexible Clocking Options

– Master or Slave Operation – High-Impedance Digital Output Option (for

easy MUXing between CODEC and Other Data Sources)

– Quarter-Speed Mode - (i.e. Allows 8 kHz Fs

while maintaining a flat noise floor up to 16 kHz)

APPLICATIONS

! HDD & Flash-Based Portable Audio Players ! MD Players/Recorders

GENERAL DESCRIPTION

The CS42L51 is a highly integrated, 24-bit, 96 kHz, low power stereo CODEC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. Both the ADC and DAC offer many features suitable for low power, portable system applications.

The ADC input path allows independent channel control of a number of features. An input multiplexer selects between line-level or microphone level inputs for each channel. The microphone input path includes a selectable programmable-gain pre-a mplifier stage and a low noise MIC bias voltage supply. A PGA is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also features a digital volume attenuator with soft ramp transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels appropriately.

The DAC output path includes a digital signal pro cessing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Mixer allows independent volume control for both the ADC mix and the PCM mix, as well as a master digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp and zero cross transitions. The DAC also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves.

The stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump provides a negative supply. This allows a gr ound-centered analog output with a wide signal swing and eliminates external DC-blocking capacitors.

In addition to its many features, the CS42L51 operates from a low-voltage analog and digital core, making this CODEC ideal for portable systems that require extremely low power consumption in a minimal amount of space.

! PDAs ! Personal Media Players ! Portable Game Consoles ! Digital Voice Recorders ! Digital Camcorders ! Digital Cameras ! Smart Phones

2 DS679A2

The CS42L51 is available in a 32-pin QFN package in both Commercial (-10 to +70° C) and Automotive grades (-40 to +85° C). The CDB42L51 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see “Ordering

Information” on page 81 for complete details.

TABLE OF CONTENTS

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................... 7

1.1 Digital I/O Pin Characteristics ....................... ... ... .... ... ... .....................................................9

2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 10

3. CHARACTERISTIC AND SPECIFICATION TABLES ........................................................... 12

SPECIFIED OPERATING CONDITIONS............................................................................... 12

ABSOLUTE MAXIMUM RATINGS.........................................................................................12

ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)............................................ 13

ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ............................................ 14

ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 15

ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)........................................ 16

ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ........................................ 17

LINE OUTPUT VOLTAGE CHARACTERISTICS................................................................... 18

HEADPHONE OUTPUT POWER CHARACTERISTICS........................................................ 19

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 20

SWITCHING SPECIFICATIONS - SERIAL PORT.................................................................20

SWITCHING SPECIFICATIONS - I²C CONTROL PORT.......................................................22

SWITCHING CHARACTERISTICS - SPI CONTROL PORT..................................................23

DC ELECTRICAL CHARACTERISTICS .......... ... ... ... .... ...................................................... ... 24

DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS....................................... 24

POWER CONSUMPTION......................................................................................................25

4. APPLICATIONS ..................................................................................................................... 26

4.1 Overview ... ... .... ... ... ... .... ................................................................................................... 26

4.1.1 Architecture ......................................... ... .... ... ... ................................................... 26

4.1.2 Line & MIC Inputs ..................... .... ... ....................................................... ... ... ......26

4.1.3 Line & Headphone Outputs ........................ ... ... ... .... ... ... ... ... ................................ 26

4.1.4 Signal Processing Engine ................... ... .... ... ... ... .... ... ......................................... 26

4.1.5 Beep Generator ..................... ... .... ... ... ... .... ... ... ... ................................................ 26

4.1.6 Device Control (Hardware or Software Mode) .................................................... 26

4.1.7 Power Management ............................................ .... ... ... ... ... .... ............................ 26

4.2 Hardware Mode .. ....................................................... ... ... .... ... ... ...................................... 27

4.3 Analog Inputs ............................................................... ... .... ............................................ 28

4.3.1 Digital Code, Offset & DC Measurement ............................................................ 28

4.3.2 High-Pass Filter and DC Offset Calibration ........................................................ 29

4.3.3 Digital Routing ..................... ... ....................................................... ... ................... 29

4.3.4 Differential Inputs ................ ... ....................................................... ... .... ... ... ... ......29

4.3.4.1 External Passive Components ............. ............. ............. ................ ......... 29

4.3.5 Analog Input Multiplexer ..................................................................................... 30

4.3.6 MIC & PGA Gain .............................................. ... .... ............................................ 31

4.3.7 Automatic Level Control (ALC) ........................................................................... 31

4.3.8 Noise Gate .......... ... ... .... ... ... ... ... .......................................................................... 32

4.4 Analog Outputs .......................... ... ... ... ....................................................... ... .... ............... 33

4.4.1 De-Emphasis Filter ................ ... .... ... ... ... ....................................................... ... ... 33

4.4.2 Volume Controls ................. ... ... ....................................................... .... ... ............ 34

4.4.3 Mono Channel Mixer ...........................................................................................34

4.4.4 Beep Generator ..................... ... .... ... ... ... .... ... ... ... ................................................ 34

4.4.5 Tone Control ................................................. ... ... .... ... ... ...................................... 35

4.4.6 Limiter ................................................. ... .... .........................................................35

4.4.7 Line-Level Outputs and Filtering .........................................................................36

4.4.8 On-Chip Charge Pump ................. ... ... ... ....................................................... ... ... 36

4.5 Serial Port Clocking ............................................................. ... ... ... ... ................................ 37

4.5.1 Slave ......... ... .... ... ... ... .................................................... ... ... .... ... ... ...................... 37

4.5.2 Master ................................................................................................................. 38

CS42L51

DS679A2 3

CS42L51

4.5.3 High-Impedance Digital Output ........................................................................... 38

4.5.4 Quarter- and Half-Speed Mode ..................................... ... ... .... ... ... ... .... ... ... ... ... ... 39

4.6 Digital Interface Formats ................................................................................................. 39

4.7 Initialization ...................................................................................................................... 40

4.8 Recommended Power-Up Sequence .............................................................................. 40

4.9 Recommended Power-Down Sequence ......................................................................... 41

4.10 Software Mode ........... ... ... ... .... ... ... ... ....................................................... ... .... ... ... ... ... ... 42

4.10.1 SPI Control ........................... ... .... ... ... ... .... ... ... ... .... ... ......................................... 42

4.10.2 I²C Control ............................ ... .... ... ... ... .... ... ... ................................................... 42

4.10.3 Memory Address Pointer (MAP) ....................................................................... 44

4.10.3.1 Map Increment (INCR) ..........................................................................44

5. REGISTER QUICK REFERENCE ............. .......................................................... .... ... ... ... ... ... 45

6. REGISTER DESCRIPTION ................................................. ... .... ... ... ... ... ................................ 47

6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ............... ... ... ... .... ... ............ 47

6.2 Power Control 1 (Address 02h) ................................................. ... ... .... ... ... ... .... ... ... ... ... ... 47

6.3 MIC Power Control & Speed Control (Address 03h) ...................................................... 48

6.4 Interface Control (Address 04h) ...................................................................................... 49

6.5 MIC Control (Address 05h) .............................................................................................. 51

6.6 ADC Control (Address 06h) ............................................................................................. 52

6.7 ADCx Input Select, Invert & Mute (Address 07h) ............................................................ 53

6.8 DAC Output Control (Address 08h) ................................................................................. 54

6.9 DAC Control (Address 09h) ............................................................................................. 55

6.10 ALCX & PGAX Control:

ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ..................................... 56

6.11 ADCx Attenuator:

ADCA (Address 0Ch) & ADCB (Address 0Dh) ............................................................ 57

6.12 ADCx Mixer Volume Control:

ADCA (Address 0Eh) & ADCB (Address 0Fh) ....................... ...................................... 58

6.13 PCMX Mixer Volume Control:

PCMA (Address 10h) & PCMB (Address 11h) .................... ................ ................ ......... 59

6.14 Beep Frequency & Timing Configuration (Address 12h) ............................................... 60

6.15 Beep Off Time & Volume (Address 13h) ....................................................................... 61

6.16 Beep Configuration & Tone Configuration (Address 14h) ............................................. 62

6.17 Tone Control (Address 15h) .............................................. ... ... ... ... .... ... ... ... .... ... ... ... ... ... 63

6.18 AOUTx Volume Control:

AOUTA (Address 16h) & AOUTB (Address 17h) ......................................................... 64

6.20 Limiter Threshold SZC Disable (Address 19h) .............................................................. 65

6.21 Limiter Release Rate Register (Address 1Ah) ...................................... ......................... 66

6.22 Limiter Attack Rate Register (Address 1Bh) ......................................... ......................... 67

6.23 ALC Enable & Attack Rate (Address 1Ch) .................................................................... 67

6.24 ALC Release Rate (Address 1Dh) ................................................................................. 68

6.25 ALC Threshold (Address 1Eh) ....................................................................................... 69

6.26 Noise Gate Configuration & Misc. (Address 1Fh) .................... ................................ ...... 70

6.27 Status (Address 20h) (Read Only) ............. ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ... 71

6.28 Charge Pump Frequency (Address 21h) ....................................................................... 71

7. ANALOG PERFORMANCE PLOTS ...................................................................................... 72

7.1 Headphone THD+N versus Output Power Plots ............................................................. 72

7.2 ADC_FILT+ Capacitor Effects on THD+N ....................................................................... 74

8. EXAMPLE SYSTEM CLOCK FREQUENCIES ...................................................................... 75

8.1 Auto Detect Enabled ........................................................................................................75

8.2 Auto Detect Disabled .......................................................................................................76

9. PCB LAYOUT CONSIDERATIONS .............................................. ... ... ... .... ... ... ... .... ... ... ... ... ... 77

9.1 Power Supply, Grounding ................................................................................................ 77

9.2 QFN Thermal Pad ........................................................................................................... 77

4 DS679A2

CS42L51

10. ADC & DAC DIGITAL FILTERS .......................................................................................... 78

11. PARAMETER DEFINITIONS ................................................................................................ 79

12. PACKAGE DIMENSIONS ................................................................................................... 80

THERMAL CHARACTERISTICS............................................................................................ 80

13. ORDERING INFORMATION ............................................................................................... 81

14. REFERENCES ................................................................................ ... ... .... ... ... ...................... 81

15. REVISION HISTORY ........................................................................................................... 82

DS679A2 5

LIST OF FIGURES

Figure 1. Typical Connection Diagram (Software Mode).......................................................................... 10

Figure 2. Typical Connection Diagram (Hardware Mode)......................................................................... 11

Figure 3. Headphone Output Test Load.................................................................................................... 19

Figure 4. Serial Audio Interface Slave Mode Timing.................................................. .... ... ... ... ... .... ... ... ..... 21

Figure 5. TDM Serial Audio Interface Timing............................................................................................ 21

Figure 6. Serial Audio Interface Master Mode Timing............................................................................... 21

Figure 7. Control Port Timing - I²C............................................................................................................ 22

Figure 8. Control Port Timing - SPI Format............................................................................................... 23

Figure 9. Analog Input Architecture............................ ... ... .... ... ... ... ............................................................ 28

Figure 10. MIC Input Mix w/Common Mode Rejection.............................................................................. 30

Figure 11. Differential Input....................................................................................................................... 30

Figure 12. ALC................. ... ... .... ... ... ... ....................................................... ... .... ........................................ 31

Figure 13. Noise Gate Attenuation............................................. ... .... ........................................................ 32

Figure 14. Output Architecture.................................................................................................................. 33

Figure 15. De-Emphasis Curve................................................................................................................. 33

Figure 16. Beep Configuration Options............................................. ... ... ... ... .... ... ... ... .... ... ... ... ... .... ........... 34

Figure 17. Peak Detect & Limiter .............................................................................................................. 35

Figure 18. Master Mode Timing................................................................................................................ 38

Figure 19. Tri-State Serial Port ................................................................................................................. 38

Figure 20. I²S Format.................... ... ... .... ... ... ... ... .... ....................................................... ... ........................ 39

Figure 21. Left-Justified Format................................................................................................................ 39

Figure 22. Right-Justified Format (DAC only) ........................................................................................... 39

Figure 23. Initialization Flow Chart............................................................................................................ 41

Figure 24. Control Port Timing in SPI Mode ........................ ... ... ... .... ... ... ... ... .... ........................................ 42

Figure 25. Control Port Timing, I²C Write................................................... ... .... ... ... ... .... ... ... ... ... ............... 43

Figure 26. Control Port Timing, I²C Read............................. ... ... ... .... ... ... ... ... .... ... ... .................................. 43

Figure 27. AIN & PGA Selection ............................................................................................................... 53

Figure 28. THD+N vs. Ouput Power per Channel at 1.8 V (16 Ω load) .................................................... 72

Figure 29. THD+N vs. Ouput Power per Channel at 2.5 V (16 Ω load) .................................................... 72

Figure 30. THD+N vs. Ouput Power per Channel at 1.8 V (32 Ω load) .................................................... 73

Figure 31. THD+N vs. Ouput Power per Channel at 2.5 V (32 Ω load) .................................................... 73

Figure 32. ADC THD+N vs. Frequency w/Capacitor Effects..................................................................... 74

Figure 33. ADC Passband Ripple ............................................................................................................. 78

Figure 34. ADC Stopband Rejection......................................................................................................... 78

Figure 35. DAC Passband Ripple ............................................................................................................. 78

Figure 36. DAC Stopband......................................................................................................................... 78

Figure 35. DAC Transition Band ............................................................................................................... 78

Figure 36. DAC Transition Band (Detail)................................................................................................... 78

Figure 35. ADC Transition Band ............................................................................................................... 78

Figure 36. ADC Transition Band (Detail)................................................................................................... 78

CS42L51

6 DS679A2

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE

)

CS42L51

RESET

262728

AIN1B

AIN1A

AFILTB

AFILTA

AIN2B/BIAS AIN2A

MICIN2/BIAS/AIN3B

MICIN1/AIN3A

ADC_FILT+

LRCK

SDA/CDIN (MCLKDIV2)

SCL/CCLK (I²S/LJ

AD0/CS

(DEM) VA_HP

FLYP

GNDHP

FLYN

SDIN

SCLK

MCLK

SDOUT (M/S

303132

)

CS42L51

109

AOUTA

AOUTB

VSS_HP

DGND

13 14 15 16

AGND

DAC_FILT+

Pin Name # Pin Description

LRCK 1 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

SDA/CDIN 2 Serial Control Data (Input/Output) - SDA is a data I/O in I²C mode. CDIN is the input data line for the

control port interface in SPI mode. (MCLKDIV2) MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. SCL/CCLK 3 Serial Control Port Clock (Input) - Serial clock for the serial control port. (I²S/LJ

) Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-

mats for the ADC & DAC. AD0/CS

(DEM) De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter. VA_HP 5 Analog Power For Headphone (Input) - Positive power for the internal analog headphone section. FLYP 6 Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor. GNDHP 7 Analog Ground (Input) - Ground reference for the internal headphone/charge pump section. FLYN 8 Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor. VSS_HP 9 Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-

AOUTB AOUTA

VA 12 Analog Power (Input) - Positive power for the internal analog section. AGND 13 Analog Ground (Input) - Ground reference for the internal analog section.

4 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS

is the chip select signal for SPI format.

phone section.

1011Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris-

tics specification table.

DS679A2 7

CS42L51

DAC_FILT+ ADC_FILT+1416

VQ 15 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. MICIN1/

AIN3A MICIN2/

BIAS/AIN3B

AIN2A 19 Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification

AIN2B/BIAS 20 Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specifi-

AFILTA AFILTB

AIN1A AIN1B

RESET VL 26 Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and

VD 27 Digital Power (Input) - Positive power for the internal digital section. DGND 28 Digital Ground (Input) - Ground reference for the internal digital section. SDOUT 29 Serial Audio Data Output (Output) - Output for two’s complement serial audio data. (M/S

) Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between master and

MCLK 30 Master Clock (Input) -Clock source for the delta-sigma modulators. SCLK 31 Serial Clock (Input/Output) - Serial clock for the serial audio interface. SDIN 32 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Thermal Pad - Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 77.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

17 Microp hone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specifi-

cation table.

18 Microp hone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics

specification table. This pin can also be configured as an output to provide a low noise bias supply for an

external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.

table.

cation table. This pin can also be configured as an output to provide a low noise bias supply for an exter-

nal microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.

2122Filter Connection (Output) - Filter connection for the ADC inputs.

2324Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification

table.

25 Reset (Input) - The device enters a low power mode when this pin is driven low.

host control port. Refer to the Recommended Operating Conditions for appropriate voltages.

slave mode for the serial port.

8 DS679A2

CS42L51

1.1 Digital I/O Pin Characteristics

The logic level for each input should adhere to the corr esponding power rail and should not exceed the maximum ratings.

Power

Rail

Pin Name

SW/(HW)

RESET Input

SCL/CCLK

(I²S/LJ)

SDA/CDIN

(MCLKDIV2)

AD0/CS

(DEM) MCLK Input

LRCK Input/Output SCLK Input/Output

SDOUT

(M/S) SDIN Input

Input/Output

I/O Driver Receiver

- 1.8 V - 3.3 V

Input

- 1.8 V - 3.3 V, with Hysteresis

1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis

Input

- 1.8 V - 3.3 V

1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V

- 1.8 V - 3.3 V

Table 1. I/O Power Rails

DS679A2 9

2. TYPICAL CONNECTION DIAGRAMS

+1.8 V o r +2.5 V

* *Use low ESR ceramic capacitors.

Note 2 :

For best response to Fs/2 :

This circuitry is intended fo r applications where the CS42L51 connects directly to an unbalanced output of the device. For internal routing applications please see the DAC Analog Output Cha racteristics section for loading limitations.

Note 5 :

Larger capacitors, such as 1.5 µF, improves the charge pump performance (and subsequent THD+N) at the full scale output power achieved with gain (G) settings greater than default.

470×+

ext

()

RFs

ext

1.5 µF

See Note 5

1.5 µF

4704

1 µF

Digital Audio

Processor

2 k

Ω

+1.8 V, +2.5 V

See Note 1

or +3.3 V

Note 1: Resistors are required for I²C control port operation

Ω

0.1 µF

FLYP FLYN VSS_HP

GND_HP

CS42L51

MCLK SCLK LRCK SDIN SDOUT RESET SCL/CCLK SDA/CDIN AD0/CS

DGND

0.1 µF

AIN3B/MICIN2

ADC_FILT+ DAC_FILT+

VA_HP

AOUTB

AOUTA

AIN1A

AIN1B

AIN2A

AIN2B

BIAS1

MICIN1

AIN3A

BIAS2

AGND

AFILTA AFILTB

0.1 µF

1800 pF

* Capacitors must be C0G or equivalent

0.022 µF

51.1 Ω

1 µF

0.1 µF

1000 pF

1 µF

See Note 4

+1.8 V or +2.5 V

Note 4: Series resistance in the path of the power supplies must be avoided. Any voltage drop on VA_HP will dir ectly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output .

Headphone Out Left & Right

470

Ω

Line Level Out Left & Right

See Note 2

470

Ω

Speaker Driver

Left Analog Input 1

100 Ω

100 kΩ

100 Ω

100 kΩ

Note 3: The value of RL is dictated by the microphone cartridge.

1 µF

1000 pF

Right Analog Input 1

Left Analog Input 2

100 kΩ

Right Analog Input 2

Microphone Input

Microphone Bias

See Note 3

10 µF

1 µF

CS42L51

ext

Figure 1. Typical Connection Diagram (Software Mode)

10 DS679A2

CS42L51

+1.8V or +2.5V

* *Use low ESR ceramic capacitors.

Digital Audio

Processor

+1.8V, 2.5 V

or +3.3V

1 µF

0.1 µF

FLYP FLYN VSS_HP

GND_HP

MCLK SCLK LRCK SDIN

SDOUT/ M/S

RESET I²S/LJ MCLKDIV2

DEM

CS42L51

DGND

0.1 µF

VA_HP

AOUTB

AOUTA

AIN1A

AIN1B

0.1 µF

1800 pF

0.022 µF

51.1 Ω

See Note 4

1 µF

Note 4: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output .

470Ω

100 Ω

1 µF

100 Ω

1 µF

+1.8V or +2.5V

Line Level Out Left & Right

See Note 2

Speaker Driver

Left Analog Input 1

100 kΩ

Right Analog Input 1

Headphone Out Left & Right

ext

ADC_FILT+ DAC_FILT+

AGND

AFILTA AFILTB

1 µF

* Capacitors must be C0G or equivalent

1000 pF

10 µF

1 µF

Note 2 :

This circuitry is intended for applications where the CS 42L51 connects directly to an unbalanced output of the device . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations .

470×+

ext

For best response to Fs/2 :

()

RFs

ext

4704

Figure 2. Typical Connection Diagram (Hardware Mode)

DS679A2 11

CS42L51

3. CHARACTERISTIC AND SPECIFICATION TABLES

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and spe cif icat ion s ar e de ri ved from measurements taken at nominal supply voltages and T

= 25° C.)

SPECIFIED OPERATING CONDITIONS

(AGND=DGND=0 V, all voltages with respect to ground.)

Parameters Symbol Min Nom Max Units

DC Power Supply (Note 1) Analog Core VA 1.71

2.37

Headphone Amplifier VA_HP 1.71

2.37

Digital Core VD 1.71

2.37

Serial/Control Port Interface VL 1.71

2.37

3.14

Ambient Temperature

Commercial - CNZ

Automotive - DNZ

-10

-40

1.8

2.5

1.8

2.5

1.8

2.5

1.8

2.5

3.3

1.89

2.63

1.89

2.63

1.89

2.63

1.89

2.63

3.47

+70 +85

V V

V V V

°C °C

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog

Digital

Serial/Control Port Interface Input Current (Note 2) I Analog Input Voltage (Note 3)

Digital Input Voltage

(Note 3))

Ambient Operating Temperature Commercial - CNZ (power applied) Automotive - DNZ

Storage Temperature T

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

Notes:

1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and serial/control port interface supplies.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

VA, VA_HP

VD VL

IND

stg

-0.3

-±10mA

3.0

4.0

V V V

AGND-0.7 VA+0.7 V

-0.3 VL+ 0.4 V

-20

-50

-65 +150 °C

+85 +95

°C °C

12 DS679A2

CS42L51

ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)

(Test Conditions (unless otherwise specified): All supplies = VA = 2.5 V and 1.8 V; Input sine wave (relative to digital full-scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)

VA = 2.5V VA = 1.8V

Parameter (Note 4)

Analog In to ADC (PGA bypassed)

Dynamic Range A-weighted

unweighted9390

Total Harmonic Distortion + Noise -1 dBFS

-20 dBFS

-60 dBFS

Analog In to PGA to ADC Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted9289

PGA Setting: +12 dB A-weighted

unweighted8582 Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS

-60 dBFS PGA Setting: +12 dB -1 dBFS - -85 -79 - -83 -77 dB

Analog In to MIC Pre-Amp(+16 dB) to PGA to ADC Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS - -76 - - -74 - dB

Analog In to MIC Pre-Amp(+32 dB) to PGA to ADC Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS - -74 - - -71 - dB

Other Characteristics

DC Accuracy Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Gain Drift - ±100 - - ±100 - ppm/°

Input Interchannel Isolation - 90 - - 90 - dB DAC Isolation (Note 5) -70- -70-dB Full-scale Input Voltage (x•VA) (Note 7) 0.70•VA 0.72•VA 0.75•VA 0.70•VA 0.72•VA 0.75•VA Vpp Input Impedance (Note 6) ADC

PGA

MIC

Min Typ Max Min Typ Max Unit

18 40 50

99 96

-86

-76

-36

98 95

91 88

-88

-35

86 83

78 74

-80

-82

90 87

89 86

82 79

18 40 50

96 93

-84

-73

-33

95 92

88 85

-86

-32

83 80

75 71

-78

-80

dB dB

dB dB dB

dB dB

Ω

k kΩ kΩ

DS679A2 13

CS42L51

ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)

(Test Conditions (unless otherwise specified): All supplies = VA = 2.5 V and 1.8 V; Input sine wave (relative to fullscale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)

VA = 2.5V VA = 1.8V

Parameter (Note 4)

Analog In to ADC

Dynamic Range A-weighted

unweighted9178

Total Harmonic Distortion + Noise -1 dB

-20 dB

-60 dB

Analog In to PGA to ADC Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted9087 PGA Setting: +12 dB A-weighted

unweighted8380 Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dB

-60 dB PGA Setting: +12 dB -1 dB - -85 -77 - -83 -75 dB

Analog In to MIC Pre-Amp(+16 dB) to PGA to ADC Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dB - -76 - - -74 - dB

Analog In to MIC Pre-Amp(+32 dB) to PGA to ADC Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dB - -74 - - -71 - dB

Other Characteristics

DC Accuracy Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Gain Drift - ±100 - - ±100 - ppm/°

Input Interchannel Isolation - 90 - - 90 - dB DAC Isolation (Note 5) -70- -70-dB Full-scale Input Voltage (Note 7) 0.70•VA 0.72•VA 0.75•VA 0.70•VA 0.72•VA 0.75•VA Vpp Input Impedance (Note 6) ADC

PGA

MIC

Notes:

4. Referred to the typical full-scale voltage.

5. Measured with DAC delivering full-scale output power into 16 Ω.

Min Typ Max Min Typ Max Unit

18 40 50

99 96

-86

-76

-36

98 95

91 88

-88

-35

86 83

78 74

-78

-80

88 85

87 84

80 77

18 40 50

96 93

-84

-73

-33

95 92

88 85

-86

-32

83 80

75 71

-76

-78

dB dB

dB dB dB

dB dB

Ω

k kΩ kΩ

14 DS679A2

CS42L51

Notes:

6. Measured between AINxx and AGND.

7. Full-scale input voltage characteristics for the PGA and Microphone inputs are scaled based on the gain setting for each.

ADC DIGITAL FILTER CHARACTERISTICS

Parameter (Note 8) Min Typ Max Unit

Passband (Frequency Response) to -0.1 dB corner 0 - 0.4948 Fs Passband Ripple -0.09 - 0 dB Stopband 0.6677 - - Fs Stopband Attenuation 48.4 - - dB Total Group Delay - 2.7/Fs - s

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB Phase Deviation @ 20 Hz - 10 - Deg Passband Ripple - - 0.17 dB Filter Settling Time -10

3.7

24.2

/Fs 0 s

Hz Hz

Notes:

8. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 33 to 36 on

page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

DS679A2 15

CS42L51

ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)

(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load R

(see Figure 3), and test load R

= 16 Ω, CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.)

= 10 kΩ, CL = 10 pF for the line output

Parameter (Note 9)

Min Typ Max

VA = 2.5V

VA = 1.8V

Min Typ Max Unit

RL = 10 kΩ Dynamic Range

18 to 24-Bit A-weighted unweighted 16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

92 89

98 95

96 93

-86

-75

-35

-86

-73

-33

-80

89 86

95 92

93 90

-88

-72

-32

-88

-70

-30

-82

dB dB dB dB

dB dB dB dB dB dB

RL = 16 Ω

Dynamic Range 18 to 24-Bit A-weighted

unweighted 16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Other Characteristics for RL = 16 Ω or 10 k

Output Parameters Modulation Index (MI)

(Note 10) Analog Gain Multiplier (G)

Full-scale Output Voltage (2•G•MI•VA) (Note 10) Refer to Table “Line Output Voltage Characteristics” on

Full-scale Output Power (Note 10) Refer to Table “Headphone Output Power Characteristics” on

Interchannel Isolation (1 kHz) 16 Ω

Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB Gain Drift - ±100 - - ±100 - ppm/°

AC-Load Resistance (R Load Capacitance (C

) (Note 11) 16 - - 16 - - Ω

) (Note 11) - - 150 - - 150 pF

Ω

10 kΩ

92 89

- 0.6787

98 95 96 93

-75

-35

-75

-73

-33

0.6047

80 95

-69

- - 0.6787

page 18

89 86

page 19

95 92 93 90

-75

-72

-32

-75

-70

-30

0.6047

80 93

-69

dB dB dB dB

dB dB dB dB dB dB

Vpp

dB dB

16 DS679A2

CS42L51

ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)

(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load R

line output (see Figure 3), and test load R

= 16 Ω, CL = 10 pF (see Figure 3) for the headphone output.

HP_GAIN[2:0] = 011.)

= 10 kΩ, CL = 10 pF for the

Parameter (Note 9)

Min Typ Max

VA = 2.5V

VA = 1.8V

Min Typ Max Unit

RL = 10 kΩ Dynamic Range

18 to 24-Bit A-weighted unweighted 16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

90 87

98 95

96 93

-86

-75

-35

-86

-73

-33

-78

87 84

95 92

93 90

-88

-72

-32

-88

-70

-30

-80

dB dB dB dB

dB dB dB dB dB dB

RL = 16 Ω Dynamic Range

18 to 24-Bit A-weighted

unweighted 16-Bit A-weighted

unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Other Characteristics for RL = 16 Ω or 10 k

Output Parameters Modulation Index (MI)

(Note 10) Analog Gain Multip lier (G)

Full-scale Output Voltage (2•G•MI•VA) (Note 10) Refer to Table “Line Output Voltage Characteristics” on

Full-scale Output Power (Note 10) Refer to Table “Headphone Output Power Characteristics” on

Interchannel Isolation (1 kHz) 16 Ω

Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB Gain Drift - ±100 - - ±100 - ppm/°

AC-Load Resistance (R Load Capacitance (C

) (Note 11) 16 - - 16 - - Ω

) (Note 11) - - 150 - - 150 pF

Ω

10 kΩ

90 87

- 0.6787

98 95 96 93

-75

-35

-75

-73

-33

0.6047

80 95

-67

- - 0.6787

page 18

87 84

page 19

95 92 93 90

-75

-72

-32

-75

-70

-30

0.6047

80 93

-67

dB dB dB dB

dB dB dB dB dB dB

Vpp

dB dB

DS679A2 17

CS42L51

LINE OUTPUT VOLTAGE CHARACTERISTICS

Test conditions (unless otherwise specified): Inp ut test signal is a fu ll-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load R

= 10 kΩ, CL = 10 pF (see Figure 3).

Parameter

AOUTx Voltage Into RL = 10 k

HP_GAIN[2:0] Analog

Min Typ Max

Ω

VA_HP

VA = 2.5V

VA = 1.8V

Min Typ Max Unit

Gain (G)

000 0.3959 1.8 V - 1.34 - - 0.97 - V

2.5 V - 1.34 - - 0.97 - V

001 0.4571 1.8 V - 1.55 - - 1.12 - V

2.5 V - 1.55 - - 1.12 - V

010 0.5111 1.8 V - 1.73 - - 1.25 - V

2.5 V - 1.73 - - 1.25 - V

011 (default) 0.6047 1.8 V - 2.05 - 1.41 1.48 1.55 V

2.5 V 1.95 2.05 2.15 - 1.48 - V

100 0.7099 1.8 V - 2.41 - - 1.73 - V

2.5 V - 2.41 - - 1.73 - V

101 0.8399 1.8 V - 2.85 - 2.05 V

2.5 V - 2.85 - - 2.05 - V

110 1.0000 1.8 V - 3.39 - - 2.44 - V

2.5 V - 3.39 - - 2.44 - V

1 11 1.1430 1.8 V (See (Note 12) 2.79 V

2.5 V - 3.88 - - 2.79 - V

pp pp pp pp pp pp pp pp pp pp pp pp pp pp pp pp

18 DS679A2

CS42L51

HEADPHONE OUTPUT POWER CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load R

= 16 Ω, CL = 10 pF (see Figure 3).

Parameter

AOUTx Power Into RL = 16

HP_GAIN[2:0] Analog

Min Typ Max

Ω

VA_HP

VA = 2.5V

VA = 1.8V

Min Typ Max Unit

Gain (G)

000 0.3959 1.8 V - 14 - - 7 - mW

2.5 V - 14 - - 7 - mW

001 0.4571 1.8 V - 19 - - 10 - mW

2.5 V - 19 - - 10 - mW

010 0.5111 1.8 V - 23 - - 12 - mW

2.5 V - 23 - - 12 - mW

011 (default) 0.6047 1.8 V (Note 12) -17 -mW

2.5 V - 32 - - 17 - mW

100 0.7099 1.8 V (Note 12) -23 -mW

2.5 V - 44 - - 23 - mW

101 0.8399 1.8 V (Note 10)) See Figure 28 on

rms rms rms rms rms rms rms rms rms rms rms

page 72

2.5 V -32 -mW

110 1.0000 1.8 V (Note 10, 12) See Figures 28 and 29 on page 72 mW

2.5 V mW

111 1.1430 1.8 V mW

2.5 V mW

rms rms rms rms rms

Notes:

9. One-half LSB of triangular PDF dither is added to data.

10. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog

Gain (HP_GAIN[2:0])” on page 54. High gain settings at certain VA and VA_HP supply levels may

cause clipping when the audio signal approaches full-scale, maximum power output, as shown in

Figures 28 - 31 on page 73.

11. See Figure 3. R quired for the internal op-amp's stability and signal integrity. In this circuit topology, C

and CL reflect the recommended minimum resistance and maximum capacitance re-

will effectively

move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable.

12. VA_HP settings lower than VA reduces the headroom of the h eadphone amplifier. As a resu lt, the DAC may not achieve the full THD+N performance at full-scale output voltage and power.

AOUTx

51 Ω

0.022 µF

AGND

Figure 3. Headphone Output Test Load

DS679A2 19

CS42L51

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Parameter (Note 13))MinTypMaxUnit

Frequency Response 10 Hz to 20 kHz -0.01 - +0.08 dB Passband to -0.05 dB corner

to -3 dB corner00 StopBand 0.5465 - - Fs StopBand Attenuation (Note 14) 50 - - dB Group Delay - 9/Fs - s De-emphasis Error Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

0.4780

0.4996

+1.5/+0

+0.05/-0.25

-0.2/-0.4

Fs Fs

dB dB dB

Notes:

13. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 35 and 36 on

page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

14. Measurement Bandwidth is from Stopband to 3 Fs.

SWITCHING SPECIFICATIONS - SERIAL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C

LOAD

= 15 pF.)

Parameters Symbol Min Max Units

RESET pin Low Pulse Width (Note 15)

MCLK Frequency 1.024 38.4 MHz MCLK Duty Cycle (Note 16) 45 55 %

1-ms

Slave Mode

Input Sample Rate (LRCK) Quarter-Speed Mode

Half-Speed Mode

Single-Speed Mode

Double-Speed Mode LRCK Duty Cycle 45 55 % SCLK Frequency 1/t SCLK Duty Cycle 45 55 % LRCK Setup Time Before SCLK Rising Edge t LRCK Edge to SDOUT MSB Output Delay t SDOUT Setup Time Before SCLK Rising Edge t SDOUT Hold Time After SCLK Rising Edge t SDIN Setup Time Before SCLK Rising Edge t SDIN Hold Time After SCLK Rising Edge t

s(LK-SK)

d(MSB) s(SDO-SK) h(SK-SDO)

s(SD-SK)

4 8 4

-64•FsHz

40 - ns

-40ns 30 - ns 30 - ns 20 - ns 20 - ns

12.5 25 50

100

kHz kHz kHz kHz

20 DS679A2

CS42L51

LRCK

s(LK-SK)

SCLK

SDOUT

SDIN

d(MSB)

s(SD-SK)

MSB

h(SK-SDO)

s(SDO-SK)

MSB-1

Figure 4. Serial Audio Interface Slave Mode Timing

Parameters Symbol Min Max Units

Master Mode (Note 17)

Output Sample Rate (LRCK) All Speed Modes F

LRCK Duty Cycle 45 55 % SCLK Frequency 1/t

SCLK Duty Cycle 45 55 % SCLK Rising Edge to SDOUT Output Delay t

LRCK Edge to SDOUT MSB Output Delay t SDOUT Setup Time Before SCLK Rising Edge t SDOUT Hold Time After SCLK Rising Edge t SDIN Setup Time Before SCLK Rising Edge t SDIN Hold Time After SCLK Rising Edge t

d(MSB) s(SDO-SK) h(SK-SDO)

s(SD-SK)

-Hz

- 64•F

-s

MCLK

----------------128

-----------------

MCLK

-40ns 30 - ns 30 - ns 20 - ns 20 - ns

Notes:

15. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are se ttled.

16. See “Example System Clock Frequencies” on page 75 for typical MCLK frequencies.

17. See “Master” on page 38.

LRCK

SCLK

d(MSB)

SDOUT

s(SD-SK)

SDIN

Figure 6. Serial Audio Interface Master Mode Timing

DS679A2 21

MSB

h(SK-SDO)

s(SDO-SK)

MSB-1

SWITCHING SPECIFICATIONS - I²C CONTROL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF)

Parameter Symbol Min Max Unit

SCL Clock Frequency f

RESET Rising Edge to Start

Bus Free Time Between Transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling (Note 18) t SDA Setup time to SCL Rising t Rise Time of SCL and SDA t Fall Time SCL and SDA t Setup Time for Stop Condition t Acknowledge Delay from SCL Falling t

Notes:

18. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

scl

irs

buf

hdst

low high sust hdd sud

rc fc

susp

ack

CS42L51

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs 0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

300 1000 ns

RST

SDA

SCL

irs

Stop Start

buf

Repeated

Start

hdst

low

high

hdd

sud

sust

Figure 7. Control Port Timing - I²C

hdst

Stop

susp

22 DS679A2

SWITCHING CHARACTERISTICS - SPI CONTROL PORT

(Inputs: Logic 0 = DGN D, Lo gic 1 = VL)

Parameter Symbol Min Max Units

CCLK Clock Frequency f

RESET Rising Edge to CS Falling

Falling to CCLK Edge t CS High Time Between Transmissions t CCLK Low Time t CCLK High Time t CDIN to CCLK Rising Setup Time t CCLK Rising to DATA Hold Time (Note 19) t Rise Time of CCLK and CDIN (Note 20) t Fall Time of CCLK and CDIN (Note 20) t

Notes:

19. Data must be held for sufficient time to bridge the transition time of CCLK.

20. For f

<1 MHz.

sck

srs css csh

scl sch dsu

r2 f2

20 - ns 20 - ns

1.0 - µs 66 - ns 66 - ns 40 - ns 15 - ns

CS42L51

06.0MHz

-100ns

RST

CCLK

CDIN

srs

sch

css

scl

dsu

Figure 8. Control Port Timing - SPI Format

csh

DS679A2 23

CS42L51

DC ELECTRICAL CHARACTERISTICS

(AGND = 0 V; all voltages with respect to ground.)

Parameters Min Typ Max Units

VQ Characteristics

Nominal Voltage Output Impedance DC Current Source/Sink

DAC_FILT+ Nominal Voltage

(Note 21)

ADC_FILT+ Nominal Voltage

VSS_HP Characteristics

Nominal Voltage DC Current Source

MIC BIAS Characteristics

Nominal Voltage MICBIAS _LVL[1:0] = 00

MICBIAS_LVL[1:0] = 01 MICBIAS_LVL[1:0] = 10

MICBIAS_L VL[1:0] = 11 DC Current Source Power Supply Rejection Ratio (PSRR) 1 kHz

Power Supply Rejection Ratio (PSRR) (Note 22) 1 kHz - 60 - dB

0.5•VA 23

VA VA

-0.8•(VA_HP) -

0.8•VA

0.7•VA

0.6•VA

0.5•VA

V kΩ µA

V µA

Notes:

21. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through electrolytic de-coupling capacitors.

22. Valid with the recommended capacitor values on DAC_FILT+, ADC_FILT+ and VQ. In cr ea sin g t he capacitance will also increase the PSRR.

DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS

Parameters (Note 23) Symbol Min Max Units

Input Leakage Current I Input Capacitance -10pF

1.8 V - 3.3 V Logic High-Level Output Voltage

Low-Level Output Voltage (I High-Level Input Voltage V

Low-Level Input Voltage V

(IOH = -100 µA) V

= 100 µA) V

OH OL

IH IL

23. See “Digital I/O Pin Characteristics” on page 9 for serial and control port power rails.

-±10µA

VL - 0.2 - V

-0.2V

0.65•VL - V

- 0.35•VL V

24 DS679A2

CS42L51

POWER CONSUMPTION

See (Note 24).

Power Ctl. Registers Typical Current (mA)

02h 03h

Total

Power

Operation

(Note 25)

Off

2 Standby (Note 26) xxxxxx1xxx1.8 0 0.01 0.02 0 0.05

3 Mono Record ADC11111001111.8 0 1.85 2.03 0.03 7.05

PGA to ADC11101001111.8 0 2.35 2.03 0.03 7.95

MIC to PGA to ADC

(with Bias)

MIC to PGA to ADC

(no Bias)

4 Stereo Record ADC11110001111.8 0 2.69 2.12 0.03 8.72

PGA to ADC11000001111.8 0 3.65 2.12 0.03 10.45

MIC to PGA to ADC

(no Bias)

5 Mono Playback 10111101111.8 1.66 1.40 2.35 0.01 9.74

6 Stereo Playback 00111101111.8 2.77 2.05 2.35 0.01 12.93

7 Mono Record & Playback

PGA in (no MIC) to Mono Out

8 Phone Monitor

MIC (w/bias) in to Mono Out

9 Stereo Record & Playback

PGA in (no MIC) to Stereo Out

PDN_DACB

PDN_DACA

PDN_PGAB

PDN_PGAA

PDN_ADCB

PDN_ADCA

PDN

PDN_MICB

xxxxxxxxxx1.8 0 0 0 0 0

11101001001.8 0 3.67 2.05 0.03 10.36

11101001011.8 0 3.27 2.03 0.03 9.61

11000000011.8 0 5.48 2.11 0.03 13.73

10101001111.8 1.66 3.63 2.73 0.03 14.49

10101001001.8 1.66 4.95 2.75 0.03 16.90

00000001111.8 2.77 5.59 2.82 0.03 20.18

PDN_MICA

VA_HP VA VDVL(Note 27)

PDN_MICBIAS

2.5 0 0 0 0 0

2.5 0 0.01 0.03 0 0.10

2.5 0 2.07 3.05 0.05 12.94

2.5 0 2.58 3.08 0.05 14.29

2.5 0 3.95 3.09 0.05 17.71

2.5 0 3.52 3.08 0.05 16.62

2.5 0 2.93 3.18 0.04 15.40

2.5 0 3.91 3.17 0.04 17.84

2.5 0 5.76 3.17 0.04 22.45

2.5 2.03 1.71 3.48 0.02 18.08

2.5 3.21 2.50 3.49 0.02 23.02

2.5 2.03 4.16 4.08 0.05 25.79

2.5 2.03 5.52 4.08 0.05 29.20

2.5 3.21 6.28 4.19 0.04 34.30

(mW

rms

)

Notes:

24. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and master/slave operation.

25. RESET

26. RESET

pin 25 held LO, all clocks and data lines are held LO. pin 25 held HI, all clocks and data lines are held HI.

27. VL current will slightly increase in master mode.

DS679A2 25

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