Cirrus Logic CS4299-KQ, CS4299-JQ Datasheet

CrystalClear SoundFusion™ Audio Codec ’97

Features

l AC ’97 2.1 Compatible

l Industry Leading Mixed Signal Technology

l 20-bit Stereo Digital-to-Analog Converters

l 18-bit Stereo Analog-to-Digital Converters

l Sample Rate Converters

l Four Analog Line-level Stereo Inputs for

LINE_IN, CD, VIDEO, and AUX

l Two Analog Line-level Mono Inputs for

Modem and Internal PC Beep

l Dual Stereo Line-level Outputs for

LINE_OUT and ALT_LINE_OUT

l Dual Microphone Inputs

l High Quality Pseudo-Differential CD Input

l Extensive Power Management Support

CS4299

l Meets or Exceeds the Microsoft

Audio Performance Requirements

l S/PDIF Digital Audio Output
l CrystalClear



3D Stereo Enhancement

Description

The CS4299 is an AC ’97 2.1 compatible stereo audio
codec designed for PC multimedia systems. Using the
industry leading CrystalClear
signal technology, the CS4299 enables the design of
PC 99-compliant desktop, portable, and entertainment
PCs.

Coupling the CS4299 with a PCI audio accelerator or
core logic supporting the AC ’97 interface, implements a
cost effective, superior quality, audio solution. The
CS4299 surpasses PC 99 and AC ’97 2.1 audio quality
standards.

ORDERING INFO

CS4299-KQ 48-pin TQFP 9x9x1.4 mm
CS4299-JQ 48-pin TQFP 9x9x1.4 mm



delta-sigma and mixed



PC 99

AC-LINK AND AC’97

REGISTERS

PWR

MGT

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

AC-

LINK

AC’97

REGISTERS

S/PDIF

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

ANALOG INPUT MUX

AND OUTPUT MIXER

LINE
CD
AUX

ADC

DAC

INPUT

MUX

OUTPUT

MIXER

Σ

SRC

GAIN / MUTE CONTROLS

MIXER / MUX SELECTS

SRC

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

PCM_DATA

PCM_DATA

Copyright  Cirrus Logic, Inc. 2001

(All Rights Reserved)

18 bits

20 bits

VIDEO

MIC1

MIC2

PHONE

PC_BEEP

LINE_OUT
ALT_LINE_OUT
MONO_OUT

JUN ‘01

DS319PP5

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS .................................................................5

Analog Characteristics ........................................................................................................5

Mixer Characteristics ..........................................................................................................6

Absolute Maximum Ratings ................................................................................................6

Recommended Operating Conditions.................................................................................6

Digital Characteristics .........................................................................................................6

AC ’97 Serial Port Timing....................................................................................................7

2. GENERAL DESCRIPTION ...............................................................................................10

2.1 AC-Link ....................................................................................................................10

2.2 Control registers ......................................................................................................10

2.3 Output Mixer .............................................................................................................11

2.4 Input Mux .................................................................................................................11

2.5 Volume Control ........................................................................................................11

3. AC LINK FRAME DEFINITION .........................................................................................13

3.1 AC-Link Serial Data Output Frame ..........................................................................14

3.1.1 Serial Data Output Slot Tags (Slot 0) ...........................................................14

3.1.2 Command Address Port (Slot 1) ..................................................................15

3.1.3 Command Data Port (Slot 2) ........................................................................15

3.1.4 PCM Playback Data (Slots 3-10) .................................................................15

3.2 AC-Link Audio Input Frame ......................................................................................16

3.2.5 Serial Data Input Slot Tag Bits (Slot 0) .......................................................16

3.2.6 Status Address Port (Slot 1) .........................................................................16

3.2.7 Status Data Port (Slot 2) ..............................................................................17

3.2.8 PCM Capture Data (Slot 3-10) .....................................................................17

3.3 AC-Link Protocol Violation - Loss of SYNC ..............................................................18

4. REGISTER INTERFACE ..................................................................................................19

4.3 Reset Register (Index 00h) ......................................................................................20

4.4 Master Volume Register (Index 02h) .......................................................................20

4.5 Alternate Volume Register (Index 04h) ....................................................................21

4.6 Mono Volume Register (Index 06h) .........................................................................21

4.7 PC_BEEP Volume Register (Index 0Ah) .................................................................22

4.8 Phone Volume Register (Index 0Ch) ........................................................................22

4.9 Microphone Volume Register (Index 0Eh) ................................................................23

CS4299

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Microsoft is a registered trademark of Microsoft Corporation in the United States and/or other countries.
Intel is a registered trademark of Intel Corporation.
Crystal Clear and Sound Fusion are trademarks of Cirrus Logic.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor­mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the infor­mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without
warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or
other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets.
No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, pho­tographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user.
However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (elec­tronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a
basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors
and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list
of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2

4.10 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h) ................................. 24

4.11 Input Mux Select Register (Index 1Ah) ................................................................... 25

4.12 Record Gain Register (Index 1Ch) ......................................................................... 25

4.13 General Purpose Register (Index 20h) ................................................................... 26

4.14 3D Control Register (Index 22h) .............................................................................26

4.15 Powerdown Control/Status Register (Index 26h) ...................................................27

4.16 Extended Audio ID Register (Index 28h) ................................................................ 28

4.17 PCM Front DAC Rate Register (Index 2Ch) ........................................................ 28

4.18 PCM L/R ADC Rate Register (Index 32h) .............................................................. 28

4.19 AC Mode Control Register (Index 5Eh) .................................................................. 29

4.20 Misc. Crystal Control Register (Index 60h) ............................................................. 29

4.21 S/PDIF Control Register (Index 68h) ..................................................................... 30

4.22 Vendor ID1 Register (Index 7Ch) ........................................................................... 31

4.23 Vendor ID2 Register (Index 7Eh) ........................................................................... 31

5. POWER MANAGEMENT ................................................................................................. 32

5.1 AC ’97 Reset Modes ................................................................................................ 32

5.1.1 Cold AC ‘97 Reset ....................................................................................... 32

5.1.2 Warm AC ’97 Reset ..................................................................................... 32

5.1.3 Register AC ’97 Reset ................................................................................. 32

5.2 Powerdown Controls ................................................................................................ 33

6. ANALOG HARDWARE DESCRIPTION ......................................................................... 35

6.1 Analog Inputs ........................................................................................................... 35

6.1.4 Line-Level Inputs ........................................................................................ 35

6.1.5 CD Input ..................................................................................................... 35

6.1.6 Microphone Inputs ...................................................................................... 36

6.1.7 PC Beep Input ............................................................................................36

6.1.8 Phone Input ................................................................................................37

6.2 Analog Outputs ........................................................................................................ 37

6.2.9 Stereo Outputs ........................................................................................... 37

6.2.10 Mono Output .............................................................................................37

6.3 Miscellaneous Analog Signals .................................................................................38

6.4 Power Supplies ........................................................................................................ 38

6.5 Reference Design ....................................................................................................38

7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ............................................................ 39

8. GROUNDING AND LAYOUT .......................................................................................... 39

9. PIN DESCRIPTIONS 41

10. PARAMETER AND TERM DEFINITIONS ....................................................................46

11. REFERENCE DESIGN ................................................................................................. 48

12. REFERENCES .............................................................................................................. 49

13. PACKAGE DIMENSIONS ............................................................................................. 50

CS4299

LIST OF FIGURES

Figure 1. Power Up Timing .......................................................................................................8

Figure 2. Codec Ready from Startup or Fault Condition........................................................... 8

Figure 3. Clocks ........................................................................................................................ 8

Figure 4. Data Setup and Hold.................................................................................................. 9

Figure 5. PR4 Powerdown and Warm Reset ............................................................................ 9

Figure 6. Test Mode .................................................................................................................. 9

Figure 7. AC-link Connections ................................................................................................10

Figure 8. Mixer Diagram.......................................................................................................... 12

Figure 9. AC-link Input and Output Framing ........................................................................... 13

Figure 10. Line Input (Replicate for Video and Aux) ...............................................................35

3

Figure 11. Differential 2 VRMS CD Input ................................................................................35

Figure 12. Differential 1 VRMS CD Input ................................................................................35

Figure 13. Microphone Input ...................................................................................................36

Figure 14. Microphone Pre-amplifier .......................................................................................36

Figure 15. PC_BEEP Input......................................................................................................36

Figure 16. Modem Connection ................................................................................................37

Figure 17. Alternate Line Output as Headphone Output .........................................................37

Figure 18. Stereo Output .........................................................................................................37

Figure 19. Voltage Regulator ..................................................................................................38

Figure 20. S/PDIF Output ........................................................................................................39

Figure 21. Conceptual Layout for the CS4297A......................................................................40

Figure 22. Pin Locations for the CS4297A ..............................................................................41

Figure 23. CS4297A Reference Design ..................................................................................48

LIST OF TABLES

Table 1. Mixer Registers .........................................................................................................19

Table 2. Analog Mixer Output Attenuation ..............................................................................21

Table 3. Microphone Input Gain Values ..................................................................................23

Table 4. Analog Mixer Input Gain Values................................................................................24

Table 5. Stereo Volume Register Index ..................................................................................24

Table 6. Input Mux Selection...................................................................................................25

Table 7. Slot Mapping ............................................................................................................29

Table 8. Device ID with Corresponding Part Number .............................................................31

Table 9. Revision Values.........................................................................................................31

Table 10. Powerdown PR Bit Functions..................................................................................33

Table 11. Powerdown PR Function Matrix ..............................................................................34

Table 12. Power Consumption by Powerdown Mode .............................................................34

CS4299

4

1. CHARACTERISTICS AND SPECIFICATIONS

CS4299

ANALOG CHARACTERISTICS Standard test conditions unless otherwise noted: T

AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; Z
1000 pF load, C

= 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding for ADC

DL

ambient

=100 kΩ/

AL

= 25° C,

functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain.

CS4299-KQ CS4299-JQ

Parameter

(Note 2)

Symbol Path

(Note 3)

UnitMin Typ Max Min Typ Max

Full Scale Input Voltage
Line Inputs
Mic Inputs
Mic Inputs (20 dB internal gain)

A-D
A-D
A-D

0.91

0.91

0.091

1.00

1.00

0.10

-

0.91

-

0.91

-

0.091

1.00

1.00

0.10

-

V
V
V

RMS

RMS

RMS

-

-

Full Scale Output Voltage
Line,Alternate Line, and Mono Outputs D-A 0.91 1.0 1.13 0.91 1.0 1.13 V

Frequency Response (Note 4)
Analog Ac = ± 0.25 dB
DAC Ac = ± 0.25 dB
ADC Ac = ± 0.25 dB

Dynamic Range
Stereo Analog inputs to LINE_OUT
Mono Analog inputs to LINE_OUT
DAC Dynamic Range
ADC Dynamic Range

DAC SNR (-20 dB FS input w/
CCIR-RMS filter on output)

Total Harmonic Distortion + Noise

FR

DR

SNR

THD+N

A-A
D-A
A-D

A-A
A-A
D-A
A-D

20
20
20

90
85
85
85

95
90
90
90

-

-

-

20,000
20,000
20,000

-

-

-

-

20
20
20

-

20,000

-

20,000

-

20,000

90

­85

­87

­85

-

-

-

-

-

D-A-70---- dB

RMS

Hz
Hz
Hz

dB FS A
dB FS A
dB FS A
dB FS A

(-3 dB FS input signal):
Line/Alternate Line Output
DAC
ADC (all inputs except phone/mic)
ADC (phone/mic)

A-A
D-A
A-D
A-D

-74

-90

-

-91

-

-88

-

-84

-

-80

-80

-80

-74

-

-

-

-

-

-74

-

-74

-

-74

-

dB FS
dB FS
dB FS
dB FS

Power Supply Rejection Ratio
(1 kHz, 0.5 V

w/ 5 V DC offset)(Note 4) 40 60 - - 40 - dB

RMS

Interchannel Isolation 70 88 - - 88 - dB
Spurious Tone (Note 4) - -100 - - -100 - dB FS
Input Impedance (Note 4) 10 - - 10 - - kΩ
External Load Impedance 10 - - 10 - - kΩ
Output Impedance (Note 4) - 730 - - 730 - Ω
Input Capacitance (Note 4) - 5 - - 5 - pF
Vrefout 2.0 2.28 2.5 2.0 2.28 2.5 V

Notes: 1. Z

2. Parameter definitions are given in the Section 10, Parameter and Term Definitions.

3. Path refers to the signal path used to generate this data. These paths are defined in the Section 10,

4. This specification is guaranteed by silicon characterization, it is not production tested.

refers to the analog output pin loading and CDL refers to the digital output pin loading.

AL

Parameter and Term Definitions.

5

CS4299

MIXER CHARACTERISTICS (for CS4299-KQ only)

Parameter Min Typ Max Unit

Mixer Gain Range Span
Line In, Aux, CD, Video, Mic1, Mic2, Phone, PC Beep
Mono Out, Alternate Line Out
Line Out

Step Size
All volume controls except PC Beep
PC Beep

ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog
Total Power Dissipation (Supplies, Inputs, Outputs) - - 1.25 W
Input Current per Pin (Except Supply Pins) -10 - 10 mA
Output Current per Pin (Except Supply Pins) -15 - 15 mA
Analog Input voltage -0.3 - AVdd+

Digital Input voltage -0.3 - DVdd +

Ambient Temperature (Power Applied) -55 - 110 °C
Storage Temperature -65 - 150 °C

-

-

-

-

-

-0.3

-0.3

-0.3

46.5

46.5

94.5

1.5

3.0

-

-

-

-

-

-

-

-

6.0

6.0

6.0

0.3

0.3

dB
dB
dB

dB
dB

V
V
V

V

V

RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Symbol Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog

Operating Ambient Temperature 0 - 70 °C

DVdd1, DVdd2
DVdd1, DVdd2

AVdd1, AVdd2

3.135

4.75

4.75

3.3
5
5

3.465

5.25

5.25

V
V
V

DIGITAL CHARACTERISTICS (AVss = DVss = 0 V)

Parameter Symbol Min Typ Max Unit

Low level input voltage V
High level input voltage V
High level output voltage V
Low level output voltage V
Input Leakage Current (AC-link inputs) -10 - 10 µA
Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA
Output buffer drive current

BIT_CLK, S/PDIF_OUT
SDATA_IN, EAPD (Note 4)

il

ih

oh

ol

- -0.8V

0.65 x DVdd - - V

0.90 x DVdd 0.99 x DVdd - V

- 0.03 0.10 x DVdd V

-

-

24

-

4

-

mA
mA

6

CS4299

AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: T

AVdd = 5.0 V, DVdd = 3.3 V; C

= 55 pF load.

L

ambient

= 25° C,

Parameter Symbol Min Typ Max Unit

RESET Timing

RESET# active low pulse width T
RESET# inactive to BIT_CLK start-up delay T
1st SYNC active to CODEC READY set T
Vdd stable to Reset inactive T

rst_low

rst2clk

sync2crd

vdd2rst#

1.0 - - µs

- 40.0 - µs

- 62.5 - µs

100 - - µs

Clocks

BIT_CLK frequency F
BIT_CLK period T

clk_period

clk

- 12.288 - MHz

- 81.4 - ns
BIT_CLK output jitter (depends on XTAL_IN source) - - 750 ps
BIT_CLK high pulse width T
BIT_CLK low pulse width T
SYNC frequency F
SYNC period T
SYNC high pulse width T
SYNC low pulse width T

sync_period

sync_high

sync_low

clk_high

clk_low

sync

36 40.7 45 ns
36 40.7 45 ns

-48-kHz

- 20.8 - µs

-1.3-µs

- 19.5 - µs

Data Setup and Hold

Output Propagation delay from rising edge of BIT_CLK T
Input setup time from falling edge of BIT_CLK T
Input hold time from falling edge of BIT_CLK T
Input Signal rise time T
Input Signal fall time T
Output Signal rise time (Note 4) T
Output Signal fall time (Note 4) T

co

isetup

ihold

irise

ifall

orise

ofall

81012ns

10 - - ns

0--ns
2-6ns
2-6ns
246ns
246ns

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) T
SYNC pulse width (PR4) Warm Reset T
SYNC inactive (PR4) to BIT_CLK start-up delay T
Setup to trailing edge of RESET# (ATE test mode) (Note 4) T

s2_pdown

sync_pr4

sync2clk

setup2rst

Rising edge of RESET# to Hi-Z delay (Note 4) T

off

-.281.0µs

1.0 - - µs

162.8 285 - ns
15 - - ns

- - 25 ns

7

BIT_CLK

CS4299

RESET#

Vdd

BIT_CLK

SYNC

CODEC_READY

T

rst_low

T

vdd2rst#

Figure 1. Power Up Timing

T

sync2crd

T

rst2clk

BIT_CLK

T

orise

SYNC

T

irise

Figure 2. Codec Ready from Startup or Fault Condition

T

clk_highTclk_low

T

sync_high

T

Figure 3. Clocks

T

ifall

sync_period

T

clk_period

T

sync_low

T

ifall

8

BIT_CLK

BIT_CLK

SDATA_IN

SDATA_OUT,
SYNC

Slot 1 Slot 2

T

co

T

isetup

Figure 4. Data Setup and Hold

T

CS4299

ihold

SDATA_OUT

SDATA_IN

SYNC

Write to 0x20 Data PR4 Don’t Care

T

s2_pdown

T

Figure 5. PR4 Powerdown and Warm Reset

RESET#

T

setup2rst

SDATA_OUT,
SYNC

T

off

sync_pr4

T

sync2clk

SDATA_IN,

BIT_CLK

Hi-Z

Figure 6. Test Mode

9

CS4299

2. GENERAL DESCRIPTION

The CS4299 is a mixed-signal serial audio Codec
compliant to the Intel® Audio Codec ‘97 Specifica-
tion, revision 2.1 [1]. It is designed to be paired
with a digital controller, typically located on the
PCI bus or integrated within the system core logic
chip set. The controller is responsible for all com­munications between the CS4299 and the remain­der of the system. The CS4299 contains two
distinct functional sections: digital and analog. The
digital section includes the AC-link interface,
S/PDIF interface, serial data port, Sample Rate
Converters, and power management support. The
analog section includes the analog input multiplex­er (mux), stereo output mixer, mono output mixer,
stereo Analog-to-Digital Converters (ADCs), ste­reo Digital-to-Analog Converters (DACs), and
their associated volume controls.

2.1 AC-Link

All communication with the CS4299 is established
with a 5-wire digital interface to the controller, as
shown in Figure 7. This interface is called the
AC-link. All clocking for the serial communication
is synchronous to the BIT_CLK signal. BIT_CLK
is generated by the primary audio codec and is used
to clock the controller and any secondary audio co-

decs. Both input and output AC-link audio frames
are organized as a sequence of 256 serial bits form­ing 13 groups referred to as ‘slots’. During each au­dio frame, data is passed bi-directionally between
the CS4299 and the controller. The input frame is
driven from the CS4299 on the SDATA_IN line.
The output frame is driven from the controller on
the SDATA_OUT line. The controller is also re­sponsible for issuing reset commands via the RE­SET# signal. Following a Cold Reset, the CS4299
is responsible for notifying the controller that it is
ready for operation after synchronizing its internal
functions. The CS4299 AC-link signals must use
the same digital supply voltage as the controller
chip, either +5 V or +3.3 V. See Section 3, AC Link
Frame Definition, for detailed AC-link informa­tion.

2.2 Control registers

The CS4299 contains a set of AC ’97 compliant
control registers and a set of Cirrus Logic defined
control registers. These registers control the basic
functions and features of the CS4299. Read access­es of the control registers by the AC ’97 controller
are accomplished with the requested register index
in Slot 1 of a SDATA_OUT frame. The following
SDATA_IN frame will contain the read data in its

10

Digital AC’97

Controller

Figure 7. AC-link Connections

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

CODEC

CS4299

Slot 2. Write operations are similar, with the regis­ter index in Slot 1 and the write data in Slot 2 of a
SDATA_OUT frame. The function of each input
and output frame is detailed in Section 3, AC Link
Frame Definition. Individual register descriptions
are found in Section 4, Register Interface.

2.3 Sample Rate Converters

The Sample Rate Converters (SRCs) provide high
accuracy digital filters supporting sample frequen­cies other than 48 kHz to be captured from the

CS4299 or played from the controller. AC ’97 re­quires support for two audio rates (44.1 and
48kHz). In addition, the Intel® I/O Controller Hub
(ICHx) specification requires support for five more
audio rates (8, 11.025, 16, 22.05, and 32). The
CS4299 supports all these rate, as shown in Table 7
on page 29.

2.4 Output Mixer

The CS4299 has two output mixers, illustrated in
Figure 8. The stereo output mixer sums together
the analog inputs to the CS4299, including the
PC_BEEP and PHONE signals, according to the
settings in the volume control registers. The stereo
output mix is sent to the LINE_OUT and

ALT_LINE_OUT pins on the CS4299. The mono
output mixer generates a monophonic sum of the
left and right channels from the stereo input mixer.
The mono output mix is sent to the MONO_OUT
output pin on the CS4299.

2.5 Input Mux

The input multiplexer controls which analog input
is sent to the ADCs. The output of the input mux is
converted to stereo 18-bit digital PCM data and
sent to the controller by means of the AC-link
SDATA_IN signal.

2.6 Volume Control

The CS4299 volume registers control analog input
levels to the input mixer and analog output levels,
including the master volume level, and the alternate
volume level. The PC_BEEP volume control uses
3 dB steps with a range of 0 dB to -45 dB attenua­tion. All other analog volume controls use 1.5 dB
steps. The analog inputs have a mixing range of
+12 dB signal gain to -34.5 dB signal attenuation.
The analog output volume controls have from 0 dB
to -94.5 dB attenuation for LINE_OUT and from
0 dB to -46.5 dB attenuation for ALT_LINE_OUT
and MONO_OUT.

11

CS4299

PC_BEEP

PHONE

PCM_OUT

MIC1

MIC2

LINE

CD

VIDEO

AUX

MIC

SELECT

MAIN D/A

CONVERTERS

DAC

BOOST

VOL

VOL

VOL

VOL VOL

VOL VOL VOL

MUTE

MUTE

MUTE

MUTE

MUTE

MUTE

MUTE

MUTE

PC BEEP BYPASS

Σ Σ

INPUT MIXER

ANALOG STEREO

Σ

ANALOG STEREO

OUTPUT MIXER

STEREO TO

MONO MIXER

Σ

1/2

STEREO TO

MONO MIXER

Σ

1/2

BYPASS
BUFFER

3D

3D OUTPUT

MIXER

DAC DIRECT

MONO OUT

ADC

INPUT

MUX

MODE

SELECT

MASTER
VOLUME

VOL VOL

ALT LINE
VOLUME

MONO

VOLUME

VOL

MAIN ADC

GAIN

VOL

MUTE

MUTE

MUTE

OUTPUT
BUFFER

OUTPUT
BUFFER

OUTPUT
BUFFER

MAIN A/D

CONVERTERS

ADCMUTE

LINE OUT

ALT LINE OUT

MONO OUT

PCM_IN

12

Figure 8. Mixer Diagram

CS4299

3. AC LINK FRAME DEFINITION

The AC-link is a bidirectional serial port with data
organized into frames consisting of one 16-bit and
twelve 20-bit time-division multiplexed slots. The
first slot, called the tag slot, contains bits indicating
if the CS4299 is ready to receive data (input frame)
and which, if any, other slots contain valid data.
Slots 1 through 12 contain audio or control/status
data. Both the serial data output and input frames
are defined from the controller perspective, not
from the CS4299 perspective.

The controller synchronizes the beginning of a
frame with the assertion of the SYNC signal.

Tag Phase Data Phase

Figure 9 shows the position of each bit location

within the frame. The first bit position in a new se-

rial data frame is F0 and the last bit position in the

serial data frame is F255. When SYNC goes active

(high) and is sampled active by the CS4299 (on the

falling edge of BIT_CLK), both devices are syn-

chronized to a new serial data frame. The data on

the SDATA_OUT pin at this clock edge is the final

bit of the previous frame’s serial data. On the next

rising edge of BIT_CLK, the first bit of Slot 0 is

driven by the controller on the SDATA_OUT pin.

On the next falling edge of BIT_CLK, the CS4299

latches this data in, as the first bit of the frame.

20.8 µs

(48 kHz)

SYNC

BIT_CLK

Bit Frame Position:

SDATA_OUT

Bit Frame Position:

SDATA_IN

12.288 MHz

81.4 ns

F0 F1 F2 F16F15F14F13F12

F255

Valid

Frame

F0 F1 F2 F16F15F14F13F12 F35 F56 F76F255

Codec
Ready

Slot 1

Valid

Slot 1
Valid

GPIO

INT

0

Slot 2

Valid

Slot 2

Valid

F36 F57

Slot 12

Valid

Slot 12

Valid

Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slots 5-12

Codec

Codec

0

ID1

R/W 0 WD15

ID0

0000

F35

F36

0

F56

D19 D18

F57

D19 D18 D19RD15

F76

D19

F96

D19

F96

D19

Figure 9. AC-link Input and Output Framing

F255

F255

GPIO

0

INT

13

CS4299

3.1 AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4299 from the AC ’97
controller. Figure 9 illustrates the serial port timing.

The PCM playback data being passed to the CS4299 is shifted out MSB first in the most significant bits
of each slot. Any PCM data from the AC ’97 controller that is not 20 bits wide should be left justified in
its corresponding slot and dithered or zero-padded in the unused bit positions.

Bits that are reserved should always be ‘cleared’ by the AC ’97 controller.

3.1.1 Serial Data Output Slot Tags (Slot 0)

Bit 1514131211109876543210

Val id

Slot 1

Frame

Valid Frame The Valid Frame bit determines if any of the following slots contain either valid playback data

Slot [1:2] Valid The Slot [1:2] Valid bits indicate the validity of data in their corresponding serial data output

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Reserved

Codec

for the CS4299 DACs or data for read/write operations. When ‘set’, at least one of the other
AC-link slots contain valid data. If this bit is ‘clear’, the remainder of the frame is ignored.

slots. If a bit is ‘set’, the corresponding output slot contains valid data. If a bit is ‘cleared’, the
corresponding slot will be ignored.

ID1

Codec

ID0

Slot [3:10] Valid The Slot [3:10] Valid bits indicate Slot [3:10] contains valid playback data for the CS4299. If a

Slot Valid bit is ‘set’, the named slot contains valid audio data. If the bit is ‘clear’, the slot will be
ignored. The CS4299 supports alternate slot mapping as defined in the AC ’97 2.1 specification.
For more information, see the AC Mode Control Register (Index 5Eh).

Codec ID[1:0] The Codec ID[1:0] bits display the Codec ID of the audio codec being accessed during the cur-

rent AC-link frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec
ID[1:0] = 01, 10, or 11 indicates one of three possible secondary codecs is being accessed. A
non-zero value of one or more of the Codec ID bits indicates a valid Read or Write Address in
Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2.

14

CS4299

3.1.2 Command Address Port (Slot 1)

Bit 191817161514131211109876543210

R/W RI6RI5RI4RI3RI2RI1RI0000000000000

R/W Read/Write. When this bit is ‘set’, a read of the AC ’97 register specified by the register index

bits will occur in the AC ’97 2.1 audio codec. When the bit is ‘cleared’, a write will occur. For any
read or write access to occur, the Frame Valid bit (F0) must be ‘set’ and the Codec ID[1:0] bits
(F[14:15]) must match the Codec ID of the AC ’97 2.1 audio codec being accessed. Additionally,
for a primary codec, the Slot 1 Valid bit (F1) must be ‘set’ for a read access and both the Slot 1
Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘set’ for a write access. For a secondary co­dec, both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘cleared’ for read and
write accesses. See Figure 9 for bit frame positions.

RI[6:0] Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the

CS4299. All registers are defined at word addressable boundaries. The RI0 bit must be ‘clear’
to access CS4299 registers.

3.1.3 Command Data Port (Slot 2)

Bit 191817161514131211109876543210

WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Reserved

WD[15:0] Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an access

is a read, this slot is ignored.

NOTE: For any write to an AC ’97 register, the write is defined to be an ‘atomic’ access. This means

that when the Slot 1 Valid bit in output Slot 0 is ‘set’, the Slot 2 Valid bit in output slot 0 should
always be ‘set’ during the same audio frame. No write access may be split across 2 frames.

3.1.4 PCM Playback Data (Slots 3-10)

Bit 191817161514131211109876543210

PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PD[19:0] Playback Data. The PD[19:0] bits contain the 20-bit PCM playback (2’s complement) data for

the left and right DACs and/or the S/PDIF transmitter. Table 8 on page 30 lists a cross reference
for each function and its respective slot. The mapping of a given slot to a DAC is determined by
the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and by the SM[1:0]
and AMAP bits in the AC Mode Control Register (Index 5Eh).

15

CS4299

3.2 AC-Link Audio Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4299 to the AC ’97 con-
troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illus­trates the serial port timing.

The PCM capture data from the CS4299 is shifted out MSB first in the most significant 18 bits of each slot.
The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the AC ’97
Controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun­cate) to the desired bit depth.

Bits that are reserved or not implemented in the CS4299 will always be returned ‘cleared’.

3.2.1 Serial Data Input Slot Tag Bits (Slot 0)

Bit 1514131211109876543210

Codec
Ready

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

00000

Codec Ready The Codec Ready bit indicates the readiness of the CS4299 AC-link. Immediately after a Cold

Reset this bit will be ‘clear’. Once the CS4299 clocks and voltages are stable, this bit will be
‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be attempted by the
controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any
other analog function. Those must be checked in the Powerdown Control/Status Register (In-
dex 26h) by the controller before any access is made to the mixer registers. Any accesses to
the CS4299 while Codec Ready is ‘clear’ are ignored.

Slot 1 Valid When ‘set’, the Slot 1 Valid bit indicates Slot 1 contains a valid read back address.

Slot 2 Valid When ‘set’, the Slot 2 Valid bit indicates Slot 2 contains valid register read data.

Slot [3:10] Valid When ‘set’, the Slot [3:10] Valid bits indicate Slot [3:10] contains valid capture data from the

CS4299 ADCs. Only if a Slot [3:10] Valid bit is ‘set’ will the corresponding input slot contain
valid data.

3.2.2 Status Address Port (Slot 1)

Bit 1918171615141312111098 7 65 4 3210

0 RI6 RI5 RI4 RI3 RI2 RI1 RI0 SR3 SR4 SR5 SR6 SR7 SR8 SR9 SR10 0 Reserved

RI[6:0] Register Index. The RI[6:0] bits echo the AC ’97 register address when a register read has

been requested in the previous frame. The CS4299 will only echo the register index for a read
access. Write accesses will not return valid data in Slot 1.

SR[3:10] Slot Request. If SRx is ‘set’, this indicates the CS4299 SRC does not need a new sample on

the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample
is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register

(Index 2Ah) is ‘clear’, the SR[3:10] bits are always 0. When VRA is ‘set’, the SRC is enabled

and the SR[3:10] bits are used to request data.

16