Cirrus Logic CS4299-BQ User Manual

Copyright © Cirrus Logic, Inc. 2006

(All Rights Reserved)

Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

http://www.cirrus.com

CrystalClear® SoundFusion™ Audio Codec ‘97

CS4299-BQ

March '06

DS319-BQPP2

CrystalClear® SoundFusion™ Audio Codec’97

Features

l AC’97 2.1 Compatible
l Industry Leading Mixed Signal Technology
l 20-bit Stereo Digital-to-Analog Converters
l 18-bit Stereo Analog-to-Digital Converters
l Sample Rate Converters
l Four Analog Line-level Stereo Inputs for

LINE_IN, CD, VIDEO, and AUX

l Two Analog Line-level Mono Inputs for

Modem and Internal PC Beep

l Dual Stereo Line-level Outputs for

LINE_OUT and ALT_LINE_OUT

l Dual Microphone Inputs

CS4299-BQ

l Meets or Exceeds the Microsoft

Audio Performance Requirements

l S/PDIF Digital Audio Output
l CrystalClear

®

3D Stereo Enhancement

l Industrial Temperature Range

Description

The CS4299-BQ is an AC’97 2.1 compatible stereo au­dio codec designed for PC multimedia systems. Using
the industry leading CrystalClear
mixed signal technology, the CS4299-BQ enables the
design of PC99-compliant desktop, portable, and enter­tainment PCs.

Coupling the CS4299-BQ with a PCI audio accelerator
or core logic supporting the AC ’97 interface, implements
a cost effective, superior quality, audio solution. The
CS4299-BQ surpasses PC 99 and AC ’97 2.1 audio
quality standards.

®

PC 99

®

delta-sigma and

l High Quality Pseudo-Differential CD Input
l Extensive Power Management Support

AC-LINK AND AC '97

REGISTERS

PWR

TEST

MGT

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

ID0#
ID1#

EAPD

SPDIF_OUT

AC-

LINK

AC '97

REGISTERS

EAPD, S/PDIF

SRC

GAIN / MUTE CONTROLS

MIXER / MUX SELECTS

SRC

ORDERING INFO

CS4299-BQZ lead-free 48-pin LQFP 9x9x1.4 mm

ANALOG INPUT MUX
AND OUTPUT MIXER

LINE

PCM_DATA

PCM_DATA

18 bit

ADC

3D Stereo

Enhancement

20 bit

DAC

INPUT

MUX

INPUT
MIXER

Σ

OUTPUT

MIXER

Σ

CD
AUX
VIDEO

MIC1
MIC2

PHONE
PC_BEEP

LINE_OUT
ALT_LINE_OUT
MONO_OUT

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright © Cirrus Logic, Inc. 2006

(All Rights Reserved)

DS319-BQPP2

MAR‘06

1

TABLE OF CONTENTS

2 DS319-BQPP2

CS4299-BQ

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................5

ANALOG CHARACTERISTICS................................................................................................5

ABSOLUTE MAXIMUM RATINGS ...........................................................................................6

RECOMMENDED OPERATING CONDITIONS.......................................................................6

DIGITAL CHARACTERISTICS.................................................................................................6

AC ’97 SERIAL PORT TIMING.................................................................................................7

2. GENERAL DESCRIPTION ..................................................................................................... 10

2.1 AC-Link ............................................................................................................................10

2.2 Control registers ..............................................................................................................10

2.3 Sample Rate Converters ..................................................................................................11

2.4 Output Mixer .................................................................................................................... 11

2.5 Input Mux .........................................................................................................................11

2.6 Volume Control ................................................................................................................11

3. ACLINK FRAME DEFINITION ...............................................................................................13

3.1 AC-Link Serial Data Output Frame ..................................................................................14

3.1.1 Serial Data Output Slot Tags (Slot 0).............................................................................14

3.1.2 Command Address Port (Slot 1).................................................................................... 15

3.1.3 Command Data Port (Slot 2)..........................................................................................15

3.1.4 PCM Playback Data (Slots 3-10)...................................................................................15

3.2 AC-Link Audio Input Frame ..............................................................................................16

3.2.1 Serial Data Input Slot Tag Bits (Slot 0) .........................................................................16

3.2.2 Status Address Port (Slot 1) ..........................................................................................16

3.2.3 Status Data Port (Slot 2)................................................................................................17

3.2.4 PCM Capture Data (Slot 3-10)....................................................................................... 17

3.3 AC-Link Protocol Violation - Loss of SYNC .....................................................................18

4. REGISTER INTERFACE ........................................................................................................19

4.1 Reset Register (Index 00h) .............................................................................................. 20

4.2 Master Volume Register (Index 02h) ...............................................................................20

4.3 Alternate Volume Register (Index 04h) ............................................................................ 21

4.4 Mono Volume Register (Index 06h) .................................................................................21

4.5 PC_BEEP Volume Register (Index 0Ah) .........................................................................22

4.6 Phone Volume Register (Index 0Ch)................................................................................22

4.7 Microphone Volume Register (Index 0Eh)........................................................................ 23

CS4299-BQ

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Microsoft is a registered trademark of Microsoft Corporation in the United States and/or other countries.
Intel is a registered trademark of Intel Corporation.
Crystal Clear and Sound Fusion are trademarks of Cirrus Logic.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor­mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the infor­mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without
warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or
other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets.
No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, pho­tographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user.
However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (elec­tronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a
basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors
and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list
of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2

CS4299-BQ

DS319-BQPP2 3

CS4299-BQ

4.8 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h)........................................... 24

4.9 Input Mux Select Register (Index 1Ah)............................................................................. 25

4.10 Record Gain Register (Index 1Ch) ................................................................................. 25

4.11 General Purpose Register (Index 20h)........................................................................... 26

4.12 3D Control Register (Index 22h)..................................................................................... 26

4.13 Powerdown Control/Status Register (Index 26h) ........................................................... 27

4.14 Extended Audio ID Register (Index 28h)........................................................................ 28

4.15 Extended Audio Status/Control Register (Index 2Ah) .................................................... 28

4.16 PCM Front DAC Rate Register (Index 2Ch) ................................................................ 29

4.17 PCM L/R ADC Rate Register (Index 32h)...................................................................... 29

4.18 AC Mode Control Register (Index 5Eh).......................................................................... 30

4.19 Misc. Crystal Control Register (Index 60h)..................................................................... 30

4.20 S/PDIF Control Register (Index 68h)............................................................................. 31

4.21 Vendor ID1 Register (Index 7Ch)................................................................................... 32

4.22 Vendor ID2 Register (Index 7Eh) ................................................................................... 32

5. POWER MANAGEMENT ....................................................................................................... 33

5.1 AC’97 Reset Modes ........................................................................................................ 33

5.1.1 Cold AC‘97 Reset .............................................................................................. 33

5.1.2 Warm AC’97 Reset ............................................................................................ 33

5.1.3 Register AC’97 Reset ........................................................................................ 33

5.2 Powerdown Controls ....................................................................................................... 34

6. ANALOG HARDWARE DESCRIPTION ................................................................................. 36

6.1 Analog Inputs ................................................................................................................... 36

6.1.1 Line-Level Inputs ................................................................................................. 36

6.1.2 CD Input .............................................................................................................. 36

6.1.3 Microphone Inputs .............................................................................................. 37

6.1.4 PC Beep Input ..................................................................................................... 37

6.1.5 Phone Input ......................................................................................................... 38

6.2 Analog Outputs ................................................................................................................ 38

6.2.1 Stereo Outputs .................................................................................................... 38

6.2.2 Mono Output ....................................................................................................... 38

6.3 Miscellaneous Analog Signals ......................................................................................... 39

6.4 Power Supplies ................................................................................................................ 39

6.5 Reference Design ............................................................................................................ 39

7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 40

8. GROUNDING AND LAYOUT ................................................................................................. 40

9. PIN DESCRIPTIONS ........................................................................................................... 42

10. PARAMETER AND TERM DEFINITIONS ............................................................................ 47

11. REFERENCE DESIGN ....................................................................................................... 49

12. REFERENCES ...................................................................................................................... 50

13. PACKAGE DIMENSIONS .................................................................................................... 51

3

LIST OF FIGURES

4 DS319-BQPP2

CS4299-BQ

Figure 1. Power Up Timing..............................................................................................................8

Figure 2. Codec Ready from Startup or Fault Condition................................................................. 8

Figure 3. Clocks ..............................................................................................................................8

Figure 4. Data Setup and Hold........................................................................................................9

Figure 5. PR4 Powerdown and Warm Reset ..................................................................................9

Figure 6. Test Mode........................................................................................................................ 9

Figure 7. AC-link Connections.......................................................................................................10

Figure 8. Mixer Diagram................................................................................................................12

Figure 9. AC-link Input and Output Framing..................................................................................13

Figure 10. Line Input (Replicate for Video and Aux) .....................................................................36

Figure 11. Differential 2 VRMS CD Input ......................................................................................36

Figure 12. Differential 1 VRMS CD Input ......................................................................................36

Figure 13. Microphone Input .........................................................................................................37

Figure 14. Microphone Pre-amplifier.............................................................................................37

Figure 15. PC_BEEP Input............................................................................................................37

Figure 16. Modem Connection...................................................................................................... 38

Figure 17. Alternate Line Output as Headphone Output............................................................... 38

Figure 18. Stereo Output...............................................................................................................38

Figure 19. Voltage Regulator ........................................................................................................39

Figure 20. S/PDIF Output..............................................................................................................40

Figure 21. Conceptual Layout for the CS4299-BQ........................................................................41

Figure 22. Pin Locations for the CS4299-BQ................................................................................42

Figure 23. CS4299 Reference Design ..........................................................................................49

CS4299-BQ

LIST OF TABLES

Table 1. Mixer Registers......................................................................................................................19

Table 2. Analog Mixer Output Attenuation...........................................................................................21

Table 3. Microphone Input Gain Values .............................................................................................. 23

Table 4. Analog Mixer Input Gain Values ............................................................................................ 24

Table 5. Stereo Volume Register Index...............................................................................................24

Table 6. Input Mux Selection ............................................................................................................... 25

Table 7. Standard Sample Rates......................................................................................................... 29

Table 8. Slot Mapping.........................................................................................................................30

Table 9. Device ID with Corresponding Part Number..........................................................................32

Table 10. Revision Values...................................................................................................................32

Table 11. Powerdown PR Bit Functions .............................................................................................. 34

Table 12. Powerdown PR Function Matrix ..........................................................................................35

Table 13. Power Consumption by Powerdown Mode..........................................................................35

4

1. CHARACTERISTICS AND SPECIFICATIONS

DS319-BQPP2 5

CS4299-BQ

CS4299-BQ

ANALOG CHARACTERISTICS Standard test conditions unless otherwise noted: T

AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; ZAL=100kΩ/
1000pF load, CDL = 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20kHz, 18-bit linear coding for ADC
functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain.

CS4299-BQZ

Parameter

(Note 2)

Full Scale Input Voltage
Line Inputs
Mic Inputs
Mic Inputs (20 dBinternal gain)

Full Scale Output Voltage
Line,Alternate Line, and Mono Outputs D-A 0.85 1.0 1.15 V

Frequency Response (Note 4)
Analog Ac = ± 0.25 dB
DAC Ac = ± 0.25 dB
ADC Ac = ± 0.25 dB

Dynamic Range
Stereo Analog inputs to LINE_OUT
Mono Analog inputs to LINE_OUT
DAC Dynamic Range
ADC Dynamic Range

DAC SNR (-20 dB FS input w/
CCIR-RMS filter on output)

Total Harmonic Distortion + Noise
(-3 dB FS input signal):
Line/Alternate Line Output
DAC
ADC (all inputs except phone/mic)
ADC (phone/mic)

Power Supply Rejection Ratio
(1kHz, 0.5 V

Interchannel Isolation - 60 - dB
Spurious Tone (Note 4) - -100 - dB FS
Input Impedance (Note 4) 10 - - kΩ
External Load Impedance 10 - - kΩ
Output Impedance (Note 4) - 730 - Ω
Input Capacitance (Note 4) - 5 - pF
Vrefout 2.0 2.28 2.5 V

w/ 5 V DC offset) (Note 4) - 40 - dB

RMS

Symbol Path

(Note 3)

A-D
A-D
A-D

FR

A-A
D-A
A-D

DR

A-A
A-A
D-A
A-D

SNR

D-A - 70 - dB

THD+N

A-A
D-A
A-D
A-D

20
20
20

-

-

-

-

-

-

-

-

-

-

-

1.00

1.00

0.10

-

-

-

90
85
85
80

-72

-72

-72

-72

-

-

-

20,000
20,000
20,000

-

-

-

-

-

-

-

-

ambient

= 25° C,

UnitMin Typ Max

V

RMS

V

RMS

V

RMS

RMS

Hz
Hz
Hz

dB FS A
dB FS A
dB FS A
dB FS A

dB FS
dB FS
dB FS
dB FS

Notes: 1. ZAL refers to the analog output pin loading and CDL refers to the digital output pin loading.

2. Parameter definitions are given in the Section10, Parameter and Term Definitions.

3. Path refers to the signal path used to generate this data. These paths are defined in the Section10,
Parameter and Term Definitions.

4. This specification is guaranteed by silicon characterization, it is not production tested.

5

CS4299-BQ

6 DS319-BQPP2

CS4299-BQ

ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Min Typ Max Unit

Power Supplies Digital

Analog
Total Power Dissipation (Supplies, Inputs, Outputs) - 0.95 1.25 W
Input Current per Pin (Except Supply Pins) -10 - 10 mA
Output Current per Pin (Except Supply Pins) -15 - 15 mA
Analog Input voltage -0.3 - AVdd +

Digital Input voltage -0.3 - DVdd +

Ambient Temperature (Power Applied) -40 - 85 °C
Storage Temperature -65 - 150 °C

-0.3

-0.3

-

-

5.5

5.5

0.3

0.3

RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Symbol Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog

Operating Ambient Temperature -40 - 85 °C

DVdd1, DVdd2
DVdd1, DVdd2
AVdd1, AVdd2

3.135

4.75

4.75

3.3
5
5

3.465

5.25

5.25

V
V

V

V

V
V
V

DIGITAL CHARACTERISTICS (AVss = DVss = 0 V)

Parameter Symbol Min Typ Max Unit

Low level input voltage V
High level input voltage V
High level output voltage V
Low level output voltage V
Input Leakage Current (AC-link inputs) -10 - 10 µA
Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA
Output buffer drive current

BIT_CLK, S/PDIF_OUT
SDATA_IN, EAPD (Note 4)

il

ih

oh

ol

- - 0.8 V

0.65 x DVdd - - V

0.90 x DVdd 0.99 x DVdd - V

- 0.03 0.10 x DVdd V

-

-

24

4

-

-

mA
mA

6

CS4299-BQ

DS319-BQPP2 7

CS4299-BQ

AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: T

AVdd = 5.0 V, DVdd = 3.3 V; C

= 55pF load.

L

ambient

= 25° C,

Parameter Symbol Min Typ Max Unit

RESET Timing

RESET# active low pulse width T
RESET# inactive to BIT_CLK start-up delay T
1st SYNC active to CODEC READY set T
Vdd stable to Reset inactive T

rst_low

rst2clk

sync2crd

vdd2rst#

1.0 - - µs

- 40.0 - µs

- 62.5 - µs

100 - - µs

Clocks

BIT_CLK frequency F
BIT_CLK period T

clk_period

clk

- 12.288 - MHz

- 81.4 - ns
BIT_CLK output jitter (depends on XTAL_IN source) - - 750 ps
BIT_CLK high pulse width T
BIT_CLK low pulse width T
SYNC frequency F
SYNC period T
SYNC high pulse width T
SYNC low pulse width T

sync_period

sync_high

sync_low

clk_high

clk_low

sync

36 40.7 45 ns
36 40.7 45 ns

- 48 - kHz

- 20.8 - µs

- 1.3 - µs

- 19.5 - µs

Data Setup and Hold

Output Propagation delay from rising edge of BIT_CLK T
Input setup time from falling edge of BIT_CLK T
Input hold time from falling edge of BIT_CLK T
Input Signal rise time T
Input Signal fall time T
Output Signal rise time (Note 4) T
Output Signal fall time (Note 4) T

co

isetup

ihold

irise

ifall

orise

ofall

- 12 - ns

10 - - ns

0 - - ns
2 - 6 ns
2 - 6 ns
2 4 6 ns
2 4 6 ns

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) T
SYNC pulse width (PR4) Warm Reset T
SYNC inactive (PR4) to BIT_CLK start-up delay T
Setup to trailing edge of RESET# (ATE test mode) (Note 4) T

s2_pdown

sync_pr4

sync2clk

setup2rst

Rising edge of RESET# to Hi-Z delay (Note 4) T

off

- .28 1.0 µs

1.0 - - µs

162.8 285 - ns
15 - - ns

- - 25 ns

7

BIT_CLK

8 DS319-BQPP2

CS4299-BQ

CS4299-BQ

RESET#

Vdd

BIT_CLK

SYNC

CODEC_READY

T

rst_low

T

vdd2rst#

Figure 1. Power Up Timing

T

sync2crd

T

rst2clk

BIT_CLK

T

orise

SYNC

T

irise

Figure 2. Codec Ready from Startup or Fault Condition

T

clk_highTclk_low

T

sync_high

T

Figure 3. Clocks

T

ifall

sync_period

T

clk_period

T

sync_low

T

ifall

8

BIT_CLK

DS319-BQPP2 9

CS4299-BQ

BIT_CLK

SDATA_IN

SDATA_OUT,
SYNC

Slot 1 Slot 2

T

co

T

isetup

Figure 4. Data Setup and Hold

CS4299-BQ

T

ihold

SDATA_OUT

SDATA_IN

SYNC

Write to 0x20 Data PR4 Don't Care

T

s2_pdown

T

Figure 5. PR4 Powerdown and Warm Reset

RESET#

T

setup2rst

SDATA_OUT,
SYNC

T

off

sync_pr4

T

sync2clk

SDATA_IN,

Hi-Z

BIT_CLK

Figure 6. Test Mode

9

CS4299-BQ

10 DS319-BQPP2

CS4299-BQ

2. GENERAL DESCRIPTION

The CS4299-BQ is a mixed-signal serial audio Co­dec compliant to the Intel® Audio Codec ‘97 Spec-
ification, revision 2.1 [1]. It is designed to be paired
with a digital controller, typically located on the
PCI bus or integrated within the system core logic
chip set. The controller is responsible for all com­munications between the CS4299-BQ and the re­mainder of the system. The CS4299-BQ contains
two distinct functional sections: digital and analog.
The digital section includes the AC-link interface,
S/PDIF interface, serial data port, Sample Rate
Converters, and power management support. The
analog section includes the analog input multiplex­er (mux), stereo output mixer, mono output mixer,
stereo Analog-to-Digital Converters (ADCs), ste­reo Digital-to-Analog Converters (DACs), and
their associated volume controls.

2.1 AC-Link

All communication with the CS4299-BQ is estab­lished with a 5-wire digital interface to the control­ler, as shown in Figure7. This interface is called
the AC-link. All clocking for the serial communi­cation is synchronous to the BIT_CLK signal.
BIT_CLK is generated by the primary audio codec
and is used to clock the controller and any second-

ary audio codecs. Both input and output AC-link
audio frames are organized as a sequence of 256 se­rial bits forming 13 groups referred to as ‘slots’.
During each audio frame, data is passed bi-direc­tionally between the CS4299-BQ and the control­ler. The input frame is driven from the CS4299-BQ
on the SDATA_IN line. The output frame is driven
from the controller on the SDATA_OUT line. The
controller is also responsible for issuing reset com­mands via the RESET# signal. Following a Cold
Reset, the CS4299-BQ is responsible for notifying
the controller that it is ready for operation after syn­chronizing its internal functions. The CS4299-BQ
AC-link signals must use the same digital supply
voltage as the controller chip, either +5 V or
+3.3V. See Section3, ACLink Frame Definition,
for detailed AC-link information.

2.2 Control registers

The CS4299-BQ contains a set of AC ’97 compli­ant control registers and a set of Cirrus Logic de­fined control registers. These registers control the
basic functions and features of the CS4299-BQ.
Read accesses of the control registers by the
AC’97 controller are accomplished with the re­quested register index in Slot1 of a SDATA_OUT
frame. The following SDATA_IN frame will con-

Digital AC'97

Controller

Figure 7. AC-link Connections

10

SYNC

BIT_CLK

SDATA_ OUT

SDATA_IN

RESET#

CODEC

CS4299-BQ

DS319-BQPP2 11

CS4299-BQ

tain the read data in its Slot 2. Write operations are
similar, with the register index in Slot 1 and the
write data in Slot 2 of a SDATA_OUT frame. The
function of each input and output frame is detailed
in Section3, ACLink Frame Definition. Individual
register descriptions are found in Section4, Regis-
ter Interface.

2.3 Sample Rate Converters

The Sample Rate Converters (SRCs) provide high
accuracy digital filters supporting sample frequen­cies other than 48kHz to be captured from the
CS4299 or played from the controller. AC ’97 re­quires support for two audio rates (44.1 and
48kHz). In addition, the Intel® I/O Controller Hub
(ICHx) specification requires support for five more
audio rates (8, 11.025, 16, 22.05, and 32). The
CS4299 supports all these rate, as shown in Table7
on page29.

2.4 Output Mixer

The CS4299-BQ has two output mixers, illustrated
in Figure8. The stereo output mixer sums together
the analog inputs to the CS4299-BQ, including the
PC_BEEP and PHONE signals, according to the
settings in the volume control registers. The stereo
output mix is sent to the LINE_OUT and

ALT_LINE_OUT pins on the CS4299-BQ. The
mono output mixer generates a monophonic sum of
the left and right channels from the stereo input
mixer. The mono output mix is sent to the
MONO_OUT output pin on the CS4299-BQ.

2.5 Input Mux

The input multiplexer controls which analog input
is sent to the ADCs. The output of the input mux is
converted to stereo 18-bit digital PCM data and
sent to the controller by means of the AC-link
SDATA_IN signal.

2.6 Volume Control

The CS4299-BQ volume registers control analog
input levels to the input mixer and analog output
levels, including the master volume level, and the
alternate volume level. The PC_BEEP volume con­trol uses 3dB steps with a range of 0dB to -45dB
attenuation. All other analog volume controls use

1.5dB steps. The analog inputs have a mixing
range of +12dB signal gain to -34.5dB signal at­tenuation. The analog output volume controls have
from 0dB to -94.5dB attenuation for LINE_OUT
and from 0dB to -46.5dB attenuation for
ALT_LINE_OUT and MONO_OUT.

11

CS4299-BQ

12 DS319-BQPP2

CS4299-BQ

PC_BEEP

PHONE

PCM_OUT

MIC1

MIC2

LINE

CD

VIDEO

AUX

MIC

SELECT

MAIN D/A

CONVERTERS

DAC

BOOST

VOL

VOL

VOL

VOL VOL

VOL VOL VOL

MUTE

MUTE

MUTE

MUTE

MUTE

MUTE

MUTE

MUTE

PC BEEP BYPASS

ΣΣ ΣΣ

INPUT MIXER

ANALOG STEREO

ΣΣ

ANALOG STEREO

OUTPUT MIXER

STEREO TO

MONO MIXER

ΣΣ

1/2

STEREO TO

MONO MIXER

ΣΣ

1/2

BYPASS
BUFFER

3D

3D OUTPUT

MIXER

DAC DIRECT

MONO OUT

ADC

INPUT

MUX

MODE

SELECT

MASTER
VOLUME

VOL VOL

ALT LINE
VOLUME

MONO

VOLUME

VOL

MAIN ADC

GAIN

VOL

MUTE

MUTE

MUTE

OUTPUT
BUFFER

OUTPUT
BUFFER

OUTPUT
BUFFER

MAIN A/D

CONVERTERS

ADCMUTE

LINE OUT

ALT LINE OUT

MONO OUT

PCM_IN

Figure 8. Mixer Diagram

12

CS4299-BQ

DS319-BQPP2 13

CS4299-BQ

3. ACLINK FRAME DEFINITION

The AC-link is a bidirectional serial port with data
organized into frames consisting of one 16-bit and
twelve 20-bit time-division multiplexed slots. The
first slot, called the tag slot, contains bits indicating
if the CS4299-BQ is ready to receive data (input
frame) and which, if any, other slots contain valid
data. Slots 1 through 12 contain audio or con­trol/status data. Both the serial data output and in­put frames are defined from the controller
perspective, not from the CS4299-BQ perspective.

The controller synchronizes the beginning of a
frame with the assertion of the SYNC signal.

Tag Phase Data Phase

Figure9 shows the position of each bit location
within the frame. The first bit position in a new se­rial data frame is F0 and the last bit position in the
serial data frame is F255. When SYNC goes active
(high) and is sampled active by the CS4299-BQ (on
the falling edge of BIT_CLK), both devices are
synchronized to a new serial data frame. The data
on the SDATA_OUT pin at this clock edge is the
final bit of the previous frame’s serial data. On the
next rising edge of BIT_CLK, the first bit of Slot0
is driven by the controller on the SDATA_OUT
pin. On the next falling edge of BIT_CLK, the
CS4299-BQ latches this data in, as the first bit of
the frame.

20.8 µs

(48 kHz)

SYNC

BIT_CLK

Bit Frame Position:

SDATA_OUT

Bit Frame Position:

SDATA_IN

12.288 MHz

81.4 ns

F255

F0 F1 F2 F16F15F14F13F12
Valid

Frame

F0 F1 F2 F16F15F14F13F12 F35 F56 F76F255

Codec
Ready

Slot 1

Valid

Slot 1

Valid

GPIO

INT

0

Slot 2

Valid

Slot 2

Valid

F36 F57

Slot 12

Valid

Slot 12

Valid

Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slots 5-12

Codec

Codec

0

ID1

R/W 0 WD15

ID0

0000

F35

F36

0

F56

D19 D18

F57

D19 D18 D19RD15

F76

D19

F96

D19

F96

D19

Figure 9. AC-link Input and Output Framing

F255

F255

GPIO

0

INT

13

CS4299-BQ

14 DS319-BQPP2

CS4299-BQ

3.1 AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4299-BQ from the AC
’97 controller. Figure9 illustrates the serial port timing.

The PCM playback data being passed to the CS4299-BQ is shifted out MSB first in the most significant
bits of each slot. Any PCM data from the AC ’97 controller that is not 20 bits wide should be left justified
in its corresponding slot and dithered or zero-padded in the unused bit positions.

Bits that are reserved should always be ‘cleared’ by the AC ’97 controller.

3.1.1 Serial Data Output Slot Tags (Slot 0)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Valid

Frame

Valid Frame The Valid Frame bit determines if any of the following slots contain either valid playback data

Slot [1:2] Valid The Slot [1:2] Valid bits indicate the validity of data in their corresponding serial data output

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

for the CS4299-BQ DACs or data for read/write operations. When ‘set’, at least one of the other
AC-link slots contain valid data. If this bit is ‘clear’, the remainder of the frame is ignored.

slots. If a bit is ‘set’, the corresponding output slot contains valid data. If a bit is ‘cleared’, the
corresponding slot will be ignored.

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Reserved

Codec

ID1

Codec

ID0

Slot [3:10] Valid The Slot [3:10] Valid bits indicate Slot [3:10] contains valid playback data for the CS4299-BQ.

If a Slot Valid bit is ‘set’, the named slot contains valid audio data. If the bit is ‘clear’, the slot will
be ignored. The CS4299-BQ supports alternate slot mapping as defined in the AC ’97 2.1 spec­ification. For more information, see the AC Mode Control Register (Index 5Eh).

Codec ID[1:0] The Codec ID[1:0] bits display the Codec ID of the audio codec being accessed during the cur-

rent AC-link frame. CodecID[1:0]= 00 indicates the primary codec is being accessed. Codec
ID[1:0] = 01, 10, or 11 indicates one of three possible secondary codecs is being accessed. A
non-zero value of one or more of the Codec ID bits indicates a valid Read or Write Address in
Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2.

14

CS4299-BQ

DS319-BQPP2 15

CS4299-BQ

3.1.2 Command Address Port (Slot 1)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RI6 RI5 RI4 RI3 RI2 RI1 RI0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

R/W

Read/Write. When this bit is ‘set’, a read of the AC ’97 register specified by the register index

bits will occur in the AC ’97 2.1 audio codec. When the bit is ‘cleared’, a write will occur. For any
read or write access to occur, the Frame Valid bit (F0) must be ‘set’ and the Codec ID[1:0] bits
(F[14:15]) must match the Codec ID of the AC ’97 2.1 audio codec being accessed. Additionally,
for a primary codec, the Slot 1 Valid bit (F1) must be ‘set’ for a read access and both the Slot 1
Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘set’ for a write access. For a secondary co­dec, both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘cleared’ for read and
write accesses. See Figure9 for bit frame positions.

RI[6:0] Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the

CS4299-BQ. All registers are defined at word addressable boundaries. The RI0 bit must be
‘clear’ to access CS4299-BQ registers.

3.1.3 Command Data Port (Slot 2)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Reserved

WD[15:0] Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an access

is a read, this slot is ignored.

NOTE: For any write to an AC ’97 register, the write is defined to be an ‘atomic’ access. This means

that when the Slot 1 Valid bit in output Slot 0 is ‘set’, the Slot 2 Valid bit in output slot 0 should
always be ‘set’ during the same audio frame. No write access may be split across 2 frames.

3.1.4 PCM Playback Data (Slots 3-10)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PD[19:0] Playback Data. The PD[19:0] bits contain the 20-bit PCM playback (2’s complement) data for

the left and right DACs and/or the S/PDIF transmitter. Table8 on page30 lists a cross reference
for each function and its respective slot. The mapping of a given slot to a DAC is determined by
the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and by the SM[1:0]
and AMAP bits in the AC Mode Control Register (Index 5Eh).

15

CS4299-BQ

16 DS319-BQPP2

CS4299-BQ

3.2 AC-Link Audio Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4299-BQ to the AC’97
controller. The data format for the input frame is very similar to the output frame. Figure9 on page13 il­lustrates the serial port timing.

The PCM capture data from the CS4299-BQ is shifted out MSB first in the most significant 18 bits of each
slot. The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the
AC’97 Controller that is less than 18 bits wide, the controller should dither and round or just round (but
not truncate) to the desired bit depth.

Bits that are reserved or not implemented in the CS4299-BQ will always be returned ‘cleared’.

3.2.1 Serial Data Input Slot Tag Bits (Slot 0)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Codec
Ready

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

0 0 0 0 0

Codec Ready The Codec Ready bit indicates the readiness of the CS4299-BQ AC-link. Immediately after a

Cold Reset this bit will be ‘clear’. Once the CS4299-BQ clocks and voltages are stable, this
bit will be ‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be attempted
by the controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref,
or any other analog function. Those must be checked in the Powerdown Control/Status Reg-
ister (Index 26h) by the controller before any access is made to the mixer registers. Any ac­cesses to the CS4299-BQ while Codec Ready is ‘clear’ are ignored.

Slot 1 Valid When ‘set’, the Slot 1 Valid bit indicates Slot 1 contains a valid read back address.

Slot 2 Valid When ‘set’, the Slot 2 Valid bit indicates Slot 2 contains valid register read data.

Slot [3:10] Valid When ‘set’, the Slot [3:10] Valid bits indicate Slot [3:10] contains valid capture data from the

CS4299-BQ ADCs. Only if a Slot [3:10] Valid bit is ‘set’ will the corresponding input slot con­tain valid data.

3.2.2 Status Address Port (Slot 1)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 RI6 RI5 RI4 RI3 RI2 RI1 RI0 SR3 SR4 SR5 SR6 SR7 SR8 SR9 SR10 0 Reserved

RI[6:0] Register Index. The RI[6:0] bits echo the AC’97 register address when a register read has

been requested in the previous frame. The CS4299-BQ will only echo the register index for
a read access. Write accesses will not return valid data in Slot 1.

SR[3:10] Slot Request. If SRx is ‘set’, this indicates the CS4299 SRC does not need a new sample on

the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample
is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register
(Index 2Ah) is ‘clear’, the SR[3:10] bits are always 0. When VRA is ‘set’, the SRC is enabled
and the SR[3:10] bits are used to request data.

16