Cirrus Logic CS4298-KQ, CS4298-JQ Datasheet

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CS4298

SoundFusion® Audio/Modem Codec ’97(AMC’97)

FEATURES

■ AC ‘97 2.0 compatible

■ 20-bit stereo output and 18-bit stereo input codec

with fixed 48 kHz sampling rat e

■ 20-bit output and 18-bit input dual modem AFE

with fixed 48 kHz s ampling rate

■ Dedicated ADC for handset or speakerphone

■ Four analog line-level stereo inputs for connec-

tion from LINE IN, CD, VIDEO, and AUX

■ High quality pseudo-differential CD input

■ Dual stereo line level output with independent 6-

bit volume control

■ 10 General Purpose I/O pins for Modem DAA

controls

■ IEC-958 Digital Output (S/PDIF)

■ Meets or exceed s M i cro soft's

audio performance requirements

■ CrystalClear™ 3D Stereo Enha ncement

PCM_OUT

MIC1

MIC2

LINE

VIDEO

AUX

MIC SELECT

PC 98 and PC 99

MAIN D/A

CONVERTERS

VOL MUTE

DAC

VOL

+20dB

VOL

PCM OUT

PATH

MUTE

STEREO TO

MONO MIXER

DESCRIPTION

The CS4298 is an AC ‘97 compatible Audio/Modem Co dec des igned for P C mu ltim edia sy stem s. Using the industry leading CrystalClear™ deltasigma and mixed signal technology, the CS4298 is ideal for PC 98-compliant desktop, notebook, and entertain ment PCs, w here high-q uality audio an d modem features are required.The CS4298 offers four channels of D/A and A/D conversion along with ana log mixing an d 3D proc essing. For m ultichannel audio systems, the CS4298 can provide four audio channels . For c ombined audio/mod em systems , the C S42 98 can prov ide a mod em AFE , voice codec, and stereo audio c odec..

ORDERING INFORMATION

CS4298-KQ 64-pin TQFP 10x10x1.4mm CS4298-JQ 64-pin TQFP 10x10x1.4mm

STEREO

INPUT MIXER

ΣΣ

STEREO OUTPUT

MIXER

MAIN ADC GAIN

ADC

VOL MUTE ADC

INPUT

MUX

MASTER VOLUME

VOL

ALTERNATE VOLUME

VOL

OUTPUT BUFFER

LINE_OUT

ALT_LINE_OUT

SDATA_OUT

RESET#

Mode Control

SYNC

MRX+

MRX-

HRX+

HRX-

(loopback) MTX+

(loopback) MTX-

(loopback) HTX+

(loopback) HTX-

Vref

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

SDATA_IN

AC-Link Interface

VOL

ADC DAC

MRX-

MRX+

HRX+

HRX-

- +

Class AB

+ -

- +

Class AB

+ -

Dif out

BIT_CLK GPIO

MTX+

MTX-

HTX+

HTX-

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

DS315PP2

AUG ‘99

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................5

AUDIO ANALOG CHARACTERISTICS......... ......... ................. ......... .......... ......... .....................5

ABSOLUTE MAXIMUM RATINGS...........................................................................................6

RECOMMENDED OPERATING CONDITIONS.......................................................................6

MIXER CHARACTERISTICS. ................. ......... .......... ......... ................. ......... .......... ..................6

MODEM CHARACTERISTICS.................................................................................................7

SERIAL PORT TIMING.............................................................................................................9

2. GENERAL DESCRIPTION .....................................................................................................12

2.1 Overview...................... ......... ................................. .......... ................................. ................12

2.2 Modes of Operation ..........................................................................................................12

2.2.1 Mode 0 ....................................................................................................................12

2.2.2 Mode 1 ....................................................................................................................12

2.2.3 Mode 2 ....................................................................................................................12

2.2.4 Mode 3 ....................................................................................................................12

3. DIGITAL SECTION .................................................................................................................13

3.1 AC-Link.......................... ......... .......... ................ .......... ......... ................. ......... ................. ..13

3.2 Control registers................................................................................................................13

4. ANALOG SECTION ................................................................................................................14

4.1 Audio Output Mixer...........................................................................................................14

4.2 Audio Input Mux................................................................................................................14

4.3 Audio Input Mixer..............................................................................................................14

4.4 Audio Volume Control.......................................................................................................14

5. AC ‘97 .....................................................................................................................................16

5.1 AC ‘97 Frame Definition ....................................................................................................16

5.2 AC-Link Serial Data Output Frame...................................................................................16

5.3 AC-Link AudioOutput Frame.............................................................................................17

5.3.1 Serial Data Output Slot Tags (Slot 0).............................................................................17

5.3.2 Register Address (Slot 1)...............................................................................................17

5.3.3 Register Write Data (Slot 2)...........................................................................................18

5.3.4 Playback Data (Slots 3-11)............................................................................................18

5.3.5 GPIO Data (Slot12)........................................................................................................18

5.4 AC-Link Audio Input Frame...............................................................................................18

5.4.1 Serial Data Input Slot Tag Bits (Slot 0) .........................................................................18

5.4.2 Read-Back Address Port (Slot 1). ..................................................................................19

5.4.3 Read-Back Data Port (Slot 2) ........................................................................................19

5.4.4 PCM Capture Data (Slot 3-11).......................................................................................19

5.4.5 GPIO Pin Status (Slot 12)..............................................................................................19

CS4298

Contacting Cirrus Logic Support

For a complete listing of Dir ect Sales, Distrib utor, and S ales Representative contacts, vi sit the Cirr us Logic w eb site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for whi ch full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any

kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc . Items fro m any Cirrus Logic webbiest or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be regi stered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2 DS315PP2

CS4298

5.5 AC ’97 Reset Modes.........................................................................................................20

5.5.1 Cold AC ‘97 Reset................................................................................................... 20

5.5.2 Warm AC ’97 Reset ................................................................................................20

5.5.3 AC’97 Register Reset.............................................................................................20

5.6 AC-Link Protocol Violation - Loss of SYNC...................................................................... 20

6. REGISTER INTERFACE ........................................................................................................21

6.1 Register Descriptions .......................................................................................................23

6.1.1 Reset (Index 00h) ......................................................................................................... 23

6.1.2 Master Volume (Index 02h) .......................................................................................... 23

6.1.3 Alternate Volume (Index 04h) ....................................................................................... 24

6.1.4 Microphone Volume (Index 0Eh)................................................................................... 24

6.1.5 Stereo Analog Mixer Input Gain (Index’s 10h - 18h) ..................................................... 25

6.1.6 Input Mux Select (Index 1Ah) ........................................................................................ 25

6.1.7 Record Gain (Index 1Ch)............................................................................................... 26

6.1.8 Record Gain Microphone (Index 1Eh)...........................................................................26

6.1.9 General Purpose (Index 20h) ........................................................................................ 26

6.1.10 3D Control (Index 22h)................................................................................................ 26

6.1.11 Power Down Control/Status (Index 26h) .................................................. ....... ..... .......27

6.1.12 Extended Audio ID (Index 28h) ..................................................................................28

6.1.13 Extended Audio Status / Control (Index 2Ah) ............................................................. 28

6.1.14 PCM Front DAC Rate (Index 2Ch) ...........................................................................29

6.1.15 PCM Surround DAC Rate (Index 2Eh) .................................................. ..... .. ..... .......29

6.1.16 PCM LFE DAC Rate (Index 30h) .................................................. ....... .. ..... ....... ..... ..29

6.1.17 PCM LR ADC Rate (Index 32h)................................................................................... 29

6.1.18 PCM MIC ADC Rate (Index 34h)................................................ ..... .. ..... .. ....... ..... ..... ..29

6.1.19 Center LFE Volume (Index 36h)..................................................................................30

6.1.20 LR Surround Volume (Index 38h)................................................................................ 30

6.1.21 Extended Modem ID (Index 3Ch) ............................................................................... 30

6.1.22 Extended Modem ID (Index 3Eh) ............................................................................... 31

6.1.23 Line 1 DAC/ADC Rate (Index 40h)......................................................... ....... .. .......... ..31

6.1.24 Line 2 DAC/ADC Rate (Index 42h)......................................................... ....... .. .......... ..31

6.1.25 Handset DAC/ADC Rate (Index 44h) .......................................................................... 32

6.1.26 Line 1 DAC/ADC Level (Index 46h)................................................................. .......... ..32

6.1.27 Line 2 DAC/ADC Level (Index 48h)................................................................. .......... ..32

6.1.28 Handset DAC/ADC Level (Index 4Ah)......................................................................... 32

6.1.29 GPIO Pin Configuration (Index 4Ch)........................................................................... 33

6.1.30 GPIO Pin Polarity/Type Configuration (Index 4Eh) ..................................................... 33

6.1.31 GPIO Pin Sticky (Index 50h)........................................................................................ 33

6.1.32 GPIO Pin Wakeup Mask (Index 4Ch)......................................................................... 34

6.1.33 GPIO Pin Status (Index 54h)....................................................................................... 34

6.1.34 Misc. Modem AFE Status (Index 56h) ........................................................................ 34

6.1.35 AC Mode Control (Index 5Eh) ............................... ....... ....... .. ............ ..... ....... ....... .......35

6.1.36 S/PDIF Control (Index 68h) .........................................................................................35

6.1.37 Vendor ID1 (Index 7Ch)......................................................... .......... ....... ....... ............ ..36

6.1.38 Vendor ID2 (Index 7Eh)........................................... ....... ....... ................. ......... ............36

7. ANALOG HARDWARE DESCRIPTION ................................................................................. 37

7.1 Line-Level Inputs..............................................................................................................37

7.2 Microphone Level Inputs .................................................................................................. 38

7.3 Line Level Outputs............................................................................................................ 38

7.4 Consumer IEC-958 Digital Interface (S/PDIF)..................................................................39

7.5 Miscellaneous Analog Signals..........................................................................................39

7.6 Power Supplies................................................. .......... .. ....... ..... ....... ....... ..... ....... .. ............ 40

7.7 Hybrid Int er fa c e............. ......... ................. ......... .......... ................ .......... ......... ................... 41

DS315PP2 3

8. PIN DESCRIPTIONS ..............................................................................................................42

8.1 g2 ......................................... ......... .......... ................. ......... ................................. .......... ....43

8.2 Analog I/O Pins ................................................................................................................45

8.3 Filter and Reference Pins ................................................................................................46

8.4 Modem/Telephony ...........................................................................................................47

8.5 Power Supplies ................................................ .......... ....... .. ....... ..... ....... ....... ..... ....... .......48

9. PARAMETER AND TERM DEFINITIONS ..............................................................................49

10. REFERENCES ......................................................................................................................50

11. PACKAGE DIMENSIONS .....................................................................................................51

LIST OF FIGURES

Figure 1. Power Up Timing............................................................................................................10

Figure 2. Clocks ............................................................................................................................10

Figure 3. Codec Ready from Startup or Fault Condition...............................................................10

Figure 4. Data Setup and Hold ......................................................................................................11

Figure 5. PR4 Powerdown............................................................................................................11

Figure 6. Test Mode......................................................................................................................11

Figure 7. AC-link Connections.......................................................................................................13

Figure 8. Mixer Diagram................................................................................................................15

Figure 9. AC-link Input and Output Framing..................................................................................16

Figure 10. Line Inputs........................................................................................................ ............37

Figure 11. Differential CDROM In .................................................................................................37

Figure 12. PC ‘99 Microphone Pre-amplifier ....................................................... ............ ............ ..38

Figure 13. Headphones Driver ......................................................................................................39

Figure 14. IEC-958 Interface Examples........................................................................................40

Figure 15. Voltage Regulator ........................................................................................................ 40

Figure 16. Hybrid Circuit Secondary ............................ ..... ..... .. ..... .. ..... .. ..... ..... .. ..... .. ..... .. ..... ..... ..41

CS4298

LIST OF TABLES

Table 1. Mixer Registers ...............................................................................................................21

Table 2. Alternate Line-Out and Master Mono Attenuation...........................................................24

Table 3. Analog Mixer Input Gain Values......................................................................................24

Table 4. Stereo Volume Register Index ........................................................................................25

Table 5. Input Mux Selection.........................................................................................................25

Table 6. 6 Channel Volume Attenuation........................................................................................30

Table 7. GPIO Input/Output Configuration....................................................................................33

Table 8. Misc. Modem Configuration.............................................................................................34

Table 9. Slot Assignments............................................................................................................35

Table 10. Reg. 7Eh Defined Part ID’s...........................................................................................36

4 DS315PP2

CS4298

1. CHARACTERISTICS AND SPECIFICATIONS

AUDIO ANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted:

Z for ADC, 20-bit linear coding for DAC; Mixer registers set for unity gain.

= 25° C, AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz;

ambient

=10 kΩ/680 pF load CDL = 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding

Path

Parameter (Note 2)Symbol

(Note 3)

CS4298-KQ CS4298-JQ

UnitMin Typ Max Min Typ Max

Full Scale Analog Input Voltage Line Inputs Mic Inputs (20 dB=0) Mic Inputs (20 dB=1)

A-D A-D A-D

0.91

0.091

1.00

0.10

0.91

0.091

1.00

0.10

V V V

RMS RMS RMS

Full Scale Output Voltage (Note 4) Line and Alternate Line Outputs D-A 0.91 1. 0 1.13 0.91 1.0 1.13 V

RMS

Frequency Response Analog Ac = ± 0.5 dB DAC Ac = ± 0.5 dB ADC Ac = ± 0.5 dB

FR A-A

D-A A-D

20 20 20

20,000 20,000 20,000

20 20 20

20,000 20,000 20,000

Hz Hz Hz

Dynamic Range Stereo Analog inputs to LINE_OUT Mono Analog inputs to LINE_OUT DAC Dynamic Range ADC Dynamic Range

DR A-A

A-A D-A A-D

90 85 85 85

95 90 90 90

dB FS A dB FS A dB FS A dB FS A

DAC SNR (-20 dB FS input w/ CCIR-RMS filter on output) SNR D-A - 63 - - - - dB

Total Harmonic Distortion + Noise (-3 dB FS input signal): Line/Alternate Line Output DAC ADC (all inputs except phone/mic) ADC (phone/mic)

THD+N A-A

D-A A-D A-D

-94

-86

-87

-80

-74

dB FS A

-74

dB FS A

-74

dB FS A

-74

dB FS A

Power Supply Rejection Ratio (1 kHz, 0.5 V

w/ 5 V DC offset)(Note 5) 40 60 - - 40 - dB

RMS

Interchannel Isolation 70 87 - - 87 - dB Spurious Tone (Note 5) - -100 - - -100 - dB FS Input Impedance (Note 5) 10 - - 10 - - kΩ External Load Impedance 10 - - 10 - - kΩ Output Impedance (Note 5) - 730 - - 730 - W Input Capacitance (Note 5) - 5 - - 5 - pF Vrefout 2.0 2.3 2.4 2.0 2.3 2.4 V

Notes: 1. Z

2. Parameter definitions are given in the

3. Path refers to the signal path used to generate this data. These paths are defined in the

4. Typical measured with Z

refers to the analog output pin loading and CDL refers to the digital output pin loading.

Term Definition

section.

=47kΩ/680 pF load.

Parameter and Term Definitions

section.

Parameter and

5. This specification is guaranteed by silicon characterization, it is not production tested.

DS315PP2 5

CS4298

ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog Total Power Dissipation (Supplies, Inputs, Outputs) - - 750 m W Input Current per Pin (Except Supply Pins) -10 - 10 mA Output Current per Pin (Except Supply Pins) -15 - 15 mA Analog Input voltage -0.3 - AVdd+

Digital Input voltage -0.3 - DVdd +

Ambient Temperature (Power Applied) -55 - 1 10 °C

Storage Temperature -65 - 150 °C

RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Symbol Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog

Operatin g C u r rent +3.3 V Digital

+5 V Digital

Analog Operating Ambient Temperature 0 - 70 °C

DVdd1, DVdd2 DVdd1, DVdd2

AVdd1, AVdd2

DVdd1, DVdd2

AVdd1, AVdd2

-0.3

3.135

4.75

3.3 5 5

40 40 75

6.0

0.3

3.465

5.25

5.25 52

97.5

V V V

mA mA mA

V V V

MIXER CHARACTERISTICS (for CS4298-KQ only)

Parameter Min Typ Max Unit

Mixer Gain Range Span Line In, Aux, CD, Video, Mic1 Mic2,

Line Out, Alternate Line Out

Step Size All volume controls - 1.5 - dB

46.5

94.5

dB dB

6 DS315PP2

CS4298

MODEM CHARACTERISTICS (Analog Transmitter Specifications: T

V; Sample Frequency, Fs = 48 kHz; Audio specifications for 20Hz - 5 kHz, actual digital filter may cutoff at 20 kHz, 600 Ω differential load where applicable)

Parameter Min Typical Max Units

= 0° to 70° C, AVdd = 5.0

ambient

Modem Analog Transmitter Characteristics

Resolution 20 bits Dynamic Range (Note 5) 100 dB FS Passband 20 5000 Hz Passband Ripple ±0.125 dB1K Total Harmonic Distortion 85 88 dB FS Full Scale Peak to Peak Output Voltage (TX+ to TX-) TBD 5.6 TBD Volts AC Output Impedance (TX+, TX-) (Note 5) 0.1 W Load Impedance (per pin) (Note 5) 250 W Power Supply Rejection (1kHz) (Note 5) 60 dB Output Current (per pin) 7.4 mA Offset (relative) (Note 5) 6 mV Out of Band specifications (T

Sample Frequency, Fs = 48 kHz; measurement bandwidth 20 kHz - 1MHz, R

Total Out of Band energy (20 kHz - 1 MHz) (Note 5) -30 dBV Highest 9kHz band (noise + tone) power (90 kHz - 2 MHz)

=600 Ω, CL=33nF) (Note 5) -40 dB FS

= 25° C, AVdd = 5 V;

ambient

-55 dBV

(Note 5, 6)

Modem Analog Receiver Characteristics

Resolution 18 bits Dynamic Range Gain = 0 90 dB FS Passband 20 5000 Hz Passband Ripple ±0.125 dB1K Total Harmonic Distortion Gain = 0 85 dB FS Total Absolute Gain Accuracy -5 +5 % Full Scale Peak to Peak Input Voltage (RX+ to RX-,

differential) Gain = 0 2.8 Volts Input Impedance (per pin) (Note 5) 15 KΩ Offset (relative) (Note 5) 6 mV Power Supply Rejection (Note 5) 40 60 dB

Notes: 6. This is the FCC specification for Out-of-Band energy at the telephone jack interface. 9 kHz refers to the

bin size of an FFT performed over the entire range. The amount of noise plus tone power in each 8kHz bin must be less than -55dBV.

DS315PP2 7

CS4298

DIGITAL CHARACTERISTICS (AVss = DVss = 0 V)

Parameter Symbol Min Typ Max Unit

DVdd = 3.3V

Low level input voltage V High level input voltage V High level output voltage V Low level output voltage V

2.15 V

3.0 3.25 V

0.03 .35 V

Input Leakage Current (AC-link inputs) -10 - 10 µA

Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA Output buffer drive current

BIT_CLK SDATA_IN, EAPD S/PDIF_OUT (Note 5)

12.5

DVdd = 5.0 V

Low level input voltage V High level input voltage V High level output voltage V Low level output voltage V

3.25 V

4.5 4.95 V

-0.03.35V Input Leakage Current (AC-link inputs) -10 - 10 µA Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA Output buffer drive current

BIT_CLK SDATA_IN, EAPD S/PDIF_OUT (Note 5)

12.5

0.8 V

mA mA mA

0.8 V

mA mA mA

8 DS315PP2

CS4298

SERIAL PORT TIMING

Parameter Symbol Min Typ Max Unit

RESET# Timing

Vdd stable to RESET# inactive T RESET# active low pulse width T RESET# inactive to BIT_CLK start-up delay T 1st SYNC active to CODEC READY set T

vdd2rst#

rst_low

rst2clk

sync2crd

Clocks

BIT_CLK frequency F BIT_CLK period T

clk

clk_period

BIT_CLK output jitter (depends on XTAL_IN source) - - 750 ps BIT_CLK high pulse width T BIT_CLK low pulse width T SYNC frequency F SYNC period T SYNC high pulse width T SYNC low pulse width T

clk_high

clk_low

sync

sync_period

sync_high

sync_low

Data Setup and Hold

Output Propagation delay from rising edge of BIT_CLK T Input setup time from falling edge of BIT _CLK T Input hold time from falling edge of BIT_CLK T Input Signal rise time T Input Signal fall time T Output Signal rise time (Note 5, 7) T Output Signal fall time (Note 5, 7) T

isetup

ihold

irise

ifall

orise

ofall

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) T SYNC pulse width (PR4) Warm Reset T SYNC inactive (PR4) to BIT_CLK start-up delay T Setup to trailing edge of RESET# (test mode) (Note 5) T Rising edge of RESET# to Hi-Z delay (Note 5) T

s2_pdown

sync_pr4

sync2clk

setup2rst

off

Notes: 7. BIT_CLK measured with 47 Ω seri es termination and CL=50 pF.

5. ms

1.0 - - µs 25 120 - µs

-62.4-µs

- 12.288 - MHz

-81.4-ns

36 40 .7 45 ns 36 40.7 45 ns

-48-kHz

-20.8-µs

-1.3-µs

-19.5-µs

- 6 12 ns

10 - - ns

0--ns 2-6ns 2-6ns 246ns 246ns

-.341.0µs

1.1 - - µs

162.8 350 - ns 15 - - ns

- - 25 ns

DS315PP2 9

BIT_CLK

RESET#

Vdd

rst_low

vdd2rst#

Figure 1. Power Up Timing

rst2clk

CS4298

BIT_CLK

SYNC

CODEC_READY

BIT_CLK

orise

SYNC

irise

sync2crd

Figure 2. Clocks

clk_highTclk_low

sync_high

clk_period

ifall

sync_low

ifall

sync_period

Figure 3. Codec Ready from Startup or Fault Condition

10 DS315PP2

BIT_CLK

SDATA_IN

SDATA_OUT, SYNC

Figure 4. Data Setup and Hold

Slot 1 Slot 2

CS4298

isetup

ihold

SDATA_OUT

SDATA_IN

SYNC

Write to 0x20 Data PR4 Don’t Care

s2_pdown

Figure 5. PR4 Powerdown

RESET#

setup2rst

SDATA_O U T, SYNC

off

sync_pr4

sync2clk

SDATA_IN, BIT_CLK

Hi-Z

Figure 6. Test Mode

DS315PP2 11

2. GENERAL DESCRIPTION

2.1 Overview

The CS4298 is a Mixed-Signal Audio/Modem Codec (AMC) based on the AC ‘97 1.0 Specification, and the AC ‘97 2.0 Extensions. It is designed to be paired with a digital controller, typically located on the PCI bus. The AMC Controller is responsible for all communications between the CS4298 and the rest of the system. The CS4298 functions as an analog mixer, a stereo audio ADC, a st ereo audio DAC, a dual modem AFE, and a control and digital stream interface to the AMC Controller. The CS4298 contains three distinct functional sections: Digital, Analog Audio, and Analog Modem.

The Digital Section includes the AC-Link registers, power management support, SYNC detection circuitry, and AC-Link serial port interface logic. The Analog Audio section includes the analog input multiplexor (mux), stereo output mixer, stereo ADCs, stereo DACs, and analog volume controls. The Analog Modem section includes dual differential ADCs, dual differential DACs, analog loopback logic, GPIO control and status, and power down and wake-up logic.

2.2 Modes of Operation

The CS4298 has four bas ic modes of operation. Each mode a llows varying functionality to meet a wide variety of software and hardware configurations. On power up or system re set, the device reverts to the basic configuration Mode 0. The audio ADC’s and DAC’s functionality remains fixed for each mode, but the modem ADC’s and DAC’s functionality changes per each configuration. From a system perspe ctive, the device can pr ovide standard audio with mode m, two line interface, speakerphone, and four channel enhanced audio.

CS4298

2.2.1 Mode 0

This is the default operating mode for the CS4298. It supports the legacy AC ‘97 audio modes of operation including audio mixer, ADC’s, and DAC’s. The modem configuration supports a phone line for modem ADC/DAC1 and a handset interface for modem ADC/DAC2.

2.2.2 Mode 1

This is the two phone line mode of operation. It is similar to mode 0 but the modem ADC/DAC2 is interfaced to a second phone line in place of the handset.

2.2.3 Mode 2

This mode facilitates a full duplex speakerphone mode of operation. The ADC of modem ADC/DAC2 is connected directly to the audio microphone in place of the handset or line 2 input. This dedicated microphone capture path allows the host controller to implement echo cancellation for hands free telephone operation. The modem DAC2 is not used in this mode.

2.2.4 Mode 3

Mode 3 is the four channel expansion mode. The modem ADC/DAC pairs are utilized for enhanced audio functionality. The modem DAC’s are routed to the alternate line audio outputs pr oviding 2 additional audio channels. The modem ADC inputs may be connected to the output of the analog stereo input mixer for enhanced audio ef f ect processing or enhanced digital doc king in a note book application.

12 DS315PP2

3. DIGITAL SECTION

3.1 AC-Link

All communication with the Codec is established with a 5-wire digital interface to the C ontroller chip as shown in Figure 7. All clocking for the serial communication is synchronous to the BIT_CLK signal. BIT_CLK is generated by the primary Codec and is used to slave the Controller and any secondary Codecs, if applicable. An AC-link audio frame is a sequence of 256 s erial bits organized into 13 groups referred to as

‘slots’. One frame consists of one 16-bit slot and twelve 20-bit slots. During each audio frame, data is passed bi-directionally between the Codec and the Controller. The input frame is driven from the Codec on the SDATA_IN line. The output frame is driven from the Controller SDATA_OUT line. Both input and output frames contain the same number of bits and are organized with the same ‘slot’ configuration. The input and output frame have differing functions for each s lot. The Controller synchronizes the beginning of a frame with the SYNC signal. In Figure 9 the pos ition of each bit location within the fram e is noted. The first bit position in a new serial data frame is F0 and the last bit position in the serial data frame is F255. When SYNC goes active (high) and is sampled active by the CS4298 (on the falling edge of BIT_CLK), both devices are synchronized to a new serial data frame. The data on the SDATA_OUT pin at this clock edge is the final bit of the previous frame’s s erial data. On the next rising e dge of BIT_CLK, the first bit of Slot 0 is driven by the Controller on the SDATA_OUT pin. The CS4298 latches in this data, as the first bit of the frame, on the next falling edge of the BIT_CLK clock signal. The Controller is also responsible for issuing reset via the RESET# signal. After being reset, the Codec is responsible for flagging the Controller that it is ready for operation after synchronizing its internal functions. The AC-link signals may be referenced to either 5 Volts or 3.3 Volts. The CS4298 must use the same digital supply voltage as the Controller chip.

Digital AC’97

Controller

Figure 7. AC-link Connections

SYNC

BIT_CLK

SDATA_OUT

SDATA_ IN

RESET#

CS4298

CODEC

3.2 Control registers

All read accesses to the Codec are generated by requesting a register address (index number) in slot 1 of a SDATA_OUT frame. The f ollowing SDATA_IN frame will contain the regist er c ontent in its slot 2. The write operation is i dentical with the index in s lot 1 and the wr ite data in slot 2. The AC ‘97

Frame Definition section details the function of each input and output frame. Individual register descriptions are found in the Register Interface section.

AC-97 Register Interface The CS4298 implements the AC ’97 Registers in accordance with the AC ’97 2.0 Specification. See

the Register Interface section for details on the CS4298’s register set.

DS315PP2 13

4. ANALOG SECTION

Please refer to Figure 8, Mixer diagram, for a high-level graphical representation of the CS4298 analog mixer structure.

4.1 Audio Output Mixer

There are two output mixers on the CS4298. The stereo output mixer sums together the analog outputs from the Input Mixer, 3D enhancement, and the PCM DAC output. The stereo output mix is sent to the LINE_OUT and ALT_LINE_OUT output pins of the CS4298. When the device is set to Mode 3 or Mode 0-2 and the EAM in AC Mode Control (Index 5Eh) is set, the modem DAC outputs are routed to ALT_LINE_OUT.

4.2 Audio Input Mux

The input multiplexor controls which analog input is sent to the ADCs. The output of the input mux is converted to stereo 18-bit digital PCM data and sent to the AMC Controller chip in Slots 3 and 4 of the AC-Link SDATA_IN signal.

4.3 Audio Input Mixer

The input mixer is an analog mix of the analog input signals such as MIC, LINE_IN, etc., and the PCM Audio DAC output. The output of the mixer is routed to the ADC Input Mux, Audio Output Mixer, and may be routed to the Modem ADC input.

CS4298

4.4 Audio Volume Control

The volume control registers of the AC ’97 Register interface control analog input level to the input mixer, the master volume level, and the alternate volume level. All analog volume controls implement volume steps at nominally 1.5 dB per step. The analog inputs allow a mixing range of +12 dB of signal gain to -34.5 dB of signal attenuation. The analog output volume controls allows from 0 dB to -94.5 dB of attenuation.

14 DS315PP2

CS4298

MIC1

MIC2

LINE

VIDEO

AUX

SDATA_OUT

RESET#

SYNC

Mode Control

MRX+

MRX-

HRX+

HRX-

MAIN D/A

CONVERTERS

PCM_OUT

MIC SELECT

DAC

+20dB

VOL MUTE

VOL

MUTE

PCM OUT

PATH

STEREO

INPUT MIXER

STEREO TO

MONO MIXER

ΣΣ

STEREO OUTPUT

MIXER

MASTER VOLUME

VOL

ALTERNATE VOLUME

VOL

OUTPUT

BUFFER

LINE_OUT

ALT_LINE_OUT

MAIN ADC GAIN

(loopback) MTX+

(loopback) MTX-

Vref

(loopback) HTX+

(loopback) HTX-

Vref

VOL

AC-Link Interface

ADC DAC

ADC

INPUT

MUX

MRX+

HRX+

VOL MUTE ADC

MRX-

HRX-

- +

Class AB

Dif out

+ -

- +

Class AB

Dif out

+ -

SDATA_IN

BIT_CLK GPIO

MTX+

MTX-

HTX+

HTX-

Figure 8. Mixer Diagram

DS315PP2 15

5. AC ‘97

5.1 AC ‘97 Frame Definition

The AC Link is a bi-directional serial port with thirteen time-division multiplexed slots in each direction. The first slot is 16 bits long and termed the tag slot. Bits in the tag slot determine if the Codec is ready and indicate which, if any, other slots contain valid data. Slots 1 through 11 are 20-bits long and can contain audio data. Slot 12 contains data to be written and read from GPIO. The serial data

line is defined from the Controller’s perspective, NOT from the Audio Codec’s perspective.

5.2 AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin TO the CS4298 FROM the Controller. Figure 9 illustrates the serial port timing.

20.8 µS

(48 kHz)

Tag Phase Data Phase

CS4298

SYNC

BIT_CLK

Bit Frame Position:

SDATA_OUT

Bit Frame Position:

SDATA_IN

12.288 MHz

81.4 nS

F0 F1 F2 F16F15F14F13F12

F255

Valid

Slot 1

Frame

F0 F1 F2 F16F15F14F13F12 F35 F56 F76F255 F36 F57

Codec

Ready

Valid

Slot 1

Valid

Slot 2

Valid

Slot 2

Valid

Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slots 5-12

SCRA1 SCRA0

R/W 0 WD15

00000

F36 F57

F35

Figure 9. AC-link Input and Output Framing

F56

LP19 LP18 RP19

LC17 LC16 RC17RD15

F76

F97

F255

16 DS315PP2

CS4298

5.3 AC-Link AudioOutput Frame

5.3.1 Serial Data Output Slot Tags (Slot 0)

Bit 1514131211109876543210

Valid

Frame

Valid Fram eDetermines if any of the following slots contain either valid playback data for the Codec’s DACs, data

Slot [1:2] ValidIndicates valid slot data when accessing the register set of the primary Codec (SCRA[1:0] = 00). For

Slot [3:11] Valid

Slot 12 ValidIf Slot 12 Valid is set, Slot 12 contains valid write data for the GPIO pins.

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 1 1

Valid

Slot 12

Valid

SCRA1SCRA

for read/write operation, or GPIO data. When set, at least one of the other AC-link slots contain valid data. If this bit is clear, the remainder of the frame is ignored.

a read operation, Slot 1 Valid is set when eration, Slot 1 Valid and Slot 2 Valid are set indicating

(Slot 1) contains valid data. For a write op-

(Slot 1) and

(Slot 2) contain valid data. The register address and write data must be valid within the same frame. SCRA[1:0] must be cleared when accessing the primary Codec. The physical address of a Codec is determined by the ID[1:0]# input pins which are reflected in the and the

Extended Modem ID

(Index 3Ch) register.

Extended Audio ID

(Index 28h) register

If a Slot Valid bit is set, the named slot contains valid audio data. If the bit is clear, the slot will be ignored. The definition of each slot is determined by the basic operating mode selected for the CS4298. For more information, see the

AC Mode Control

(Index 5Eh) register.

SCRA[1:0] Secondary Codec Register Access. Unlike the primary Codec, SCRA[1:0] indicate valid slot data when

accessing the register set of a secondary Codec. The value set in SCRA[1:0] (01,10,11) determines which of the three possible secondary Codecs is accessed. For a read operation, the SCRA[1:0] bits are set when set when

(Slot 1) contains valid data. For a write operation, SCRA[1:0] bits are

(Slot 1) and

(Slot 2) contain valid data. The write operation requires the register address and the write data to be valid within the same frame. SCRA[1:0] must be cleared when accessing the primary Codec. They must also be cleared during the idle period where no register read or write is pending. The physical address of a Codec is determined by the ID[1:0]# input pins which are reflected in the

Extended Audio ID

(Index 28h) register and the

Extended Modem ID

(In-

dex 3Ch) register. The SCRA[1:0] bits are listed as the ID[1:0] bits in Slot 0 in the AC ‘97 specification.

5.3.2 Register Address (Slot 1)

Bit 191817161514131211109876543210

R/W# RI6 RI5 RI4 RI3 RI2 RI1 RI0

R/W # Read/Write#. Determines if a read (R/W# = 1) or write (R/W# = 0) operation is requested. For a read

operation, the following Input Fram e will r et urn the regist er index in the

1) and the contents of the register in the

Read-Back Data Port

(Slot 2). A write operation does not return any valid data in the following frame. If the R/W# bit = 0, data must be valid in both the (Slot 1) and the

(Slot 2) during a frame when Slot [1:2] Valid or SCRA[1:0] are set.

RI[6:0] Register index/address. Registers can only be accessed on word boundaries; RI0 must be set to 0.

RI[6:0] must contain valid data during a frame when the Slot 1 Valid or SCRA[1:0] are set.

Read-Back Address Port

(Slot

DS315PP2 17

CS4298

5.3.3 Register Write Data (Slot 2)

Bit 1918 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3210

WD15WD14WD13WD12WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0

WD[15:0] Codec register data for write operations. For read operations, this data is ignored. If R/W# = 0, data must

be valid in both the the Slot [1:2] Valid = 11 or either SCRA[1:0] bit is set. Splitting the register address and the write data across multiple frames is not permitted.

5.3.4 Playback Data (Slots 3-11)

Bit 191817161514131211109876543210

PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PD[19:0] 20-bit PCM playback (2’s compliment) data for the left and right DACs, S/PDIF transmitter, or GPIO

pins. Any PCM data from the Controller less than 20 bits should be left justified in the slot and zeropadded. Table 9 on page 35 lists the definition of each respective slot. The mapping of a given slot is determined by the MD[1:0] bits found in the

5.3.5 GPIO Data (Slot12)

Bit 191817161514131211109876543210

GP[9:0] GPIO Output Date. Output data is transferred to the GPIO pins every frame in Slot 12.

GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0

(Slot 1) and the

AC Mode Control

(Index 5Eh) register

(Slot 2) during a frame when

5.4 AC-Link Audio Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin FROM the CS4298 to the AC ’97 Controller. The data format for the input frame is very similar to the output frame. Figure 9 illustrates the serial port timing.

5.4.1 Serial Data Input Slot Tag Bits (Slot 0)

Bit 1514131211109876543210

Codec Ready

Codec ReadyIndicates the readiness of the CS4298’s AC-link and Control and Status registers. Immediately after a

Slot 1 Valid Tag

Slot 2 Valid Tag

Slot [3:11] Valid Tag

Slot 12 Valid Tag

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 1 1

Valid

Slot 12

Valid

Cold Reset this bit will be clear. Once the CS4298 ’ s clock s and volt ages are stable, this bit will be set. Until the Codec Ready bit is set, no AC-link transactions should be attempted by the Controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog function. Those must be checked in the

2Ah)

, and

Ext’d Modem Ctrl/Stat (Index 3Eh)

Power Down Control/Status

registers by the Controller before any access is made to

(Index 26h),

Ext’d Audio Ctrl/Stat (Index

the mixer registers. Any accesses to the Codec while Codec Ready is clear is ignored.

Indicates Slot 1 contains a valid read back address.

Indicates Slot 2 contains valid register read data.

Indicates Slot [3:11] contains valid capture data from the Codec’s ADC.

Indicates Slot 12 contains valid read data of the

GPIO Pin Status Register

(Index 54h).

18 DS315PP2

CS4298

5.4.2 Read-Back Address Port (Slot 1)

Bit 1918171615141312111098765 43210

RI6 RI5 RI4 RI3 RI2 RI1 RI0

RI[6:0] Register index. The Read-Back Address Port echoes the AC ’97 Register address when a register read

has been requested in the previous frame. The Codec will only echo the register index for a read access. Write acces s e s w ill no t re tur n v a lid d ata in Slot 1.

5.4.3 Read-Back Data Port (Slot 2)

Bit 191817161514131211109876543210

RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

RD[15:0] 16-bit register value. The Read-Back Data Port contains the register data requested by the Controller

from the previous read request. All read requests will return the read address in the

Port

(Slot 1) and the register data in the

Read-Back Data Port

(Slot 2) on the following serial data frame.

5.4.4 PCM Capture Data (Slot 3-11)

Bit 191817161514131211109876543210

CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0

CD[17:0] 18-bit PCM (2’s compliment) data. The mapping of a given slot to an ADC is determined by the state of

the MD[1:0] bits found in the

AC Mode Control

(Index 5Eh) register.

Read-Back Address

5.4.5 GPIO Pin Status (Slot 12)

Bit 191817161514131211109876543210

GI9 GI8 GI7 GI6 GI5 GI4 GI3 GI2 GI1 GI0 IRQ

GI[9:0] Status of the GPIO[9:0] pin. IRQ Set when the GPIO generates a wake up or interrupt cycle. See

GPIO Pin Wake Up Mask (Index 52h)

The capture data in Slot [3:12] will only be valid when the respective slot valid bit is set in Slot 0.

DS315PP2 19

5.5 AC ’97 Reset Modes

Three methods of resetting the CS4298, as defined in the AC ’97 Specification, are supported: Cold

AC ’97 Reset, Warm AC ’ 97 R ese t, and AC ’97 Reg is ter Re se t. A Cold AC ’97 Reset is required to restart the AC-link when bit PR5 is set in the Power Down Control/Status (Index 26h) register.

5.5.1 Cold AC ‘97 Reset

A Cold Reset is performed by asserting R ESE T# in accordanc e with the minimum timing specifications in the Serial Port Timing section. Once de-asse rted, all of the C odec’s re gisters will be reset to

their default power-on states and the B IT_CLK clock and SDATA_IN signals will be reactivated. The timing of power-up/reset events is discussed in detail in the Power Management section.

5.5.2 Warm AC ’97 Reset

The CS4298 may also be reactivated whe n the AC-link is powered down (refer to the PR4 bit description in the Power Management section) by a Warm Reset. A Warm Reset allows the AC-link to

be reactivated without losing information in the Codec’s registers. Warm Reset is initiated when the SYNC signal is driven high for at least 1 µs and then driven low in the absence of the BIT_CLK clock signal. The BIT_CLK clock will not restart until at least 2 normal BIT_CLK clock periods (± 162.8 ns) after the SYNC signal is de-asserted.

CS4298

5.5.3 AC ’97 Register Reset

The third reset mode provides a register reset to the CS4298. This is available only when the CS4298’s AC-link is active and the Codec Ready bit is set. The audio and modem subsections may

be reset independently. Any write to Reset (Index 00h) register will reset the audio subsection while any write to Ext’d Modem Ctrl/Stat (Index 3Eh) register will reset the modem subsection. See the

respective register descriptions for additional information.

5.6 AC-Link Protocol Violation - Loss of SYNC

The CS4298 is designed to handle SYNC protocol violations. The following are situations where the SYNC protocol has been violated:

• The SYNC signal is not sampled high for exactly 16 BIT_CLK clock cycles at the start of an audio frame.

• The SYNC signal is not sampled high on the 256th BIT_CLK clock period after the previous SYNC assertion.

• The SYNC signal goes active high before the 256th BIT_CLK clock period after the previous SYNC assertion.

Upon loss of synchronization with the Controller, the Codec will mute all analog outputs and clear the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the Codec will ignore all register reads and writes a nd will discontinue the transmission of PCM capture data.

20 DS315PP2

6. REGISTER INTERFACE

Certain register locations change definition bas ed on the basic operating mode (Mode 0-3) selected by the MD[1:0] bits found in the AC Mode Control (Index 5Eh) register. The reset default is Mode 0.

CS4298

Reg

Num

00h Reset Mode 0 SE4 SE3 SE2 SE1 0 ID8 ID7 ID4 0 0 0 0 1990h 00h Reset Mode 1 00h Reset Mode 2 00h Reset Mode 3 02h Master Volume Mute ML5 ML4 ML3 ML2 ML1 ML0 MR5 MR4 MR3 MR2 MR1 MR0 8000h

04h Alternate Line Out Volume Mute ML5 ML4 ML3 ML2 ML1 ML0 MR5 MR4 MR3 MR2 MR1 MR0 8000h 06h Master Volume Mono Mute MM4 MM3 MM2 MM1 MM0 8000h 0Eh Mic Volume Mute 20dB GN4 GN3 GN2 GN1 GN0 8008h 10h Line In Volume Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h 12h CD Volume Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h 14h Video Volume Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h 16h Aux Volume Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h 18h PCM Out Vol Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h 1Ah Record Select SL2 SL1 SL0 SR2 SR1 SR0 0000h 1Ch Record Gain Mute GL3 GL2 GL1 GL0 GR3 GR2 GR1 GR0 8000h 1E Record Gain Microphone Mute GR3 GR2 GR1 GR0 8000h 20h General Purpose POP 3D MS LPBK 0000h 22h 3D Control S3 S2 S1 S0 0000h 26h Powerdown Ctrl/S tat PR6 PR5 PR4 PR3 PR2 PR1 PR0 REF ANL DAC ADC 000Fh 28h Ext’d Audio ID Mode 0 ID1 ID0 VRA x000h

28h Ext’d Audio ID Mode 1 ID1 ID0 VRA x000h 28h Ext’d Audio ID Mode 2 ID1 ID0 VRA x000h 28h Ext’d Audio ID Mo de 3 ID1 ID0 LDAC SDAC CDAC VRA x1C0h 2Ah Ext’d Audio Ctrl Mode 0 0000h 2Ah Ext’d Audio Ctrl Mode 1 0000h 2Ah Ext’d Audio Ctrl Mode 2 PRL MAD C 0200h 2Ah Ext’d Audio Ctrl Mode 3 PRK PRJ PRI LDAC SDAC CDAC 01C0h 2Ch PCM Front DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h 2Eh PCM Surround DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h 30h PCM LFE DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h 32h PCM Left/Right ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h 34h MIC ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h 36h Center LFE Volume Mute LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Mute CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 8080h 38h LR Surround Volume Mute LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 Mute RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 8080h 3Ch Ext’d Modem ID Mode 0 ID1 ID0 HSET LIN1 x005h 3Ch Ext’d Modem ID Mode 1 ID1 ID0 LIN2 x003h 3Ch Ext’d Modem ID Mode 2 ID1 ID0 LIN1 x001h 3C Ext’d Modem ID Mode 3 ID1 ID0 x000h

3E 40 Line 1 DAC/ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

42 Line 2 DAC/ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h 44 Handset DAC/ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 S R3 SR2 SR1 SR0 BB80h 46 Line 1 DAC/ADC Level Mute DAC3 DAC2 DAC1 DAC0 Mute ADC3 ADC2 8080h

Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

SE4 SE3 SE2 SE1 0 ID8 ID7 ID4 0 0 0 0 1990h SE4 SE3 SE2 SE1 0 ID8 ID7 ID4 0 0 0 ID0 1991h SE4 SE3 SE2 SE1 0 ID8 ID7 0 0 0 0 0 1980h

Ext’d Modem Stat/Ctrl

Ext’d Modem Stat/Ctr

Ext’d Modem Stat/Ctrl

PRH PRG PRD PRC PRB PRA HDAC HADC DAC1 ADC1 MREF GPIO 00CFh

Mode 0

Mode1

PRH P RD PRC PRB PRA HDAC DAC1 ADC1 MREF GPIO 008Fh

Mode 2

Mode 3

PRF PRE PRD PRC PRB PRA DAC2 ADC2 DAC1 ADC1 MREF GPIO 003Fh

PRG PRC PRB PRA HADC ADC1 MREF GPIO 0047h

Table 1. Mixer Registers

DS315PP2 21

CS4298

Reg

Num

48 Line 2 DAC/ACD Level Mute DAC3 DAC2 DAC1 DAC0 Mute ADC3 ADC2 8080h 4A Handset DAC/ACD Level Mute DAC3 DAC2 DAC1 DAC0 Mute ADC3 ADC2 8080h 4C GPIO Pin Configuration GC9 GC8 GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0 03FFh 4E GPIO Pin Polarity/Type GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 FFFFh 50 GPIO Pin Sticky GS9 GS8 GS7 GS6 GS5 GS4 GS3 GS2 GS1 GS0 0000h 52 GPIO Pin Walk-up Mask GW9 GW8 GW7 GW6 GW5 GW4 GW3 GW2 GW1 GW0 0000h 54 GPIO Pin Status GI9 Gi8 GI7 GI6 GI5 GI4 GI3 GI2 GI1 GI0 xxxxh

Misc. Modem AFE Stat

56 Cirrus Defined Registers:

5A Crystal Revision / Fab 1 1 1 0 0302h 5E Slot Map Register EDM EAM DDM MD1 MD0 0000h 68 S/PDIF Enable SPEN 7Ch Vendor ID1(CR) F7 F6 F5 F4 F3 F4 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4352h 7Eh Vendor ID2(Y-) T7 T6 T5 T4 T3 T2 T1 T0 PID2 PID1 PID0 RID2 RID1 RID0 5923h

Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

Mode 0

Mode 1

Mode 2

Mode 3

V Fs L CC6 CC5 CC4 CC3 CC2 CC1 CC0 Pre

Table 1. Mixer Registers

HSB2 HSB1 HSB0 L1B2 L1B1 L1B 0 0000h

L2B2 L2B1 L2B0 L1B2 L1B1 L1B0 0000h

L1B2 L1B1 L1B0 0000h

0000h

Copy #Audio

Pro

0000h

(cont.)

22 DS315PP2

CS4298

6.1 Register Descriptions

6.1.1 Reset (Index 00h)

Mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 SE4SE3SE2SE1SE00ID8ID700ID40000 1 SE4SE3SE2SE1SE00ID8ID700ID40000 2 SE4 SE3 SE2 SE1 SE0 0 ID8 ID7 0 0 ID4 0 0 0 ID0 3 SE4SE3SE2SE1SE00ID8ID70000000

SE[4:0] 3D Stereo Enhancement Technique.

00110 - Crystal 3D Stereo Enhancement. ID8 set 18-bit ADC resolution. ID7 set 20-bit DAC resolution. ID4 set Headphone out support. (Alternate Line Output) ID1 set Dedicated Mic PCM.

Read-only dataMode 0,1 1990h

Mode 2 1991h

Mode 3 1980h

Any write to this register causes the audio control registers (Index 02h - 38h) and the Crystal specific registe rs (Index 5Eh - 68h) to be reset forcing them to their default state. The mode control bits MD[1:0] of the AC Mode Control (Index 5Eh) register are also cleared forcing the Codec to Mode 0 configuration. Reads return configuration information about the audio Codec

6.1.2 Master Volume (Index 02h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute ML5 ML4 ML3 ML2 ML1 ML0 MR5 MR4 MR3 MR2 MR1 MR0

Mute Master mute for the LINE_OUT_L and the LINE_OUT_R output signals. ML[5:0] Master Volume control for LINE_OUT_L pin. Least significant bit represents -1.5 dB with 00000 = 0 dB.

The total range is 0 dB to -94.5 dB. MR[5:0] Master Volume control for LINE_OUT_R pin. Least significant bit represents -1.5 dB with 00000 = 0 dB.

The total range is 0 dB to -94.5 dB. Default 8000h, corresponding to 0 dB attenuation and mute on.

In Mode 3 the LINE_OUT volume is controlled by the Left Right Surround (Index 38h) register in place of Master Volume.

DS315PP2 23

CS4298

6.1.3 Alternate Volume (Index 04h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute ML5 ML4 ML3 ML2 ML1 ML0 MR5 MR4 MR3 MR2 MR1 MR0

Mute Master mute for the ALT_LINE_OUT_L and the ALT_LINE_OUT_R output signals. ML[5:0] Master Volume control for ALT_LINE_OUT_L pin. Least significant bit represents -1.5 dB with 00000 =

0 dB. The total range is 0 dB to -94.5 dB.

MR[5:0] Master Volume control for ALT_LINE_OUT_R pin. Least significant bit represents -1.5 dB with 00000 =

0 dB. The total range is 0 dB to -94.5 dB.

Default 8000h, corresponding to 0 dB attenuation and mute on.

In Mode 3 the ALT_LINE_OUT volume is controlled by the LFE/CNT Volume (Index 36h) registe r in place of Alternate Volume..

ML[5:0]/MR[5:0]/MM[5:0]

Write

000000 000000 0 dB 000001 000001 -1.5 dB

…… ...

111111 111111 -94.5 dB

Table 2. Alternate Line-Out and Master Mono Attenuation

ML[5:0]/MR[5:0]/MM[5:0

Read Gain Level

6.1.4 Microphone Volume (Index 0Eh)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute 20dB GN4 GN3 GN2 GN1 GN0

Mute When set, mutes MIC1/MIC2 signal. GN[4:0] MIC1/MIC2 Volume Control. Least significant bit represents 1.5 dB with 01000 = 0 dB. The total range

is 12 dB to -34.5 dB. 20dB Enables 20 dB microphone gain block. Default 8008h, 0 dB attenuation and Mute set.

This register controls the gain level of the Microphone input source to the Input Mixer. It also controls the +20 dB gain block which connects to the input volume control and to the Input Record Mux. The selection of MIC1 or MIC2 input pins is controlled by the MS bit in th e General Purpose (Index 20h) register. The gain mapping for this register is shown in Table 3.

GN4 - GN0 Gain Level Mic Gain with 20dB = 1

00000 +12.0 dB +32.0 dB 00001 +10.5 dB 30.5 dB

… … ...

00111 +1.5 dB 21.5 dB 01000 0.0 dB 20.0 dB 01001 -1.5 dB 18. 5 dB

… … ...

11111 -34.5 dB -14.5 dB

Table 3. Analog Mixer Input Gain Values

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CS4298

6.1.5 Stereo Analog Mixer Input Gain (Index’s 10h - 18h)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0

Mute When set mutes the respective input. Setting this bit mutes both right and left inputs. GL[4:0] Left Volume Control. Least significant bit represents 1.5 dB with 01000 = 0 dB. The total range is 12 dB

to -34.5 dB. See Table 3.

GR[4:0] Right Volume Control. Least significant bit represents 1.5 dB with 01000 = 0 dB. The total range is 12

dB to -34.5 dB. See Table 3.

Default 8808h, 0 dB gain with Mute enabled.

These registers control the gain levels of the analog input sources to the Input Mixer. The analog inputs associated with registers 10h-18h are found in Table 4.

10h Line IN Volume 12h CD Volume 14h Video Volume 16h Aux Volume 18h PCM Out Volume

Table 4. Stereo Volume Register Index

6.1.6 Input Mux Select (Index 1Ah)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SL2 SL1 SL0 SR2 SR1 SR0

SL[2:0] Left Channel ADC input source select. SR[2:0] Right Channel ADC input source select. Default 0000h, MIC inputs selected for both channels.

When capturing PCM data, this register controls the input MUX for the ADCs. Table 5 below lists the possible values for each input.

Sx2 - Sx0 Record Source

0MIC 1 CD Input 2 Video Input 3 AUX Input 4 Line Input 5 Stereo Mix 6 Mono Mix 7 Not Available

Table 5. Input Mux Selection

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CS4298

6.1.7 Record Gain (Index 1Ch)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute GL3 GL2 GL1 GL0 GR3 GR2 GR1 GR0

Mute When set, mutes the input to the ADCs. GL[3:0] Left ADC gain. Least significant bit represents +1.5 dB with 0000 = 0 dB.

The total range is 0 dB to +22.5 dB.

GR[3:0] Right ADC gain. Least significant bit represents +1.5 dB with 0000 = 0 dB.

The total range is 0 dB to +22.5 dB.

Default 8000h, 0 dB gain with Mute on.

6.1.8 Record Gain Microphone (Index 1Eh)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute GM3 GM2 GM1 GM0

Mute When set, mutes the input to MADC2. GM[3:0] Dedicated Microphone gain. Least significant bit represents +1.5 dB with 0000 = 0 dB.

The total range is 0 dB to +22.5 dB.

Default 8000h, 0 dB gain with Mute on.

This register is only available in Mode 2.

6.1.9 General Purpose (Index 20h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

POP 3D MS LPBK

POP PCM Output Path. By default, the PCM output is mixed prior to the 3D enhancement. When set, the

PCM output is mixed after the 3D enhancement. 3D 3D Enable. If set, enables the CrystalClear 3D stereo enhancement. MS Microphone Select. Determines which of the two MIC inputs are passed to the mixer. When set, MIC2

input is selected; when clear MIC1 is selected. LPBK Loopback. If set, enables Analog ADC/DAC Loopback Mode. Default 0000h.

6.1.10 3D Control (Index 22h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

S3 S2 S1 S0

S[3:0] Spacial Enhancement Depth. Spacial Enhancem ent is enabled by the 3D bit in the

(Index 20h) register.

0000 - No spacial enhancement.

1111 - Full spacial enhancement. Default 0000h, no spacial enhancement added.

General Purpose

The Spacial Enhancements is not availa ble on the ALT_LINE output when the codec is in Mode 3 or EAM is set. See the AC Mode Control (Index 5Eh) register for more detail.

26 DS315PP2

CS4298

6.1.11 Power Down Control/Status (Index 26h)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

PR6 PR5 PR4 PR3 PR2 PR1 PR0 REF ANL DAC ADC

PR6 When set, the alternate line-out buffer is powered down. PR5 When set, the internal master clock is disabled. The only way to recover from setting this bit is through

a cold AC ‘97 reset (driving the RESET# signal active).

PR4 When set, the AC link is powered down. The AC link can be restarted through a warm AC ‘97 reset using

the SYNC signal, or a cold AC ‘97 reset using the RESET# signal (the primary codec only).

PR3 When set, the analog mixer and voltage reference are powered down. When clearing this bit, the ANL,

ADC, and DAC bits should be checked before writing any mixer registers. Because the reference voltage is shared with the modem subsection, it will not power down unless the PRB bit is also set in the

Ext’d Modem Stat/Ctrl

PR2 When set, the analog mixer is powered down (the voltage reference is still active). When clearing this

bit, the ANL bit should be checked before writing any mixer registers.

PR1 When set, the DACs are powered down. When clearing this bit, the DAC bit should be checked before

sending any data to the DACs.

PR0 When set, the ADCs and the ADC input muxes are powered down. When clearing this bit, no valid data

will be sent down the AC link until the ADC bit goes high. REF Voltage Reference Ready Status. When set, indicates the voltage reference is at a nominal level. ANL Analog Ready Status. When set, the analog output mixe r, input multiplexer, and volume controls are

ready. When clear, no volume control registers should be written. DAC DAC Ready Status. When set, the DACs are ready to receive data across the AC link. When clear, the

DACs will not accept any valid data. ADC ADC Ready Status. When set, the ADCs are ready to send data across the AC link. When clear, no data

will be sent to the Controller. Default 0000h, all blocks are powered on. The lower four bits will eventually change as the Codec finishes an

initialization and calibration sequence.

The PR[6:0] are power-down control for different sections of the Codec. The REF, ANL, DAC, and ADC bits are status bits which, when set, indicate that a particular section of the Codec is ready. After the Controller receives the Codec Ready bit in Slot 0, these status bits must be checked before writing to any mixer registers.

(Index 3Eh) register.

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CS4298

6.1.12 Extended Audio ID (Index 28h)

Mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0ID1ID0 VRA 1ID1ID0 VRA 2ID1ID0 VRA 3 ID1 ID0 LDAC SDAC CDAC VRA

ID[1:0] Codec configuration ID. Primary is 00; Secondary is 01,10,or 11. This is a reflection of the ID[1:0]# con-

figuration pins. The state of the ID# pins are determined at power-up and are the inverse of the ID bits

in this register. LDAC PCM LFA DAC. Indicates a LFE DAC is supported. SDAC PCM Surround DA C. Indicates a Surround DAC is supported. CDAC PCM Center DAC. Indicates a Center DAC is supported. VRA Variable Rate Audio. This bit is clear indicating variable sample rates are not supported.

Read-only data Mode 0,1,2 x000h. Where x is determined by the state of ID[1:0] input pins.

Mode 3 x1C0h.

6.1.13 Extended Audio Status / Control (Index 2Ah)

Mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 2 3

CDAC PCM Center DAC Ready. When set, the Center DAC is ready. LDAC PCM LFE DAC Ready. When set, the LFE DAC is ready. SDAC PCM Surround DAC Ready. When set, the Surround DACs are ready. MADC MIC ADC Ready. When Set, the dedicated Microphone ADC is ready. PRI PCM Center DAC Disable. When set, the Center DAC is disabled. PRJ PCM Surround DAC Disable. When set, the Surround DAC is disabled. PRK P CM LFE DAC Disable. When set, the LFE DAC is disabled. PRL Dedicated Microphone ADC D isable. When set, the MIC ADC is disabled.

000000000 000000000 PRL0000MDAC000 0 PRK PRJ PRI 0 0 LDAC SDAC CDAC

Default Mode 0,1 0000h

Mode 2 0200h

Mode 3 01C0h

CDAC, LDAC, SDAC, and MADC are read only bits.

28 DS315PP2

CS4298

6.1.14 PCM Front DAC Rate (Index 2Ch)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR[15:0] Front DAC Sample Rate.

Default Read-only value BB80h, indicating 48 kHz sample rate.

6.1.15 PCM Surround DAC Rate (Index 2Eh)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR[15:0] Surround DAC Sample Rate.

Default Read-only value BB80h, indicating 48 kHz sample rate.

6.1.16 PCM LFE DAC Rate (Index 30h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR[15:0] LFE DAC Sample Rate.

Default Read-only value BB80h, indicating 48 kHz sample rate.

6.1.17 PCM LR ADC Rate (Index 32h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR[15:0] LR ADC Sample Rate. Default Read-only value BB80h, indicating 48 kHz sample rate.

6.1.18 PCM MIC ADC Rate (Index 34h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR[15:0] MIC ADC Sample Rate.

Default Read-only value BB80h, indicating 48 kHz sample rate.

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CS4298

6.1.19 Center LFE Volume (Index 36h)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Mute CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

LFE[5:0] LFE Volume. Lea st significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to -

94.5 dB.

CNT[5:0] Cent er Volume .Lea st significant bit represents -1.5 d B with 00000 = 0 dB. The total range is 0 dB to -

94.5 dB.

Default 8080h, indicating mute with 0 dB attenuation.

LFE[5:0]/LSR[5:0]

CNT[5:0]/RSR[5:0]

Write

LFE[5:0]/LSR[5:0]

CNT[5:0]/RSR[5:0]

Read

Gain L evel

000000 000000 0 dB 000001 000001 -1.5 dB

…… ...

111111 111111 -94.5 dB

Table 6. 6 Channel Volume Attenuation

6.1.20 LR Surround Volume (Index 38h)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 Mute RSR5 RSR4 RSR3 RSR2 RSR1 RSR0

LSR[5:0] Left Surround Volume. Least significant bit represents -1.5 d B with 00000 = 0 dB. The total range is 0

dB to -94.5 dB. RSR[5:0] Right Surround Volume. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0

dB to -94.5 dB. Default 8080h, indicating 0 dB attenuation.

6.1.21 Extended Modem ID (Index 3Ch)

Mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ID1 ID0 HSET

ID1 ID0 LIN2

ID1 ID0

LIN1

HSET Handset . Indicates handset ADC/DAC is supported. LIN1 Line 1. When set, indicates 1st line is supported. LIN2 Line 2. When set, indicates 2nd line is supported. ID[1:0] Codec configuration ID. Primary is 00; Secondary is 01,10,or 11. This is a reflection of the configuration

pins. The state of the ID# pins are determined at power-up and are the inverse of the ID bits in this reg-

ister. Default Mode 0 x005h

Mode 1 x003h

Mode 2 x001h

Mode 3 x000h Where x is determined by the state of ID[1:0] input pins.

The Extended Modem ID is a read/write register that identifies the Codec ’s modem capabilities. Thi s register reports the features available based on the basic operating mode determined by MD[1:0] of AC Mode (Index 5Eh) register. Writing any value to this location issues a reset to the modem registers (Index 3Ch-56h). Audio registers are not reset by a write to this location.

NOTE: All GPIO registers (Index 46h-54h) are reset by any write to this location.

30 DS315PP2

CS4298

6.1.22 Extended Modem ID (Index 3Eh)

Mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

PRH PRG PRD PRC PRB PRA HDAC HADC DAC1 ADC1 MREF GPIO

0 1

PRH PRD PRC PRB PRA HDAC DAC1 ADC1 MREF GPIO

2 3

PRG PRC PRB PRA HADC ADC1 MREF GPIO

PRH Handset DAC. When set powers down the Handset DAC. PRG H andset ADC. When set powe rs down the Handset ADC. PRF Line 2 DAC. When set powers down the Line 2 DAC. PRE Line 2 ADC. When set powers down the Line 2 ADC. PRD Line 1 DAC. When set powers down the Line 1 DAC. PRC Line 1 ADC. When set powers down the Line 1 ADC. PRB Modem Reference. When set powers down the modem reference. The modem and audio share a com-

mon reference. The reference will not power down unless PR3 of the register is also set.

PRA GPIO. When set the GPIO pins are tri-state and powered down. Slot 12 is marked invalid if the AC-link

is active. HDAC Handset DAC. When set indicates the Handset DAC is ready. HADC Handset ADC. When set indicates the Handset ADC is ready. DAC2 Line 2 DAC. When set indicates the Line 2 DAC is ready. ADC2 Line 2 ADC. When set indicates the Line 2 ADC is ready. DAC1 Line 1 DAC. When set indicates the Line 1 DAC is ready. ADC1 Line 1 ADC. When set indicates the Line 1 ADC is ready. MREF Modem Reference. When set indicates the modem reference is ready. GPIO GPIO. When set the GPIO pins are ready. Slot 12 is marked valid.

PRF PRE PRD PRC PRB PRA DAC2 ADC2 DAC1 ADC1 MREF GPIO

Power Down Ctrl/Stat (Index 26h)

Default Mode 0 x0CFh

Mode 1 x03Fh

Mode 2 x08Fh

Mode 3 x047h Where x is determined by the state of ID[1:0] input pins.

PR[A:H] are read/wr ite bits that provide power management of the modem AFE subsection. All remaining bits are read/only status indicating modem subsystems are ready for operation. After reset or issuing a change to the MD [1:0] of AC Mode (Index 5Eh) r egister, the r espective status bi ts for that mode will be clear until the subsystem becomes ready.

6.1.23 Line 1 DAC/ADC Rate (Index 40h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR[15:0] Line 1 DAC/ADC Sample Rate. Default Read-only value BB80h, indicating 48 kHz sample rate.

6.1.24 Line 2 DAC/ADC Rate (Index 42h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR[15:0] Line 2 DAC/ADC Sample Rate. Default Read-only value BB80h, indicating 48 kHz sample rate.

DS315PP2 31

CS4298

6.1.25 Handset DAC/ADC Rate (Index 44h)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

SR[15:0] Handset DAC/ADC Sample Rate. Default Read-only value BB80h, indicating 48 kHz sample rate.

6.1.26 Line 1 DAC/ADC Level (Index 46h)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute DAC3 DAC2 DAC1 DAC0 Mute ADC3 ADC2

Mute[D15] Mute. Mutes the input of Line 1 DAC. Mute[D7] Mute. Mutes the output of Line 1 ADC. DAC[3:0] Line 1 DAC attenuation. Least significant bit represents 1.5 dB with 00000 = 0 dB. The total range is 0

dB to -22.5 dB. ADC[3:2] Line 1 ADC gain. Least significant bit represents 6 dB with 00 = 0 dB. The total range is 0 dB to +18 dB. Default 8080h indicating mute with 0 dB attenuation or gain.

When EAM of the AC Mode Control (Index 5Eh) is s et, the L ine 1 DAC attenuation is controlled by ML[4:0] of the Alternate Volume (Index 04h) register.

6.1.27 Line 2 DAC/ADC Level (Index 48h)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute DAC3 DAC2 DAC1 DAC0 Mute ADC3 ADC2

Mute[D15] Mute. Mutes the input of Line 2 DAC. Mute[D7] Mute. Mutes the output of Line 2 ADC. DAC[3:0] Line 2 DAC attenuation. Least significant bit represents 1.5 dB with 00000 = 0 dB. The total range is 0

dB to -22.5 dB. ADC[3:2] Line 2 ADC gain. Least significant bit represents 6 dB with 00 = 0 dB. The total range is 0 dB to +18 dB. Default 8080h indicating mute with 0 dB attenuation or gain.

When EAM of the AC Mode Control (Index 5Eh) is s et, the L ine 2 DAC attenuation is controlled by MR[4:0] of the Alternate Volume (Index 04h) register.

6.1.28 Handset DAC/ADC Level (Index 4Ah)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mute DAC3 DAC2 DAC1 DAC0 Mute ADC3 ADC2

Mute[D15] Mute. Mutes the input of Handset DAC. Mute[D7] Mute. Mutes the output of Handset ADC. DAC[3:0] Handset1 DAC attenuation. Least significant bit represents 1.5 dB with 00000 = 0 dB. The total range

is 0 dB to -22 dB. ADC[3:2] Handset ADC gain. Least significant bit represents 6 dB with 00 = 0 dB. The total range is 0 dB to

+18 dB. Default 8080h indicating mute with 0 dB attenuation or gain.

32 DS315PP2

CS4298

6.1.29 GPIO Pin Configuration (Index 4Ch)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

000000GC9GC8GC7GC6GC5GC4GC3GC2GC1GC0

GC[9:0] GPIO Pin Configuration. When set defines the corresponding GPIO pin as an input Default 03FFh

After a cold reset, power up, or modem regis ter reset (see Extended Modem ID (Index 3Ch)) all GPIO pins are configured as inputs.

6.1.30 GPIO Pin Polarity/Type Configuration (Index 4Eh)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

111111GP9GP8GP7GP6GP5GP4GP3GP2GP1GP0

GP[9:0] GPIO Pin Configuration. The definition of GP[9:0] changes based on the pin defined as an input or an

output by GC[9:0] of

Defau lt FFFFh

When the GPIO pin is def ined a s an input, its status is reported in the GPIO Pin Status ( Inde x 54h) register as well as Slot 12.

GCx GPx Function

0 0 Output CMOS drive 0 1 Output Open drain 1 0 Input Active Low 1 1 In put Active High (default)

GPIO Pin Configuration (Index 4Ch).

Table 7. GPIO Input/Output Configuration

6.1.31 GPIO Pin Sticky (Index 50h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

GS9 GS8 GS7 GS6 GS5 GS4 GS3 GS2 G S1 GS0

GS[9:0] GPIO Pin Sticky. If set, the GPIO pin input is latched. Default 0000h

If a GPIO is defined as “sticky” the input requires a transition of the GPIO input pin to set the corresponding bit in Slot 12 and the GPIO Pin Status (Index 54h) register. When “sticky” is set the corresponding bit in GPIO Pin Polarity/Type Configuration (Index 4Ah) register determines which edge of the GPIO pin will set GI[x]. If GP[x] is set, a low to high transition sets the GI[x] bit. A high to low transition sets GI[x] if GP[x] is clear. Once set, writing a 0 to GI[x] will clear the “sticky” input.

DS315PP2 33

CS4298

6.1.32 GPIO Pin Wakeup Mask (Index 4Ch)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

GW9 GW8 GW7 GW6 GW5 GW4 GW3 GW2 GW1 GW0

GS[9:0] Wake up mask. If set, allow the GPIO input to generate AC-LINK wake up protocol. Default 0000h

The CS4298 has the ability to generate a “wake up” cycle by a transition of a GPIO pin when the AC-Link has been powered down. If a mask bit is set, a one being set in the corresponding GPIO Pin Status (Index 54h) will initiate a wake up interrupt. Bit 0 of SDATA_IN Slot 12 will be set indicating a GPIO interrupt. GPIO pins must be defined as “input”, “sticky”, and the mask set to allow a GPIO interrupt. The GPIO interrupt is cleared by writing a 0 to the respective status bit in GPIO Pin Status

(Index 54h) register.

6.1.33 GPIO Pin Status (Index 54h)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

GI9 GI8 GI7 GI6 GI5 GI4 GI3 GI2 GI1 GI0

GI[9:0] GPIO pin status. Reflects the state of all GPIO pins either input or output. If the GPIO pin is defined as

an output, the respective bit reflects the state of SDATA_OUT Slot 12. If the GPIO pin is defined as an

input, the register is reflected in SDATA_IN Slot 12. GPIO output pins cannot be accessed by Slot 1,2

6.1.34 Misc. Modem AFE Status (Index 56h)

Mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 2 3

HSB[2:0] Handset Loopback. L2B[2:0] Line 2 Loopback. L1B[2:0] Line 1 Loopback.

Default 0000h.

Loop Back Mode

HSB[2:0], L2B[2:0], L1B[2:0]

000 Disabled 001 Digital Loop Back 010 Local Analog Loop Back 011 DAC to ADC 1-Bit data Loop Back 100 Remote Analog Loop Back 101 AC-Link Loop Back

110-111 Not Used

HSB2 HSB1 HSB0 L1B2 L1B1

L2B2 L2B1 L2B0 L1B2 L1B1

L1B2 L1B1

Function

Table 8. Misc. Modem Configuration

L1B0 L1B0 L1B0

34 DS315PP2

CS4298

6.1.35 AC Mode Control (Index 5Eh)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

EDM EAM DDM MD1 MD0

DDM DAC Direct Mode. This bit controls the source to the line and alternate line output drivers. When set, the

Left and Right DAC directly drive the line and alternate line outputs by bypassing the audio mixer. When clear, the audio mixer is the source for the line and alternate line outputs.

EAM Extended Audio Mode. When set the output of MDAC2 and MDAC1 are mapped to the ALT_LINE OUT-

PUT. The MDAC volumes are set by the

EDM Extended Docking Mode. When set the output of the analog input mixer is routed to the MADC1 and

MADC2 inputs. This allows any analog input mix to be digitized and routed to a second AC ‘97 codec or allows the host controller to add effects processing to analog sources.

MD[1:0] Mode. Sets basic operating mode for the codec. This effects the mapping of the ADCs and DACs to AC-

LINK Slot locations. See the Mode of Operation subsection for additional detail. Table XXX below details the Slot mapping.

Default 0000h

Alternate Line Volume (Index 04h)

Mode Definition

0 Basic

1 2 Line

2 Speakerphone

Extended 4

Channel

Audio DAC1

Left Right Left Right Line 1 Handset Line 1 Handset

343451151112

Left Right Left Right Line 1 Line 2 Line 1 Line 2

343451051012

Left Right Left Right Line 1 Handset Line 1 Mi c

34345115 612

Surrnd

Left

78346 9 51112

Audio

DAC2

Surrnd

Right

Audio ADC1

Left Right Center LFE Line 1 Handset

Audio ADC2

Modem

DAC1

Modem

DAC2

Modem

ADC1

Modem

ADC2

GPIO

Table 9. Slot Assignments

6.1.36 S/PDIF Control (Index 68h)

D15 D14 D13 D12 D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SPEN V 0 0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 Pre Copy #Audio 0

SPEN S/PDIF Enable. When set, Slot 6 and Slot 9 are mapped to the SPDIF_OUT pin. When in Mode 3 and

SPEN set, data is not passed to Modem DAC1 and Modem DAC2.

V Validity Bit. When set, this bit notifies the S/PDIF receiver that the subframe data is not suitable for con-

version. L Generation Level . CC[6:0] Category Code. Pre Premphasis. If set, filter premphasis is 50/15 µs. If clear, premphasis is none. Copy Copyright. When clear, copyright is asserted. If clear, copyright is not asserted. #Audio #Audio valid. When clear, the data routed to the S/PDIF transmitter contains valid PCM data. For trans-

mitting all other compressed data formats, the #Audio bit must be set. Default 0000h.

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CS4298

6.1.37 Vendor ID1 (Index 7Ch)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0

F[7:0] First Character of Vendor ID.

43h - ASCII ‘C’ character.

S[7:0] Second Character of Vendor ID.

52h - ASCII ‘R’ character.

Read-only data4352h.

6.1.38 Vendor ID2 (Index 7Eh)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

T7 T6 T5 T4 T3 T2 T1 T0 PID2 PID1 PID0 RID2 RI D1 RID0

T[7:0] Third Character of Vendor ID.

59h - ASCII ‘Y’ character.

PID[3:0] Part ID.

See Table10 below.

RID[2:0] Revision.

See Table10 below.

Read-only data5923h.

The two Vendor ID registers provide a means to determine the manufacturer of the AC ’97 Codec. The first three bytes of the ID registers contain the ASCII code for the first 3 letters of Crystal (CRY). The final byte of the Vendor ID2 register is divided into a Part ID field and a Revision field.Table 10 lists the Part ID’s defined to date.

PID3-PID0 Part Name

000 CS4297 001 CS4297A 010 CS4294 Rev C * 010 CS4298 011 CS4299

* D3 set

Table 10. Reg. 7Eh Defined Part ID’s

36 DS315PP2

7. ANALOG HARDWARE DESCRIPTION

The analog hardware consist of a four line-level s ter eo inputs, two selectable mono microphone inputs, two mono inputs, a mono output, and dual, independent stereo line outputs. This section describes the analog hardware needed to interface with these pins.

7.1 Line-Level Inputs

The analog inputs consist of four stereo analog inputs and four mono inputs. As shown in Figure 8, the input to the ADCs comes from the Input Mux which selects one of the following: Phone (Mono), Aux, Video, CD, Mic1 or Mic2 (Mono), Line, Stereo Output Mix, or the Mono Output Mix (Mono). Unused analog inputs should be connected together and then connected through a capacitor to analog ground or tied to the Vrefout line directly.

The analog input mixer is designed to accommodate five stereo inputs and one mono input. These inputs are: a stereo line-level input (LINE), a mono microphone input (MIC), a stereo CD-ROM input (CD), a stereo auxiliary line-level input (AUX), and the PCM output from the DAC s. Each of the stereo inputs has separate volume controls for each channel and one mute control for each left/right pair. The mono microphone input has one mute and one volume control.

The inputs to the output mixer are: the input mixer output, the PC Beep mono input, and the Phone mono input.

CS4298

All analog inputs to the CS4298, including CD_GND, should be capacitively coupled to the input pins.

Since many analog levels can be as large as 2 V attenuate the analog input by 6 dB (to 1 V

RMS)

, the circuit shown in Figure 10 can be used to

RMS

which is the maximum voltage allowed for all the

stereo line-level inputs: LINE_IN, AUX_IN, and VIDEO_IN. The CD line-level inputs have an extra pin, CD_GND, which provides a pseudo-differential input for

both CD_L and CD_R. This pin takes the common-mode noise out of the CD inputs when connected to the ground coming from the CD analog source. Connecting the CD pins as shown in Figure 11 provides extra attenuation of common mode noise coming from the C DROM drive, thereby producing a higher quality signal. One percent resistors are recommended since the better the resistors match, the better the common-mode attenuation of unwanted signals. If CD is not used, the inputs should be connected through AC capacitors to analog ground or connected to Vrefout.

6.8 k

Ω

6.8 k

1.0 µF

1.0

Ω

6.8 k

Ω

6.8 k

(All resistors 1%)

Ω

3.4 k

Ω

6.8 k

Ω

3.4 k

1.0 µF

2.0 µF

Ω

1.0

6.8 k

Ω

CD_L

CD_GND

CD_R

Figure 10. Line Inputs Figure 11. Differential CDROM In

DS315PP2 37

7.2 Mic rophone Level Inputs

The microphone level inputs, MIC1 and M IC2, include a selectable -34.5 dB to +12 dB gain s tage for interfacing to an external microphone. An additional 20 dB gain block is also available. Figure 12 illustrates a single-ended microphone input buffer circuit that will support lower gain mics. The circuit in Figure 12 supports dynamic mics and phantom-powered mics that use the right channel (ring) of the jack for power..

7.3 Line Level Outputs

The analog output section provides a stereo line-level output and an alternate stereo line-level output. LINE_OUT_L, LINE_OUT_R, ALT_LINE_OUT_L, and ALT_LINE_OUT_R outputs should be capacitively coupled to external circuitry.

The mono output, MONO_OUT, can be used a s either a sum of the left and right output channe ls attenuated by 6 dB to prevent clipping at full scale or the selected MIC_IN signal. The mono out channel can be used to dr ive the PC internal mono s peaker using an appropriate drive c ircuit. This approach allows the traditional PC sounds to be integrated with the rest of the audio system. The mute control is independent of the line outputs allowing the mono channel to mute the speaker without muting the line outputs.

CS4298

Each of the 5 analog outputs, if used in the design, require 680 pF or larger NPO dielectric capacitors between the corresponding pin and AGND. Each analog output is DC biased up to the Vrefout voltage signal reference which is nominally 2.2 V. This requires that the output either be AC coupled to external circuitry (AC load must be greater than 10 kΩ) or DC coupled to a buffer op-amp biased at the Vrefout voltage (see Figure 13 for the recommended headphone op-amp circuit).

+5 VA

U1A

MC33078D

100 k

AGND

Ω

10 µF

6.8 k

47 k

Ω

68 k

Ω

4 3 5 2 1

AGND

2.7 k AGND

0.068 µF

X7R

220 pF 220 pF

CGND

AGND

+5 VA

AGND

220 pF

10 µF

U1B MC33078D

Ω

47 k

AGND

47 k

X7R

Ω

1 µF

MIC1

Figure 12. PC ‘99 Microphone Pre-amplifier

38 DS315PP2

7.4 Consumer IEC-958 Digital Interface (S/PDIF)

The CS4298 supports the industry standard IEC-958 consumer digital interface. Sometimes this standard is referred to as S/PDIF, which refers to an older version of this standard. This output provides an interface, external to the PC, for storing digital CD-ROM) or playing digit al audio from digital speakers. Figure 14 illustrates the circuit necessary for implementation of the IEC-958 consumer interface. The CS4298 is capable of directly driving the voltage divider for the 75 Ω interface. An optional current driver is shown when an increase of the transmission range of the coaxial circuitry is required. An optional fiber optic circuit may be connected directly to the CS4298.

7.5 Miscellaneous Analog Signals

The AFILT1 and AFILT2 pins must have a 1000 pF NPO capacitor (must not be smaller than 390 pF) to analog ground. These capacitors, al ong with an internal resistor, provide a single-pole lowpass filter at the inputs to the ADCs. By placing these filters at the input to the ADCs, low-pass filters at each analog input pin are not necessary.

The REFFLT pin lowers the noise of the internal voltage reference. A 1 µF (must not be greater than 1 µF) and 0.1 µF capacitor to analog ground should be connected with a short, wide trace to this pin. No other connection should be made, as any coupling onto this pin will degrade the analog performance of the Codec. Likewise, digital signals should be kept away from REFFLT for similar reasons.

CS4298

ALT_LINE_OUT_R

ALT_LINE_OUT_L

Vrefout

0.1µF

Y5V

680pF

NPO

AGND

27k

Ω

2 3

680pF

NPO

1.0µF

Y5V

Figure 13. Headphones Driver

22pF NPO

2 3

22pF

NPO

TDA1308

Ω

39k

220µF

ELEC

220µF

ELEC

Ω

1 2

AGND

1/4 WATT

47K

HP_OUT_R

Ω

HP_OUT_L

Ω

DS315PP2 39

The Vrefout pin is typically 2.2 V and provides a common mode signal for single-supply external circuits. Vrefout only supports light DC loads and should be buffered if AC loading is needed. For typical use, a 0.1 µF in parallel with a 1 µF capacitor should be connected to Vrefout.

7.6 Power Supplies

The power supplies providing analog power should be as clean as possible to minimize coupling into the analog section which could degrade analog performance. The pins AVdd1 and AVdd2 supply power to all the analog circuitry on the CS4298. This 5 Volt analog supply should be generated from a voltage regulator (7805 type) connected to a +12 Volt supply. This helps isolate the analog circuitry from noise typically found on +5 V digital supplies which power many digital circuits in a PC environment. A typical voltage regulator circuit f or analog power using an MC78M05CDT is shown in Figure 15.

The digital power pins DVdd1 and DVdd2 should be connected to the same digital supply as the AC

’97 Controller’s AC-Link interface. S ince the digital interface on the CS4298 may operate at either

3.3 V or 5 V, proper connection of these pins will depend on the digital power supply of the AC ’97 Controller. connections (vias). The AC-Link digital interface connection traces should be routed

CS4298

0.1

DGND

SPDIFO

SN75179D

+5 V PCI

VCC

GND

DGND

J-RCA-R4-PCB

374

DGND DGND

1 4

90.9

+5V_PCI

.1µF

DGND

SPDIFO

8.2K

2 1

TOTX-173

DGND

Figure 14. IEC-958 Interface Examples

Y5V

0.1µF

+12VD

ELEC 10µF

MC78M05CDT

GND

OUT

Y5V

0.1µF

+5VA

ELEC 10µF

AGNDDGND

Figure 15. Voltage Regulator

40 DS315PP2

such that digital ground plane lies underneath these s ignals (on the inter nal ground layer) f rom the

AC ’97 Controller continuously to the CS4298.

7.7 Hybrid Interface

Figure 16 indicate s the required components for the secondary side of the hybrid circuity required for the CS4298. The multiple configurations required for the line interface are beyond the scope of this document. Please contact Crystal applications engineering for additional information.

TX+

Rb1

RX+

10 k

R2_1

6650

Rt1 140 1%

Cblock

671-8039

CS4298

Line

Interface

Line

RX-

TX-

Caa

1000 pF

Rb2 10 k

Co_lpf

0.033

R2_2

6650

MIDCOM

Rt2 140 1%

Figure 16. Hybrid Circuit Secondary

DS315PP2 41

8. PIN DESCRIPTIONS

CS4298

FLTI

FLTO GPIO9 GPIO8

GPIO7/TP3 GPIO6/TP2 GPIO5/TP1 GPIO4/TP0

GPIO3 GPIO2 GPIO1 GPIO0 DVdd1

XTL_OUT

XTL_IN

DVss1

SDATA_OUT

BIT_CLK

DVss2

SDATA_IN

DVdd2

SYNC

RESET#

S/PDIF_OUT

BCM#

AUX_L

AUX_R

VIDEO_L

VIDEO_R

CD_L

CD_GND

CD_R

57 58 59 60

61 62

63 64

10 11 12

13 14

15 16 17 18 19 20

22 23 24

FLT3D

AVss5

HRX-

HRX+

AVss4

HTX-

HTX+

AVdd4

AVss3

63 61 59 57 55 53 51 49

2 3 4

5 6

7 8 9

64 62 60 58 56 54 52 50

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 19 21 23 25 27 29 31

18 20 22 24 26 28 30 32

Top View

CS4298-KQ

64-pin TQFP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

MTX-

MTX+

AVdd3

MRX-

MRX+

ID0#

ALT_LINE_OUT_R

ALT_LINE_OUT_L

AVss2

AVdd2

LINE_OUT_R

LINE_OUT_L

ID1#

AFLT2

AFLT1

Vrefout

REFFLT

AVss1

AVdd1

LINE_IN_R

LINE_IN_L

MIC2

MIC1

42 DS315PP2

8.1 g2

Digital I/O Pins

RESET# - AC ’97 Chip Reset, Input

This active low signal is the asynchronous Cold Reset input to the CS4298. The CS4298 must be reset before it can enter normal operating mode. When the PR4 bit of register 26h is set, the

RESET# rising edge will be used as an AC ‘97 2.1 Warm Reset only, preserving register values.

SYNC - AC-link Serial Port Sync pulse, Input

This signal is the serial port timing signal for the AC-link of the CS4298. Its period is the reciprocal of the sample rate of the CS4298, 48 kHz. This signal is generated by the AC ’97 Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the CS4298 is in a PR4 powerdown state and is configured as a primary codec. A series terminating resistor of 47 Ω should be conne cted on this signal close to the device driving the signal.

BIT_CLK - AC-link Serial Port Master Clock, Input/Output

CS4298

This input/output signal controls the master clock timing for the AC-link. In codec primary mode, this signal is an output 12.288 MHz clock signal which is divided down by two from the XTL_IN input clock pin. In codec secondary mode, this signal is an input which controls the AC-link serial interface. In BIT_CLK mode, th is signal generates all internal clocking includi ng the AC-link serial interface timing. A series terminating resistor of 47 Ω should be connected on this signal close to the CS4298 in primary mode or close to the BIT_CLK source if in secondary mode.

SDATA_OUT - AC-link Serial Data Input Stream to AC ‘97, Input

This input signal transmits the control information and digital audio output streams to be sent to the DACs. The data is clocked into the CS4298 on the falling edge of BIT_CLK. A series terminating resistor of 47 Ω should be conne cted on this signal close to the device driving the input.

SDATA_IN - AC-link Serial Data Output Stream from AC ‘97, Output

This output signal transmits the status information and digital audio input streams from the ADCs. The data is clocked out of the CS4298 on the rising edge of BIT_CLK. A series terminating resistor of 47 Ω should be connected on this signal as close to the CS4298 as possible.

XTL_IN - Crystal Input

This pin accepts either a crystal, with the other pin attached to XTL_OUT, or an external CMOS clock. XTL_IN must have a crystal or clock source attached f or proper operation except when operating in BIT_CLK mode. The crystal frequency must be 24.576 MHz and designed for fundamental mode, parallel resonance operation.

DS315PP2 43

XTL_OUT - Crystal Output

This pin is used for a crystal placed between this pin and XLT_IN . If an external clock is used on XTL_IN or the codec is in BIT_CLK mode, this pin must be left floating w ith no traces or components connected to it.

ID1#, ID0# - Codec ID, Inputs

These pins select the codec ID and mode of operation for the CS4298. They ar e sampled after the rising edge of RESET# and not used after. These inputs have internal 100 kΩ pull-ups and should be left floating for a logic 0 or tied to analog ground for a logic 1. The pins utilize inverted logic, so the condition of both pins floating sets the codec to primary mode while any other combination sets the codec to a secondary mode. In primary mode, the codec is always clocked from an external crystal or an external oscillator connected to the XTL_IN and/or XTL_OUT pins with BIT_CLK as an output. In secondary mode, the clocking mechanism is determined by the state of the BCM# pin with BIT_CLK always being an input.

BCM# - BIT_CLK Mode, Input

This pin selects the secondary mode clocking mechanism. BCM# is sampled after the rising edge of RESET# and not used after. In codec secondary mode (ID1# and or ID0# grounded), grounding this input will select BIT_CLK mode. In this mode, BIT_CLK is defined as an input and all internal timing will be derived from the BIT_CLK signal and no connections should be made to XTAL_IN and XTAL_OUT. When BCM# is floating, all timing will be derived from the XTAL_IN pin. In this case, XTAL_IN must be syncronous to BIT_CLK. In primary mode, BCM# must be left floating.

CS4298

S/PDIF_OUT - Sony/Phillips Digital Interface, Output

This pin generates IEC 958 consumer compatible (S/PDIF) digital output from the CS4298 using output slots 6 and 9 when the SPDIF_EN bit in register 68h is set. For use with consumer audio equipment, the output may be used to drive an RS422A compliant interface through an isolation transformer, or a CP-1201 compliant interface through a TOSLINK module. When

S/PDIF_OUT is not being used this output is driven to a logic ‘0’.

GPIO[9:0] - General Purpose Input/Output

These GPIO pins are used to control modem DAAs and other discrete digital functions. When a GPIO pin is configured as an input, it behaves as a Schmitt trigger input with 350 mV of hysteresis at 5 V and 220 mV of hysteresis at 3.3 V. When a GPIO pin in configured as an output, it may function as a normal CMOS output (4 mA drive) or as an open drain output. GPIO pins power up in the high impedance state (tri-state).

44 DS315PP2

8.2 Analog I/O Pins

MIC1 - Analog Mono Source, Input

This analog input is a monophonic source to the analog output mixer. It is intended to be used as a desktop microphone connection to the audio subsystem. This input is MUX selectable to the input mixer with the MIC2 input source. The maximum allowable input is 1 V (sinusoidal). If the 20 dB internal boost is enabled, the maximum allowable input is 100 mV

(sinusoidal). This input is internally biased at the Vrefout voltage reference and

RMS

requires AC coupling to external circuitry. If this input is not used, it should be AC coupled to analog ground.

MIC2 - Analog Mono Source, Input

This analog input is a monophonic source to the analog output mixer. It is intended to be used as an alternate microphone connection to the audio subsystem. This input is MUX selectable to the input mixer with the MIC1 input source. The maximum allowable input is 1 V (sinusoidal). If the 20 dB internal boost is enabled, the maximum allowable input is 100 mV

(sinusoidal).This input is internally biased at the Vrefout voltage reference and

RMS

requires AC coupling to external circuitry. If this input is not used, it should be AC coupled to analog ground.

CS4298

RMS

LINE_IN_L and LINE_IN_R- Analog Line Source, Inputs

These inputs form a stereo input pair to the CS4298. The maximum allowable input is 1V

(sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC

RMS

coupling to external circuitry is required. If these inputs are not used, they should both be connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog ground.

CD_L and CD_R - Analog CD Source, Inputs

These inputs form a stereo input pair to the CS4298. It is intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input is 1 V (sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry is required. If these inputs are not used, they should both be connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog ground.

CD_GND - Analog CD Common Source, Input

This analog input is used to remove common mode noise from Red Book CD audio signals. The impedance on the input signal path should be one half the impedance on the CD_L and CD_R input paths. This pin requires AC coupling to external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC coupled to analog ground.

RMS

DS315PP2 45

VIDEO_L and VIDEO_R - Analog Video Audio Source, Inputs

These inputs form a stereo input pair to the CS4298. It is intended to be used for the audio signal output of a video device. The maximum allowable input is 1 V inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry is required. If these inputs are not used, they should both be connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog gr ound.

AUX_L and AUX_R - Analog Auxiliary Source, Inputs

CS4298

(sinusoidal). These

RMS

These inputs form a stereo input pair to the CS4298. The maximum allowable input is 1 V (sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry is required. If these inputs are not used, they should both be connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog ground.

LINE_OUT_L and LINE_OUT_R - Analog Line Level Outputs

These signals are analog outputs from the stere o output mixer. The full scale output voltage for output is nominally 1 V

and is internally biased at the Vrefout voltage reference. It is

RMS

required to either AC couple these pins to external circuitry or DC couple them to a buffer opamp biased at the Vr efout voltage. These pins need a 680 pF NPO capacitor attached to analog ground.

ALT_LINE_OUT_L and ALT_LINE_OUT_R - Analog Alternate Line Level Outputs

These signals are analog outputs from the stere o output mixer. The full scale output voltage for each output is nominally 1 V

and is internally biased at the Vr efout voltage reference. It is

RMS

required to either AC couple these pins to external circuitry or DC couple them to a buffer opamp biased at the Vr efout voltage. These pins need a 680 pF NPO capacitor attached to analog ground.

8.3 Filter and Reference Pins

RMS

REFFLT - Internal Reference Voltage, Input

This is the voltage reference used internal to the part. A 0.1 µF and a 1 µF (must not be larger than 1 µF) capacitor with short, wide traces must be connected to this pin. No other connections should be made to this pin.

Vrefout - Voltage Reference, Output

All analog inputs and outputs are centered around Vrefout which is nominally 2.2 Volts. This pin may be used to level shift external circuitry, however any external loading should be buffered.

AFLT1 - Left Channel Antialiasing Filter Input

This pin needs a 390 pF NPO capacitor attached to analog ground.

AFLT2 - Right Channel Antialiasing Filter Input

This pin needs a 390 pF NPO capacitor attached to analog ground.

46 DS315PP2

FLTI - 3D Filter Input

A 1000 pF capacitor must be attached betwee n this pin and FLTO if the 3D function is used.

FLTO - 3D Filter Output

A 1000 pF capacitor must be attached betwee n this pin and FLTI if the 3D function is used.

FLT3 D - 3D F ilter

A 0.01 µF capacitor must be attached from this pin to AGND if the 3D function is used.

8.4 Modem/Telephony

MRX+, MRX- - Modem Line Differential Receive, Inputs

This differential input receive pair connects to a 2- to 4-wire hybrid converter or an integrated DAA and is used to sample the analog phone line signal. The maximum full scale differential input is 3.0 Vp-p. These pins may be used in single ended fashion by connecting the input to MRX+ and AC-grounding the MRX- pin, or by tying one of the two inputs to Vrefout to provide DC-biasing.

CS4298

HRX+, HRX- - Handset Differential Rece ive, Inputs

This differential input receive pair connects to a 2- to 4-wire hybrid converter and is used to communicate with the local handset. These input pins may also be used to interface to a second telephone line. The maximum full scale differ ential input is 3.0 Vp-p. These pins may be used in single ended fashion by connecting the input to HRX+ and AC-grounding the HRX- pin, or by tying one of the two inputs to Vrefout to provide DC-biasing.

MTX+, MTX- - Modem Line Di fferential Transmit, Outputs

This differential transmit output pair connects the a 2- to 4-wire hybrid converter or an integrated DAA and is used to transmit over the analog phone line. The maximum full scale differential output is 5.6 Vp-p (MTX+ to MTX-). Each output pin is internally biased at the Vrefout voltage. These pins may be used in single ended fashion by using one leg of the differential output pair. The maximum output for each pin is 2.8 Vp-p or 1.0 Vrms.

HTX+, HTX- - Handset Differential Transmit, Outputs

This differential transmit output pair connects the a 2- to 4-wire hybrid converter or an integrated DAA and is used to transmit over the analog phone line. The maximum full scale differential output is 5.6 Vp-p (HTX+ to HTX-). Each output pin is internally biased at the Vrefout voltage. These pins may be used in single ended fashion by using one leg of the differential output pair. The maximum output for each pin is 2.8 Vp-p or 1.0 Vrms.

DS315PP2 47

8.5 Power Supplies

DVdd1, DVdd2 - Digital Supply Voltage

These pins provide the digital supply voltage for the AC-link section of the CS4298. These pins may be tied to +5 V digital or to +3.3 V digital. The CS4298 and digital controller’s AC-link

should share a common digital supply.

DVss1, DVss2 - Digital Ground

These pins are the digital ground connection for the AC-link section of the CS4298. These pins should be isolated from analog ground currents.

AVdd1, AVdd2, AVdd3, AVdd4 - Analog Supply Voltage

These pins provide the analog supply voltage for the analog and mixed signal sections of the CS4298. These pins must be tied to +5 V analog supply. It is strongly recommended that +5 V be generated from a voltage regulator to ensure proper supply currents and noise immunity from the rest of the sys tem.

AVss1, AVss2, AVs s3, AVss4, AVss5 - Analog Ground

CS4298

These pins are the ground connection for the analog, mixed signal, and substrate sections of the CS4298. These pins should be isolated from digital ground currents.

48 DS315PP2

9. PARAMETER AND TERM DEFINITIONS

AC ’97 Specification

Refers to the Audio Codec ‘97 Component Specification Ver 2.1 published by Intel Corporation [].

AC ’97 Cont roller or Controller

Refers to the control chip which interfaces to the Codec’s AC-link. This has been also called

DC ’97 for Digital Controller ‘97 [].

AC ’97 Regis ters or Codec registers

Refers to the 64-field register map defined in the AC ’ 97 Specification.

ADC

Refers to a single Analog-to-Digital converter in the Codec. “ADCs” refers to the stereo pair of Analog-to-Digital converters.

DAC

CS4298

A single Digital-to-Analog converter in the Codec “DACs” refers to the stereo pair of Digitalto-Analog converters.

SRC

Sample Rate converter. Converts data derived at one sample rate to a differing sample rate.

Codec

Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the Codec is the CS4297A9.

FFT

Fast Fourier Transform.

Resolution

The number of bits in the output words to the DACs, and in the input words to the ADCs.

Differential Nonlinearity

The worst case deviation from the ideal code width. Units in LSB.

dB FS A

dB FS is defined as dB relative to full-scale. The “A” indicates an A weighting filter was used.

DS315PP2 49

Freque nc y Re spon se ( FR)

FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency to maximum frequency inclusive.

Dynamic Range (DR)

DR is the ratio of the RMS full-scale signal level divided by the RMS sum of the noise floor, in the presence of a signal, available at any instant in time (no change in gain settings be tween measurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A.

Total Harmonic Distortion plus Noise (THD+N)

THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level. It is tested using a -3 dB FS input signal and is measured over a 20 Hz to 20 kHz bandwidth with units in dB FS.

Signal to Noise Ratio (SNR)

SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor, in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB.

CS4298

S/PDIF

Sony/Phillips Digital Interface. This interface was established as a means of digitally interconnecting consumer audio equipment. The documentation for S/PDIF has been superseded by the IEC-958 consumer digital interface document.

Interchannel Isolation

The amount of 1 kHz signal present on the output of the grounded AC-coupled line input channel with 1 kHz, 0 dB, signal present on the other line input channel. Units in dB.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage to get an equal code on both channels. For the DACs, the difference in output voltages for each channel when both channel s are fed the same code. Units in dB.

PATHS

A-D: Analog in, through the ADC, onto the serial link. D-A: Serial interface inputs through the DAC to the analog output. A-A: Analog in to Analog out (analog mixer).

10.REFERENCES

Intel, Audio Codec ‘97 Component Specification, Revision 2.1, May 22,1998.

http://developer.intel.com/pc-supp /platform/ac97/

50 DS315PP2

11.PACKAGE DIMENSIONS

64L TQFP PACKAGE DRAWING

CS4298

∝

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A --- 0.063 --- 1. 60

A1 0.002 0.006 0.05 0.15

B 0.007 0.011 0.17 0.27 D 0.461 0.484 11.70 12.30

D1 0.390 0.398 9.90 10.10

E 0.461 0 .48 4 11.70 12.30

E1 0.390 0 .39 8 9.90 10.10

e* 0.016 0.024 0.40 0.60

L 0.018 0.03 0 0.45 0.75

∝

* Nominal pin pitch is 0.50 mm

0.000° 7.000° 0.00° 7.00°

Controlling dimension is mm. JEDEC Designation: MS026

DS315PP2 51

Cirrus Logic CS4298-KQ, CS4298-JQ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

ORDERING INFORMATION

TABLE OF CONTENTS

Contacting Cirrus Logic Support

LIST OF FIGURES

LIST OF TABLES

1. CHARACTERISTICS AND SPECIFICATIONS

AUDIO ANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted:

ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

MODEM CHARACTERISTICS (Analog Transmitter Specifications: T

Modem Analog Transmitter Characteristics

Modem Analog Receiver Characteristics

DIGITAL CHARACTERISTICS (AVss = DVss = 0 V)

DVdd = 3.3V

DVdd = 5.0 V

SERIAL PORT TIMING

RESET# Timing

Clocks

Data Setup and Hold

Misc. Timing Parameters

Figure 1. Power Up Timing

Figure 2. Clocks

Figure 3. Codec Ready from Startup or Fault Condition

Figure 4. Data Setup and Hold

Figure 5. PR4 Powerdown

Figure 6. Test Mode

2. GENERAL DESCRIPTION

2.1 Overview

2.2 Modes of Operation

2.2.1 Mode 0

2.2.2 Mode 1

2.2.3 Mode 2

2.2.4 Mode 3

3. DIGITAL SECTION

3.1 AC-Link

Figure 7. AC-link Connections

3.2 Control registers

4. ANALOG SECTION

4.1 Audio Output Mixer

4.2 Audio Input Mux

4.3 Audio Input Mixer

4.4 Audio Volume Control

Figure 8. Mixer Diagram

5. AC ‘97

5.1 AC ‘97 Frame Definition

5.2 AC-Link Serial Data Output Frame

Figure 9. AC-link Input and Output Framing

5.3 AC-Link AudioOutput Frame

5.3.1 Serial Data Output Slot Tags (Slot 0)

5.3.2 Register Address (Slot 1)

5.3.3 Register Write Data (Slot 2)

5.3.4 Playback Data (Slots 3-11)

5.3.5 GPIO Data (Slot12)

5.4 AC-Link Audio Input Frame

5.4.1 Serial Data Input Slot Tag Bits (Slot 0)

5.4.2 Read-Back Address Port (Slot 1)

5.4.3 Read-Back Data Port (Slot 2)

5.4.4 PCM Capture Data (Slot 3-11)

5.4.5 GPIO Pin Status (Slot 12)

5.5 AC ’97 Reset Modes

5.5.1 Cold AC ‘97 Reset

5.5.2 Warm AC ’97 Reset

5.5.3 AC ’97 Register Reset

5.6 AC-Link Protocol Violation - Loss of SYNC

6. REGISTER INTERFACE

Table 1. Mixer Registers

6.1 Register Descriptions

6.1.1 Reset (Index 00h)

6.1.2 Master Volume (Index 02h)

6.1.3 Alternate Volume (Index 04h)

Table 2. Alternate Line-Out and Master Mono Attenuation

6.1.4 Microphone Volume (Index 0Eh)

Table 3. Analog Mixer Input Gain Values

6.1.5 Stereo Analog Mixer Input Gain (Index’s 10h - 18h)