Cirrus Logic CS42418 User Manual

PLL

Internal Voltage

Reference

RST

GPO1

AD0/CS

SCL/CCLK

SDA/CDOUT

AD1/CDIN

VLC

AOUTA1+ AOUTA1-

AOUTB1+

AOUTA3+ AOUTA3-

AOUTA2-

AOUTB2-

AOUTA2+

AOUTB2+

AOUTB1-

AOUTB3+ AOUTB3-

AOUTA4+ AOUTA4-

AOUTB4+ AOUTB4-

AINL+ AINL-

AINR+ AINR-

FILT+REFGND VQ

ADC#1

ADC#2

Digital Filter

Gain & Clip

DAC_SCLK

DAC_LRCK

DAC_SDIN4

DAC_SDIN3

DAC_SDIN2

DAC_SDIN1

VLS

DGND VDOMCK RMCK LPFLT

INT

Control

Port

DAC#1

DAC#2

DAC#3

DAC#4

DAC#5

DAC#6

DAC#7

DAC#8

Digital Filter

Volume Control

GPO2 GPO3 GPO4 GPO5 GPO6 GPO7

MUTEC

Mute

Analog Filter

VA AGND

Mult/Div

GPO

Level Translator

DAC Serial Audio Port

ADC_SDOUT

ADCIN1 ADCIN2

ADC_LRCK

ADC Serial Audio

Port

ADC_SCLK

Level Translator

CS42418

110 dB, 192-kHz 8-Ch CODEC with PLL

Features

 Eight 24-bit D/A, two 24-bit A/D Converters

 110 dB DAC / 114 dB ADC Dynamic Range

 -100 dB THD+N

 System Sampling Rates up to 192 kHz

 Integrated Low-Jitter PLL for Increased System

Jitter Tolerance

 PLL Clock or System Clock Selection

 7 Configurable General-Purpose Outputs

 ADC High-Pass Filter for DC Offset Calibration

 Expandable ADC Channels and One-Line

Mode Support

 Digital Output Volume Control with Soft Ramp

 Digital ±15 dB Input Gain Adjust for ADC

 Differential Analog Architecture

 Supports Logic Levels between 1.8 V and 5 V

General Description

The CS42418 provides two analog-to-digital and eight digital-to-analog delta-sigma converters, as well as an integrated PLL.

The CS42418 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All eight channels of DAC provide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators.

The CS42418 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and digital speakers.

The CS42418 is available in a 64-pin LQFP package in Commercial (-10° to +70° C) grades. The CDB42428 Customer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on

page 71.

http://www.cirrus.com

MAR '14

DS603F2

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6

SPECIFIED OPERATING CONDITIONS ............................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6

ANALOG INPUT CHARACTERISTICS .................................................................................................. 7

A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 8

ANALOG OUTPUT CHARACTERISTICS .............................................................................................. 9

D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ 10

SWITCHING CHARACTERISTICS ......................................................................................................11

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT ........................................... 12

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 14

DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 15

2. PIN DESCRIPTIONS ............................................................................................................................ 16

3. TYPICAL CONNECTION DIAGRAMS ..............................................................................................18

4. APPLICATIONS ................................................................................................................................... 20

4.1 Overview ......................................................................................................................................... 20

4.2 Analog Inputs .................................................................................................................................. 20

4.2.1 Line-Level Inputs ................................................................................................................... 20

4.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 21

4.3 Analog Outputs ............................................................................................................................... 21

4.3.1 Line-Level Outputs and Filtering ........................................................................................... 21

4.3.2 Interpolation Filter .................................................................................................................. 21

4.3.3 Digital Volume and Mute Control ........................................................................................... 22

4.3.4 ATAPI Specification ............................................................................................................... 22

4.4 Clock Generation ............................................................................................................................ 23

4.4.1 PLL and Jitter Attenuation ..................................................................................................... 23

4.4.2 OMCK System Clock Mode ...................................................................................................24

4.4.3 Master Mode ......................................................................................................................... 24

4.4.4 Slave Mode ........................................................................................................................... 24

4.5 Digital Interfaces ............................................................................................................................. 25

4.5.1 Serial Audio Interface Signals ............................................................................................... 25

4.5.2 Serial Audio Interface Formats .............................................................................................. 27

4.5.3 ADCIN1/ADCIN2 Serial Data Format .................................................................................... 30

4.5.4 One-Line Mode (OLM) Configurations .................................................................................. 31

4.5.4.1 OLM Config #1 ........................................................................................................... 31

4.5.4.2 OLM Config #2 ........................................................................................................... 32

4.5.4.3 OLM Config #3 ........................................................................................................... 33

4.5.4.4 OLM Config #4 ........................................................................................................... 34

4.6 Control Port Description and Timing ............................................................................................... 34

4.6.1 SPI Mode ............................................................................................................................... 35

4.6.2 I²C Mode ................................................................................................................................ 36

4.7 Interrupts ........................................................................................................................................ 37

4.8 Reset and Power-Up ...................................................................................................................... 37

4.9 Power Supply, Grounding, and PCB Layout .................................................................................. 37

5. REGISTER QUICK REFERENCE ........................................................................................................ 39

6. REGISTER DESCRIPTION .................................................................................................................. 42

6.1 Memory Address Pointer (MAP) ..................................................................................................... 42

6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 42

6.3 Power Control (address 02h) .......................................................................................................... 43

6.4 Functional Mode (address 03h) ...................................................................................................... 43

6.5 Interface Formats (address 04h) .................................................................................................... 45

6.6 Misc Control (address 05h) ............................................................................................................ 46

CS42418

™

FORMAT .......................................... 13

2 DS603F2

CS42418

6.7 Clock Control (address 06h) ........................................................................................................... 48

6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 49

6.9 Clock Status (address 08h) (Read Only) ........................................................................................ 50

6.10 Volume Transition Control (address 0Dh) .................................................................................... 51

6.11 Channel Mute (address 0Eh) ........................................................................................................ 52

6.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) ...................................... 53

6.13 Channel Invert (address 17h) ....................................................................................................... 53

6.14 Mixing Control Pair 1 (Channels A1 & B1) (address 18h) Mixing Control Pair 2 (Channels A2 & B2) (address 19h) Mixing Control Pair 3 (Channels A3 & B3) (address 1Ah)

Mixing Control Pair 4 (Channels A4 & B4) (address 1Bh) ........................................................... 53

6.15 ADC Left Channel Gain (address 1Ch) ........................................................................................ 55

6.16 ADC Right Channel Gain (address 1Dh) ......................................................................................55

6.17 Interrupt Control (address 1Eh) .................................................................................................... 55

6.18 Interrupt Status (address 20h) (Read Only) ................................................................................. 56

6.19 Interrupt Mask (address 21h) ....................................................................................................... 57

6.20 Interrupt Mode MSB (address 22h)

Interrupt Mode LSB (address 23h) ...............................................................................................57

6.21 Mutec Pin Control (address 28h) .................................................................................................. 57

6.22 General-Purpose Pin Control (addresses 29h to 2Fh) ................................................................. 58

7. PARAMETER DEFINITIONS ................................................................................................................ 60

8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 61

8.1 ADC Input Filter .............................................................................................................................. 61

8.2 DAC Output Filter ........................................................................................................................... 61

9. APPENDIX B: PLL FILTER .................................................................................................................. 62

9.1 External Filter Components ............................................................................................................ 62

9.1.1 General .................................................................................................................................. 62

9.1.2 Capacitor Selection ............................................................................................................... 62

9.1.3 Circuit Board Layout .............................................................................................................. 63

10. APPENDIX C: ADC FILTER PLOTS .................................................................................................. 64

11. APPENDIX D: DAC FILTER PLOTS .................................................................................................. 66

12. PACKAGE DIMENSIONS ............................................................................................................... 70

THERMAL CHARACTERISTICS .......................................................................................................... 70

13. ORDERING INFORMATION .............................................................................................................. 71

14. REFERENCES .................................................................................................................................... 71

15. REVISION HISTORY ......................................................................................................................... 72

LIST OF FIGURES

Figure 1. Serial Audio Port Master Mode Timing ...................................................................................... 11

Figure 2. Serial Audio Port Slave Mode Timing ........................................................................................ 11

Figure 3. Control Port Timing - I²C Format ................................................................................................ 12

Figure 4. Control Port Timing - SPI Format ............................................................................................... 13

Figure 5. Typical Connection Diagram ...................................................................................................... 18

Figure 6. Typical Connection Diagram using the PLL ............................................................................... 19

Figure 7. Full-Scale Analog Input .............................................................................................................. 20

Figure 8. Full-Scale Output ....................................................................................................................... 21

Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4) ....................................................................22

Figure 10. Clock Generation ..................................................................................................................... 23

Figure 11. Right-Justified Serial Audio Formats ........................................................................................ 27

Figure 12. I²S Serial Audio Formats .......................................................................................................... 28

Figure 13. Left-Justified Serial Audio Formats .......................................................................................... 28

Figure 14. One Line Mode #1 Serial Audio Format ................................................................................... 29

Figure 15. One Line Mode #2 Serial Audio Format ................................................................................... 29

DS603F2 3

CS42418

Figure 16. ADCIN1/ADCIN2 Serial Audio Format ..................................................................................... 30

Figure 17. OLM Configuration #1 .............................................................................................................. 31

Figure 18. OLM Configuration #2 .............................................................................................................. 32

Figure 19. OLM Configuration #3 .............................................................................................................. 33

Figure 20. OLM Configuration #4 .............................................................................................................. 35

Figure 21. Control Port Timing in SPI Mode ............................................................................................. 35

Figure 22. Control Port Timing, I²C Write .................................................................................................. 36

Figure 23. Control Port Timing, I²C Read .................................................................................................. 36

Figure 24. Recommended Analog Input Buffer ......................................................................................... 61

Figure 25. Recommended Analog Output Buffer ...................................................................................... 61

Figure 26. Recommended Layout Example .............................................................................................. 63

Figure 27. Single-Speed Mode Stopband Rejection ................................................................................. 64

Figure 28. Single-Speed Mode Transition Band ....................................................................................... 64

Figure 29. Single-Speed Mode Transition Band (Detail) ........................................................................... 64

Figure 30. Single-Speed Mode Passband Ripple ..................................................................................... 64

Figure 31. Double-Speed Mode Stopband Rejection ................................................................................64

Figure 32. Double-Speed Mode Transition Band ...................................................................................... 64

Figure 33. Double-Speed Mode Transition Band (Detail) ......................................................................... 65

Figure 34. Double-Speed Mode Passband Ripple .................................................................................... 65

Figure 35. Quad-Speed Mode Stopband Rejection ..................................................................................65

Figure 36. Quad-Speed Mode Transition Band ........................................................................................ 65

Figure 37. Quad-Speed Mode Transition Band (Detail) ............................................................................65

Figure 38. Quad-Speed Mode Passband Ripple ...................................................................................... 65

Figure 39. Single-Speed (fast) Stopband Rejection .................................................................................. 66

Figure 40. Single-Speed (fast) Transition Band ........................................................................................ 66

Figure 41. Single-Speed (fast) Transition Band (detail) ............................................................................ 66

Figure 42. Single-Speed (fast) Passband Ripple ...................................................................................... 66

Figure 43. Single-Speed (slow) Stopband Rejection ................................................................................ 66

Figure 44. Single-Speed (slow) Transition Band ....................................................................................... 66

Figure 45. Single-Speed (slow) Transition Band (detail) ........................................................................... 67

Figure 46. Single-Speed (slow) Passband Ripple ..................................................................................... 67

Figure 47. Double-Speed (fast) Stopband Rejection ................................................................................ 67

Figure 48. Double-Speed (fast) Transition Band ....................................................................................... 67

Figure 49. Double-Speed (fast) Transition Band (detail) ........................................................................... 67

Figure 50. Double-Speed (fast) Passband Ripple ..................................................................................... 67

Figure 51. Double-Speed (slow) Stopband Rejection ............................................................................... 68

Figure 52. Double-Speed (slow) Transition Band ..................................................................................... 68

Figure 53. Double-Speed (slow) Transition Band (detail) ......................................................................... 68

Figure 54. Double-Speed (slow) Passband Ripple ................................................................................... 68

Figure 55. Quad-Speed (fast) Stopband Rejection ................................................................................... 68

Figure 56. Quad-Speed (fast) Transition Band ......................................................................................... 68

Figure 57. Quad-Speed (fast) Transition Band (detail) ............................................................................. 69

Figure 58. Quad-Speed (fast) Passband Ripple ....................................................................................... 69

Figure 59. Quad-Speed (slow) Stopband Rejection .................................................................................. 69

Figure 60. Quad-Speed (slow) Transition Band ........................................................................................ 69

Figure 61. Quad-Speed (slow) Transition Band (detail) ............................................................................ 69

Figure 62. Quad-Speed (slow) Passband Ripple ...................................................................................... 69

4 DS603F2

LIST OF TABLES

Table 1. Common OMCK Clock Frequencies ............................................................................................ 24

Table 2. Common PLL Output Clock Frequencies..................................................................................... 24

Table 3. Slave Mode Clock Ratios ............................................................................................................. 25

Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26

Table 5. DAC De-Emphasis ....................................................................................................................... 44

Table 6. Digital Interface Formats .............................................................................................................. 45

Table 7. ADC One-Line Mode.................................................................................................................... 45

Table 8. DAC One-Line Mode.................................................................................................................... 45

Table 9. RMCK Divider Settings ................................................................................................................ 48

Table 10. OMCK Frequency Settings ........................................................................................................ 48

Table 11. Master Clock Source Select....................................................................................................... 49

Table 12. PLL Clock Frequency Detection................................................................................................. 50

Table 13. Example Digital Volume Settings ............................................................................................... 53

Table 14. ATAPI Decode ........................................................................................................................... 54

Table 15. Example ADC Input Gain Settings ............................................................................................. 55

Table 16. PLL External Component Values ............................................................................................... 62

CS42418

DS603F2 5

CS42418

1. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T

= 25° C.)

SPECIFIED OPERATING CONDITIONS

(AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)

Parameter Symbol Min Typ Max Units

DC Power Supply Analog

Digital

Serial Port Interface

Control Port Interface

Ambient Operating Temperature (power applied)

VD VLS VLC

4.75

3.13

1.8

-10 - +70 C

5.0

3.3

5.0

5.25

V V V V

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog

Digital

Serial Port Interface

Control Port Interface Input Current (Note 1)

Analog Input Voltage (Note 2)

Digital Input Voltage Serial Port Interface

(Note 2) Control Port Interface

Ambient Operating Temperature(power applied)

Storage Temperature

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

VLS VLC

IND-S

IND-C

VA VD

T T

stg

-0.3

-±10mA

AGND-0.7 VA+0.7 V

-0.3

-20

-50

-65 +150 °C

6.0

VLS+ 0.4 VLC+ 0.4

+85 +95

V V V V

V V

°C °C

Notes:

1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

2. The maximum over/under voltage is limited by the input current.

6 DS603F2

CS42418

ANALOG INPUT CHARACTERISTICS

(TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Full-scale input sine wave, 997 Hz.; PDN_PLL = 1;

OMCK = 12.288 MHz; Single-Speed Mode DAC_SCLK = 3.072 MHz; Double-Speed Mode DAC_SCLK =

6.144 MHz; Quad-Speed Mode DAC_SCLK = 12.288 MHz.)

Parameter Symbol Min Typ Max Unit

Single-Speed Mode (Fs=48 kHz) Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise

(Note 3) -1 dB

-20 dB

-60 dB Double-Speed Mode (Fs=96 kHz) Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

Total Harmonic Distortion + Noise

(Note 3) -1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB Quad-Speed Mode (Fs=192 kHz) Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

Total Harmonic Distortion+ Noise

(Note 3) -1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

Dynamic Performance for All Modes

Interchannel Isolation Interchannel Phase Deviation

DC Accuracy

Interchannel Gain Mismatch Gain Drift Offset Error HPF_FREEZE disabled

HPF_FREEZE enabled

Analog Input

Full-scale Differential Input Voltage Input Impedance (Differential) (Note 4) Common Mode Rejection Ratio

THD+N

CMRR - 82 - dB

108 105

-110- dB

- 0.0001 - Degree

-0.1-dB

- +/-100 - ppm/°C

1.05 VA 1.10 VA 1.16 VA Vpp 17 - - k

114 111

-100

-91

-51

114 111 108

-100

-91

-51

-97

114 111 108

-100

-91

-51

-97

100

-94

dB dB

dB dB dB

dB dB dB dB

dB dB dB

dB dB dB dB

LSB LSB

Notes:

3. Referred to the typical full-scale voltage.

4. Measured between AIN+ and AIN-

DS603F2 7

A/D DIGITAL FILTER CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Single-Speed Mode (2 to 50 kHz sample rates)

Passband (-0.1 dB) (Note 5)

Passband Ripple

Stopband (Note 5)

Stopband Attenuation

Total Group Delay (Fs = Output Sample Rate)

Group Delay Variation vs. Frequency

Double-Speed Mode (50 to 100 kHz sample rates)

Passband (-0.1 dB) (Note 5)

Passband Ripple

Stopband (Note 5)

Stopband Attenuation

Total Group Delay (Fs = Output Sample Rate)

Group Delay Variation vs. Frequency

Quad-Speed Mode (100 to 192 kHz sample rates)

Passband (-0.1 dB) (Note 5)

Passband Ripple

Stopband (Note 5)

Stopband Attenuation

Total Group Delay (Fs = Output Sample Rate)

Group Delay Variation vs. Frequency

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 6)

Phase Deviation @ 20 Hz (Note 6)

Passband Ripple

Filter Setting Time

t

CS42418

0 - 0.47 Fs

--0.035 dB

0.58 - - Fs

-95 - - dB

-12/Fs- s

--0.0s

0 - 0.45 Fs

--0.035 dB

0.68 - - Fs

-92 - - dB

-9/Fs- s

--0.0s

0 - 0.24 Fs

--0.035 dB

0.78 - - Fs

-97 - - dB

-5/Fs- s

--0.0s

-120-

-10-Deg

--0dB

-10

/Fs - s

Hz Hz

Notes:

5. The filter frequency response scales precisely with Fs.

6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

8 DS603F2

CS42418

ANALOG OUTPUT CHARACTERISTICS

(TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measurement

= 3 k,

dB dB dB dB

dB dB dB dB dB dB

Bandwidth 10 Hz to 20 kHz unless otherwise specified.; Full-scale output 997 Hz sine wave, Test load R C

= 30 pF; PDN_PLL = 1; OMCK = 12.288 MHz; Single-Speed Mode, DAC_SCLK = 3.072 MHz; Double-Speed

Mode, DAC_SCLK = 6.144 MHz; Quad-Speed Mode, DAC_SCLK = 12.288 MHz.)

Parameter Symbol Min Typ Max Unit

Dynamic performance for all modes

Dynamic Range (Note 7)

24-bit A-Weighted

unweighted

16-bit A-Weighted

(Note 8) unweighted

Total Harmonic Distortion + Noise

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

(Note 8) -20 dB

-60 dB Idle Channel Noise/Signal-to-Noise Ratio (A-Weighted) Interchannel Isolation (1 kHz)

THD+N

104 101

-110 - dB

-90 -dB

110 107

97 94

-100

-91

-51

-94

-74

-34

-94

Analog Output Characteristics for all modes

Unloaded Full-Scale Differential Output Voltage Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance

OUT

R C

.89 VA .94 VA .99 VA Vpp

-0.1 - dB

- 300 - ppm/°C

- 150 - 

3- -k

- - 30 pF

Notes:

7. One LSB of triangular PDF dither is added to data.

8. Performance limited by 16-bit quantization noise.

DS603F2 9

D/A DIGITAL FILTER CHARACTERISTICS

Fast Roll-Off Slow Roll-Off

Parameter

Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 10) Group Delay Passband Group Delay Deviation 0 - 20 kHz De-emphasis Error (Note 11) Fs = 32 kHz

(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 10) Group Delay Passband Group Delay Deviation 0 - 20 kHz

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 10) Group Delay Passband Group Delay Deviation 0 - 20 kHz

0 0

-0.01 - +0.01 -0.01 - +0.01 dB

0.5465 - - 0.5834 - - Fs 90 - - 64 - - dB

- 12/Fs - - 6.5/Fs - s

- - ±0.41/Fs - ±0.14/Fs s

0 0

-0.01 - 0.01 -0.01 - 0.01 dB

0.5834 - - 0.7917 - - Fs 80 - - 70 - - dB

- 4.6/Fs - - 3.9/Fs - s

- - ±0.03/Fs - ±0.01/Fs s

0 0

-0.01 - 0.01 -0.01 - 0.01 dB

0.6355 - - 0.8683 - - Fs 90 - - 75 - - dB

- 4.7/Fs - - 4.2/Fs - s

- - ±0.01/Fs - ±0.01/Fs s

0.4535

0.4998

±0.23 ±0.14 ±0.09

0.4166

0.4998

0.1046

0.4897

0 0

CS42418

UnitMin Typ Max Min Typ Max

0.4166

0.4998FsFs

±0.23 ±0.14 ±0.09

0.2083

0.4998FsFs

0.1042

0.4813FsFs

dB dB dB

Notes:

9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 39 to 62) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

10. Single- and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.

11. De-emphasis is available only in Single-Speed Mode.

10 DS603F2

CS42418

DAC_SCLK ADC_SCLK

(output)

RMCK

smd

lmd

DAC_LRCK ADC_LRCK

(output)

sckh

sckl

MSB

MSB-1

dpd

ADC_SDOUT

DAC_SDINx

lrpd

lrcks

lrckd

DAC_SCLK ADC_SCLK

(input)

DAC_LRCK ADC_LRCK

(input)

Figure 1. Serial Audio Port Master Mode Timing Figure 2. Serial Audio Port Slave Mode Timing

SWITCHING CHARACTERISTICS

(TA = -10 to +70° C; VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS,

= 30 pF)

Parameters Symbol Min Typ Max Units

RST Pin Low Pulse Width (Note 12)

PLL Clock Recovery Sample Rate Range

RMCK Output Jitter (Note 14)

RMCK Output Duty Cycle (Note 15)

OMCK Frequency (Note 13)

OMCK Duty Cycle (Note 13)

DAC_SCLK, ADC_SCLK Duty Cycle

DAC_LRCK, ADC_LRCK Duty Cycle

Master Mode

RMCK to DAC_SCLK, ADC_SCLK active edge delay

RMCK to DAC_LRCK, ADC_LRCK delay

Slave Mode

DAC_SCLK, ADC_SCLK Falling Edge to ADC_SDOUT, ADC_SDOUT Output Valid

DAC_LRCK, ADC_LRCK Edge to MSB Valid

DAC_SDIN Setup Time Before DAC_SCLK Rising Edge

DAC_SDIN Hold Time After DAC_SCLK Rising Edge

DAC_SCLK, ADC_SCLK High Time

DAC_SCLK, ADC_SCLK Low Time

DAC_SCLK, ADC_SCLK falling to DAC_LRCK, SAI_LRCK Edge

smd

sckh

sckl

lmd

dpd

lrpd

lrck

1--ms

30 - 200 kHz

- 200 - ps RMS

45 50 55 %

1.024 - 25.600 MHz

40 50 60 %

45 50 55 %

0-15ns

- (Note 16) ns

-26.5ns

10 - - ns

30 - - ns

20 - - ns

-25 - +25 ns

Notes:

12. After powering-up the CS42418, RST

should be held low after the power supplies and clocks are set-

tled.

13. See Table 1 on page 24 for suggested OMCK frequencies

14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.

15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 48 is set to Multiply by 2.

16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.

DS603F2 11

CS42418

256 Fs

---------------------

128 Fs

---------------------

64 Fs

------------------

buf

hdst

low

hdd

high

sud

Stop Start

SDA

SCL

irs

RST

hdst

sust

susp

Start

Stop

Repeated

ack

Figure 3. Control Port Timing - I²C Format

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT

(TA = -10 to +70° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC,

=30pF)

Parameter Symbol Min Max Unit

SCL Clock Frequency

Rising Edge to Start

RST

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low time

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling (Note 17)

SDA Setup time to SCL Rising

Rise Time of SCL and SDA

Fall Time SCL and SDA

Setup Time for Stop Condition

Acknowledge Delay from SCL Falling (Note 18)

hdst

low

high

sust

hdd

sud

susp

ack

scl

irs

buf

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs

0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

- (Note 19) ns

Notes:

17. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

19. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode

12 DS603F2

CS42418

dsu

sch

scl

CCLK

CDIN

css

CDOUT

csh

Figure 4. Control Port Timing - SPI Format

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT

(TA = -10 to +70° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC,

=30pF)

Parameter Symbol Min Typ Max Units

CCLK Clock Frequency

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time (Note 20)

CCLK Falling to CDOUT Stable

Rise Time of CDOUT

Fall Time of CDOUT

Rise Time of CCLK and CDIN (Note 21)

Fall Time of CCLK and CDIN (Note 21)

Notes:

20. Data must be held for sufficient time to bridge the transition time of CCLK.

21. For f

<1 MHz.

sck

csh

css

scl

sch

dsu

0-6.0MHz

1.0 - - s

20 - - ns

66 - - ns

40 - - ns

15 - - ns

--50ns

--25ns

--100ns

DS603F2 13

DC ELECTRICAL CHARACTERISTICS

(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)

Parameter Symbol Min Typ Max Units

Power Supply Current normal operation, VA = 5 V

(Note 22) VD = 5 V

VD = 3.3 V

Interface current, VLC=5 V (Note 23)

VLS=5 V

power-down state (all supplies) (Note 24)

Power Consumption (Note 22) VA=5 V, VD=VLS=VLC=3.3 V normal operation

power-down (Note 24)

VA=5 V, VD=VLS=VLC=5 V normal operation

power-down (Note 24)

Power Supply Rejection Ratio (Note 25) (1 kHz)

(60 Hz)

VQ Nominal Voltage VQ Output Impedance VQ Maximum allowable DC current

FILT+ Nominal Voltage FILT+ Output Impedance FILT+ Maximum allowable DC current

PSRR

75 85 51

250

587

1.25 866

1.25

60 40

2.7 50

0.01

5.0 35

0.01

650

960

CS42418

mA mA mA

A

mW mW mW mW

dB dB

k

Notes:

22. Current consumption increases with increasing FS and increasing OMCK. Max values are based on highest FS and highest OMCK. Variance between speed modes is negligible.

23. I

24. Power-Down Mode is defined as RST

measured with no external loading on the SDA pin.

pin = Low with all clock and data lines held static.

25. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 5.

14 DS603F2

DIGITAL INTERFACE CHARACTERISTICS

(TA = +25° C)

Parameters (Note 26) Symbol Min Typ Max Units

High-Level Input Voltage Serial Port

Control Port

Low-Level Input Voltage Serial Port

Control Port

High-Level Output Voltage at I

Low-Level Output Voltage at I Serial Port, Control Port, MUTEC, GPOx

High-Level Output Voltage at I

Low-Level Output Voltage at I

Input Leakage Current Input Capacitance MUTEC Drive Current

=2 mA (Note 27)Serial Port

Control Port

MUTEC, GPOx

=2 mA (Note 27)

=100 A (Note 27)Serial Port

Control Port

MUTEC, GPOx

=100 A (Note 27)Serial Port

Control Port

MUTEC, GPOx

CS42418

0.7xVLS

0.7xVLC

VLS-1.0

VLC-1.0

VA- 1.0

0.2xVLS

0.2xVLC

V V

V V V

--0.4V

0.8xVLS

0.8xVLC

0.8xVA

0.2xVLS

0.2xVLC

0.2xVA

V V V

--±10A

-8-pF

-3-mA

Notes:

26. Serial Port signals include: RMCK, OMCK, ADC_SCLK, ADC_LRCK, DAC_SCLK, DAC_LRCK, ADC_SDOUT, DAC_SDIN1-4, ADCI N 1/2 Con t rol Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS

, AD1/CDIN, INT, RST

27. When operating RMCK above 24.576 MHz, limit the loading on the signal to 1 CMOS load.

DS603F2 15

2. PIN DESCRIPTIONS

17 1 8 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

DAC_SDIN1

ADC_SCLK

ADC_LRCK

DGND

VLC

SCL/CCLK

SDA/CDOUT

AD1/CDIN

AD0/CS

INT

RST

AINR-

AINR+

AINL+

AINL-

FILT+

REFGND

AOUTB4-

AOUTB4+

AOUTA4+

AOUTA4-

AGND

AOUTB3-

AOUTB3+

AOUTA3+

AOUTA3-

AOUTB2-

AOUTB2+

AOUTA2+

AOUTA2-

AOUTB1-

AOUTB1+

AOUTA1+

AOUTA1-

MUTEC

AGND

GPO7

GPO6

GPO5

GPO4

GPO3

GPO2

GPO1

LPFLT

DGND

VLS

RMCK

ADC_SDOUT

ADCIN2

ADCIN1

OMCK

DAC_LRCK

DAC_SCLK

DAC_SDIN4

DAC_SDIN3

DAC_SDIN2

CS42418

Pin Name # Pin Description

DAC_SDIN1 DAC_SDIN2 DAC_SDIN3DAC_SDIN4

DAC_SCLK

DAC_LRCK

DGND

VLC

SCL/CCLK

SDA/CDOUT

AD1/CDIN

AD0/CS

INT

16 DS603F2

DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

63 62

DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface.

DAC Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on

the DAC serial audio data line.

Digital Power (Input) - Positive power supply for the digital section.

Digital Ground (Input) - Ground reference. Should be connected to digital ground.

Control Port Power (Input) - Determines the required signal level for the control port.

Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up

resistor to the logic interface voltage in I²C mode as shown in the Typical Connection Diagram. Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up

resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output data line for the control port interface in SPI mode.

Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C mode; CDIN is

the input data line for the control port interface in SPI mode.

Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS

is the chip select signal in SPI mode. Interrupt (Output) - The CS42418 will generate an interrupt condition as per the Interrupt Mask register.

See “Interrupts” on page 37 for more details.

RST

AINRAINR+

AINL+ AINL-

FILT+

REFGND

AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,AOUTA4 +,AOUTB4 +,-

AGND

MUTEC

LPFLT

GPO7 GPO6 GPO5 GPO4 GPO3 GPO2 GPO1

VLS

RMCK

ADC_SDOUT

ADCIN1 ADCIN2

OMCK

ADC_LRCK

ADC_SCLK

Reset

13 14

15 16

36,37 35,34 32,33 31,30 28,29 27,26 22,23 21,20

24 41

25 40

42 43 44 45 46 47 48

58 57

(Input) - The device enters a low power mode and all internal registers are reset to their default

settings when low.

Differential Right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators via the AINR+/- pins.

Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators via the AINL+/- pins.

Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

Reference Ground (Input) - Ground reference for the internal sampling circuits.

Differential Analog Output (Output) - The full-scale differential analog output level is specified in the

Analog Characteristics specification table.

Analog Power (Input) - Positive power supply for the analog section.

Analog Ground (Input) - Ground reference. Should be connected to analog ground.

Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power-on con-

dition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.

PLL Loop Filter (Output) - An RC network should be connected between this pin and ground.

General Purpose Output (Output) - These pins can be configured as general purpose output pins, an

ADC overflow interrupt or Mute Control outputs according to the General Purpose Pin Control registers.

Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.

Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference

(OMCK, pin 59) or the PLL which is locked to the incoming ADC_LRCK. ADC Serial Data Output (Output) - Output for two’s complement serial audio PCM data from the output

of the internal and external ADCs. External ADC Serial Input (Input) - The CS42418 provides for up to two external stereo analog to digital

converter inputs to provide a maximum of six channels on one serial data output line when the CS42418 is placed in One-Line Mode.

External Reference Clock (Input) - External clock reference that must be within the ranges specified in the register “OMCK Frequency (OMCK Freqx)” on page 48.

ADC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the ADC serial audio data line.

ADC Serial Clock (Input/Output) - Serial clock for the ADC serial audio interface.

CS42418

DS603F2 17

3. TYPICAL CONNECTION DIAGRAMS

VLS

AOUTA1+

0.1 µF

10 µF

100 µF

0.1 µF

FILT+

0.1 µF

4.7 µF

10 µF

0.1 µF

AOUTA1-

AOUTB1+

AOUTB1-

AOUTA2+

AOUTA2-

AOUTB2+

AOUTB2-

AOUTA3+

AOUTA3-

AOUTB3+

AOUTB3-

AOUTA4+

AOUTA4-

AOUTB4+

AOUTB4-

MUTEC

DGND

VLC

0.1 µF

+1.8 V

to +5 V

SCL/CCLK

SDA/CDOUT

AD1/CDIN

RST

OMCK

ADC_LRCK

REFGND

AD0/CS

INT

Digital Audio

Processor

Micro-

Controller

RMCK

ADCIN1

ADCIN2

CS5361

A/D Converter

CS5361

A/D Converter

ADC_SDOUT

VAVD

0.1 µF

AGNDAGND

52 40

LPFLT

AINL+

AINL-

AINR+

AINR-

Connect DGND and AGND at single point near Codec

GPO1

GPO2

GPO3

GPO4

GPO5

GPO6

GPO7

DAC_SDIN1

ADC_SCLK

DAC_SDIN3

DAC_SDIN2

DAC_SDIN4

DAC_LRCK

DAC_SCLK

0.01 µF

0.1 µF

10 µF

+5 V

0.01 µF

+3.3 V to +5 V

10 µF

0.1 µF 0.01 µF

+3.3 V

to +5.0 V

S/PDIF

CS8416

Receiver

RMCK

OSC

Optional

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Mute Drive

(optional)

+VA

* Pull up or down as

required on startup if the

Mute Control is used.

2700 pF*

Left Analog Input

Right Analog Input

Analog

Input

Buffer

Analog

Input

Buffer

CFILT

RFILT

CRIP

2 k 2 k

** **

** Resistors are required for

C control port operation

1. See the ADC Input Filter section in the Appendix.

2. See the DAC Output Filter section in the Appendix.

3. See the PLL Filter section in the Appendix.

Figure 5. Typical Connection Diagram

CS42418

18 DS603F2

CS42418

VLS

AOUTA1+

0.1 µF

10 µF

100 µF

0.1 µF

FILT+

0.1 µF

4.7 µF

10 µF

0.1 µF

+1.8 V

to +5 .0 V

AOUTA1-

AOUTB1+

AOUTB1-

AOUTA2+

AOUTA2-

AOUTB2+

AOUTB2-

AOUTA3+

AOUTA3-

AOUTB3+

AOUTB3-

AOUTA4+

AOUTA4-

AOUTB4+

AOUTB4-

MUTEC

DGND

VLC

0.1 µF

SCL/CCLK

SDA/CDOUT

AD1/CDIN

RST

OMCK

ADC_LRCK

REFGND

AD0/CS

INT

DVD

Processor

RMCK

ADCIN1

ADCIN2

ADC_SDOUT

VAVD

0.1 µF

AGNDAGND

52 40

LPFLT

AINL+

AINL-

AINR+

AINR-

GPO1

GPO2

GPO3

GPO4

GPO5

GPO6

GPO7

DAC_SDIN1

ADC_SCLK

DAC_SDIN3

DAC_SDIN2

DAC_SDIN4

DAC_LRCK

DAC_SCLK

0.01 µF

0.1 µF

10 µF

+5 V

0.01 µF

+3.3 V to +5 V

10 µF

0.1 µF 0.01 µF

27 MH z

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

An alo g O u tpu t Bu ffe r

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Mute Drive

(op tio na l)

2700 pF*

Left Analog Input

Right Analog Input

Analog

Input

Buffer

Analog

Input

Buffer

* Pull up or do wn as required on

startu p if the Mute Control is

used.

Connect DGN D and A GND at single point near Codec

CFILT

RFILT

CRIP

2 k 2 k

** **

+VA

** Resistors are required for

C control port operation

1. See the ADC Input Filter section in the Appendix.

2. See the DAC Ou tput Filter section in the Appendix.

3. See the PLL Filter section in the Appendix.

Figure 6. Typical Connection Diagram using the PLL

CS42418

DS603F2 19

4. APPLICATIONS

AIN+

AIN-

Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp

4.1 V

2.7 V

1.3 V

4.1 V

2.7 V

1.3 V

Figure 7. Full-Scale Analog Input

4.1 Overview

The CS42418 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital converters (ADC), implemented using multi-bit delta-sigma techniques, and 8 digital-to-analog converters (DAC). Other functions integrated within the codec include independent digital volume controls for each DAC, digital de-emphasis filters for DAC, digital gain control for ADC channels, ADC high-pass filters, and an on-chip voltage reference. All serial data is transmitted through one configurable serial audio interface for the ADC with enhanced one-line modes of operation, allowing up to 6 channels of serial audio data on one data line. All functions are configured through a serial control port operable in SPI mode or in I²C mode.

5 and 6 show the recommended connections for the CS42418.

The CS42418 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the FM bits in register “Functional Mode (address 03h)” on page 43. Single-Speed Mode (SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x.

Using the integrated PLL, a low-jitter clock is recovered from the ADC LRCK input signal. The recovered clock or an externally supplied clock attached to the OMCK pin can be used as the System Clock.

4.2 Analog Inputs

CS42418

4.2.1 Line-Level Inputs

AINR+, AINR-, AINL+, and AINL- are the line-level differential analog inputs. The analog signal must be externally biased to VQ, approximately 2.7 V, before being applied to these inputs. The level of the signal can be adjusted for the left and right ADC independently through the ADC Left and Right Channel Gain Control Registers on page 55. The ADC output data is in two’s complement binary format. For inputs above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC Overflow bit in the register “Interrupt Status (address 20h) (Read Only)” on

page 56 to be set to a ‘1’. The GPO pins may also be configured to indicate an overflow condition has

occurred in the ADC. See “General-Purpose Pin Control (addresses 29h to 2Fh)” on page 58 for proper configuration. Figure 7 shows the full-scale analog input levels. See “ADC Input Filter” on page 61 for a recommended input buffer.

20 DS603F2

4.2.2 High-Pass Filter and DC Offset Calibration

AOUT+

AOUT-

Full-Scale Output Level= (AIN+) - (AIN-)= 5 Vpp

3.95 V

2.7 V

1.45 V

3.95 V

2.7 V

1.45 V

Figure 8. Full-Scale Output

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. The high-pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by:

1. Running the CS42418 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time.

2. Disabling the high-pass filter and freezing the stored DC offset.

The high-pass filters are controlled using the HPF_FREEZE bit in the register “Misc Control (address

05h)” on page 46.

4.3 Analog Outputs

4.3.1 Line-Level Outputs and Filtering

The CS42418 contains on-chip buffer amplifiers capable of producing line-level differential outputs. These amplifiers are biased to a quiescent DC level of approximately VQ.

The delta-sigma conversion process produces high-frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low-pass filter. See “DAC Output Filter” on page 61 for a recommended output buffer. This filter configuration accounts for the normally differing AC loads on the AOUT+ and AOUT- differential output pins. It also shows an AC coupling configuration which minimizes the number of required AC coupling capacitors. Figure 8 shows the full-scale analog output levels.

CS42418

4.3.2 Interpolation Filter

To accommodate the increasingly complex requirements of digital audio systems, the CS42418 incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is avail-

DS603F2 21

able in Single-, Double-, and Quad-Speed Modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit found in the register “Misc Control (address 05h)”

on page 46 selects which filter is used. Filter response plots can be found in Figures 39 to 62.

4.3.3 Digital Volume and Mute Control



A Channel

Volume

Control

AOUTAx

AOUTBx

Left Channel

Audio Data

Right Channel

Audio Data

BChannel

Volume

Control

MUTE

DAC_SDINx

Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4)

Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to

-127 dB attenuation with 0.5 dB resolution. See “Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h,

14h, 15h, 16h)” on page 53. Volume control changes are programmable to ramp in increments of

0.125 dB at the rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See “Volume

Transition Control (address 0Dh)” on page 51.

Each output can be independently muted via mute control bits in the register “Channel Mute (address

0Eh)” on page 52. When enabled, each XX_MUTE bit attenuates the corresponding DAC to its maximum

value (-127 dB). When the XX_MUTE bit is disabled, the corresponding DAC returns to the attenuation level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by the SZC[1:0] bits.

The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The Mute Control pin outputs high impedance during Power-Up or in Power-Down Mode by setting the PDN bit in the register “Power Control (address 02h)” on page 43 to a ‘1’. Once out of Power-Down Mode, the pin can be controlled by the user via the control port, or automatically asserted high when zero data is present on all DAC inputs, or when serial port clock errors are present. To prevent large transients on the output, it is desirable to mute the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin in the Pin Descriptions section for more information.

Each of the GPO1-GPO7 can be programmed to provide a hardware MUTE signal to individual circuits. Each pin can be programmed as an output, with specific muting capabilities as defined by the function bits in the register “General-Purpose Pin Control (addresses 29h to 2Fh)” on page 58.

CS42418

4.3.4 ATAPI Specification

The CS42418 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 14 on page 54 and Figure 9 for additional information.

22 DS603F2

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