Cirrus Logic CS42416 User Manual

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PLL

Internal Voltage

Reference

RST

GPO1

AD0/CS

SCL/CCLK

SDA/CDOUT

AD1/CDIN

VLC

AOUTA1+ AOUTA1-

AOUTB1+

AOUTA3+ AOUTA3-

AOUTA2-

AOUTB2-

AOUTA2+

AOUTB2+

AOUTB1-

AOUTB3+ AOUTB3-

AINL+ AINL-

AINR+ AINR-

FILT+REFGND VQ

ADC#1

ADC#2

Digital Filter

Gain & Clip

ADC_SDOUT

ADCIN1 ADCIN2

DAC_SCLK

DAC_LRCK

DAC_SDIN3

DAC_SDIN2

DAC_SDIN1

VLS

ADC_LRCK

DGND VDOMCK RMCK LPFLT

INT

Control

Port

DAC#1

DAC#2

DAC#3

DAC#4

DAC#5

DAC#6

Digital Filter

Volume Control

GPO2 GPO3 GPO4 GPO5 GPO6 GPO7

MUTEC

Mute

Analog Filt er

VA AGND

ADC Serial Audio

Port

Mult/Div

GPO

ADC_SCLK

Level TranslatorLevel Translator

DAC Serial Audio Port

CS42416

110 dB, 192-kHz 6-Ch CODEC with PLL

Features

 Six 24-bit D/A, two 24-bit A/D Converters

 110 dB DAC / 114 dB ADC Dynamic Range

 -100 dB THD+N

 System Sampling Rates up to 192 kHz

 Integrated Low-Jitter PLL for Increased System

Jitter Tolerance

 PLL Clock or System Clock Selection

 7 Configurable General-Purpose Outputs

 ADC High-Pass Filter for DC Offset Calibration

 Expandable ADC Channels and One-Line

Mode Support

 Digital Output Volume Control with Soft Ramp

 Digital ±15 dB Input Gain Adjust for ADC

 Differential Analog Architecture

 Supports Logic Levels between 1.8 V and 5 V

General Description

The CS42416 provides two analog-to-digital and six digital-to-analog delta-sigma converters, as well as an integrated PLL.

The CS42416 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All six channels of DAC provide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators.

The CS42416 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and digital speakers.

The CS42416 is available in a 64-pin LQFP package in Commercial (-10° to +70° C) grades. The CDB42428 Customer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on

page 71.

http://www.cirrus.com

MAR '14

DS602F2

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6

SPECIFIED OPERATING CONDITIONS ............................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6

ANALOG INPUT CHARACTERISTICS .................................................................................................. 7

A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 8

ANALOG OUTPUT CHARACTERISTICS .............................................................................................. 9

D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ 10

SWITCHING CHARACTERISTICS ......................................................................................................11

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT ........................................... 12

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 14

DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 15

2. PIN DESCRIPTIONS ............................................................................................................................ 16

3. TYPICAL CONNECTION DIAGRAMS ..............................................................................................18

4. APPLICATIONS ................................................................................................................................... 20

4.1 Overview ......................................................................................................................................... 20

4.2 Analog Inputs .................................................................................................................................. 20

4.2.1 Line-Level Inputs ................................................................................................................... 20

4.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 21

4.3 Analog Outputs ............................................................................................................................... 21

4.3.1 Line-Level Outputs and Filtering ........................................................................................... 21

4.3.2 Interpolation Filter .................................................................................................................. 21

4.3.3 Digital Volume and Mute Control ........................................................................................... 22

4.3.4 ATAPI Specification ............................................................................................................... 22

4.4 Clock Generation ............................................................................................................................ 23

4.4.1 PLL and Jitter Attenuation ..................................................................................................... 23

4.4.2 OMCK System Clock Mode ...................................................................................................24

4.4.3 Master Mode ......................................................................................................................... 24

4.4.4 Slave Mode ........................................................................................................................... 24

4.5 Digital Interfaces ............................................................................................................................. 25

4.5.1 Serial Audio Interface Signals ............................................................................................... 25

4.5.2 Serial Audio Interface Formats .............................................................................................. 27

4.5.3 ADCIN1/ADCIN2 Serial Data Format .................................................................................... 30

4.5.4 One-Line Mode (OLM) Configurations .................................................................................. 31

4.5.4.1 OLM Config #1 ........................................................................................................... 31

4.5.4.2 OLM Config #2 ........................................................................................................... 32

4.5.4.3 OLM Config #3 ........................................................................................................... 33

4.5.4.4 OLM Config #4 ........................................................................................................... 34

4.6 Control Port Description and Timing ............................................................................................... 35

4.6.1 SPI Mode ............................................................................................................................... 35

4.6.2 I²C Mode ................................................................................................................................ 36

4.7 Interrupts ........................................................................................................................................ 37

4.8 Reset and Power-Up ...................................................................................................................... 38

4.9 Power Supply, Grounding, and PCB Layout .................................................................................. 38

5. REGISTER QUICK REFERENCE ........................................................................................................ 39

6. REGISTER DESCRIPTION .................................................................................................................. 42

6.1 Memory Address Pointer (MAP) ..................................................................................................... 42

6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 42

6.3 Power Control (address 02h) .......................................................................................................... 43

6.4 Functional Mode (address 03h) ...................................................................................................... 43

6.5 Interface Formats (address 04h) .................................................................................................... 45

6.6 Misc Control (address 05h) ............................................................................................................ 46

CS42416

™

FORMAT .......................................... 13

2 DS602F2

CS42416

6.7 Clock Control (address 06h) ........................................................................................................... 48

6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 49

6.9 Clock Status (address 08h) (Read Only) ........................................................................................ 50

6.10 Volume Transition Control (address 0Dh) .................................................................................... 51

6.11 Channel Mute (address 0Eh) ........................................................................................................ 52

6.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) ...................................................... 53

6.13 Channel Invert (address 17h) ....................................................................................................... 53

6.14 Mixing Control Pair 1 (Channels A1 & B1) (address 18h) Mixing Control Pair 2 (Channels A2 & B2) (address 19h)

Mixing Control Pair 3 (Channels A3 & B3) (address 1Ah) ............................................................ 53

6.15 ADC Left Channel Gain (address 1Ch) ........................................................................................ 55

6.16 ADC Right Channel Gain (address 1Dh) ......................................................................................55

6.17 Interrupt Control (address 1Eh) .................................................................................................... 55

6.18 Interrupt Status (address 20h) (Read Only) ................................................................................. 56

6.19 Interrupt Mask (address 21h) ....................................................................................................... 57

6.20 Interrupt Mode MSB (address 22h)

Interrupt Mode LSB (address 23h) ...............................................................................................57

6.21 Mutec Pin Control (address 28h) .................................................................................................. 57

6.22 General-Purpose Pin Control (addresses 29h to 2Fh) ................................................................. 58

7. PARAMETER DEFINITIONS ................................................................................................................ 60

8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 61

8.1 ADC Input Filter .............................................................................................................................. 61

8.2 DAC Output Filter ........................................................................................................................... 61

9. APPENDIX B: PLL FILTER .................................................................................................................. 62

9.1 External Filter Components ............................................................................................................ 62

9.1.1 General .................................................................................................................................. 62

9.1.2 Capacitor Selection ............................................................................................................... 62

9.1.3 Circuit Board Layout .............................................................................................................. 63

10. APPENDIX C: ADC FILTER PLOTS .................................................................................................. 64

11. APPENDIX D: DAC FILTER PLOTS .................................................................................................. 66

12. PACKAGE DIMENSIONS ............................................................................................................... 70

THERMAL CHARACTERISTICS .......................................................................................................... 70

13. ORDERING INFORMATION .............................................................................................................. 71

14. REFERENCES .................................................................................................................................... 71

15. REVISION HISTORY ......................................................................................................................... 72

LIST OF FIGURES

Figure 1. Serial Audio Port Master Mode Timing ...................................................................................... 11

Figure 2. Serial Audio Port Slave Mode Timing ........................................................................................ 11

Figure 3. Control Port Timing - I²C Format ................................................................................................ 12

Figure 4. Control Port Timing - SPI Format ............................................................................................... 13

Figure 5. Typical Connection Diagram ...................................................................................................... 18

Figure 6. Typical Connection Diagram using the PLL ............................................................................... 19

Figure 7. Full-Scale Analog Input .............................................................................................................. 20

Figure 8. Full-Scale Output ....................................................................................................................... 21

Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3) ........................................................................ 22

Figure 10. Clock Generation ..................................................................................................................... 23

Figure 11. Right-Justified Serial Audio Formats ........................................................................................ 27

Figure 12. I²S Serial Audio Formats .......................................................................................................... 28

Figure 13. Left-Justified Serial Audio Formats .......................................................................................... 28

Figure 14. One-Line Mode #1 Serial Audio Format .................................................................................. 29

Figure 15. One-Line Mode #2 Serial Audio Format .................................................................................. 29

Figure 16. ADCIN1/ADCIN2 Serial Audio Format ..................................................................................... 30

DS602F2 3

CS42416

Figure 17. OLM Configuration #1 .............................................................................................................. 31

Figure 18. OLM Configuration #2 .............................................................................................................. 32

Figure 19. OLM Configuration #3 .............................................................................................................. 33

Figure 20. OLM Configuration #4 .............................................................................................................. 35

Figure 21. Control Port Timing in SPI Mode ............................................................................................. 36

Figure 22. Control Port Timing, I²C Write .................................................................................................. 36

Figure 23. Control Port Timing, I²C Read .................................................................................................. 37

Figure 24. Recommended Analog Input Buffer ......................................................................................... 61

Figure 25. Recommended Analog Output Buffer ...................................................................................... 61

Figure 26. Recommended Layout Example .............................................................................................. 63

Figure 27. Single-Speed Mode Stopband Rejection ................................................................................. 64

Figure 28. Single-Speed Mode Transition Band ....................................................................................... 64

Figure 29. Single-Speed Mode Transition Band (Detail) ........................................................................... 64

Figure 30. Single-Speed Mode Passband Ripple ..................................................................................... 64

Figure 31. Double-Speed Mode Stopband Rejection ................................................................................64

Figure 32. Double-Speed Mode Transition Band ...................................................................................... 64

Figure 33. Double-Speed Mode Transition Band (Detail) ......................................................................... 65

Figure 34. Double-Speed Mode Passband Ripple .................................................................................... 65

Figure 35. Quad-Speed Mode Stopband Rejection ..................................................................................65

Figure 36. Quad-Speed Mode Transition Band ........................................................................................ 65

Figure 37. Quad-Speed Mode Transition Band (Detail) ............................................................................65

Figure 38. Quad-Speed Mode Passband Ripple ...................................................................................... 65

Figure 39. Single-Speed (fast) Stopband Rejection .................................................................................. 66

Figure 40. Single-Speed (fast) Transition Band ........................................................................................ 66

Figure 41. Single-Speed (fast) Transition Band (detail) ............................................................................ 66

Figure 42. Single-Speed (fast) Passband Ripple ...................................................................................... 66

Figure 43. Single-Speed (slow) Stopband Rejection ................................................................................ 66

Figure 44. Single-Speed (slow) Transition Band ....................................................................................... 66

Figure 45. Single-Speed (slow) Transition Band (detail) ........................................................................... 67

Figure 46. Single-Speed (slow) Passband Ripple ..................................................................................... 67

Figure 47. Double-Speed (fast) Stopband Rejection ................................................................................ 67

Figure 48. Double-Speed (fast) Transition Band ....................................................................................... 67

Figure 49. Double-Speed (fast) Transition Band (detail) ........................................................................... 67

Figure 50. Double-Speed (fast) Passband Ripple ..................................................................................... 67

Figure 51. Double-Speed (slow) Stopband Rejection ............................................................................... 68

Figure 52. Double-Speed (slow) Transition Band ..................................................................................... 68

Figure 53. Double-Speed (slow) Transition Band (detail) ......................................................................... 68

Figure 54. Double-Speed (slow) Passband Ripple ................................................................................... 68

Figure 55. Quad-Speed (fast) Stopband Rejection ................................................................................... 68

Figure 56. Quad-Speed (fast) Transition Band ......................................................................................... 68

Figure 57. Quad-Speed (fast) Transition Band (detail) ............................................................................. 69

Figure 58. Quad-Speed (fast) Passband Ripple ....................................................................................... 69

Figure 59. Quad-Speed (slow) Stopband Rejection .................................................................................. 69

Figure 60. Quad-Speed (slow) Transition Band ........................................................................................ 69

Figure 61. Quad-Speed (slow) Transition Band (detail) ............................................................................ 69

Figure 62. Quad-Speed (slow) Passband Ripple ...................................................................................... 69

4 DS602F2

LIST OF TABLES

Table 1. Common OMCK Clock Frequencies ............................................................................................ 24

Table 2. Common PLL Output Clock Frequencies..................................................................................... 24

Table 3. Slave Mode Clock Ratios ............................................................................................................. 25

Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26

Table 5. DAC De-Emphasis ....................................................................................................................... 44

Table 6. Digital Interface Formats .............................................................................................................. 45

Table 7. ADC One-Line Mode.................................................................................................................... 45

Table 8. DAC One-Line Mode.................................................................................................................... 45

Table 9. RMCK Divider Settings ................................................................................................................ 48

Table 10. OMCK Frequency Settings ........................................................................................................ 48

Table 11. Master Clock Source Select....................................................................................................... 49

Table 12. PLL Clock Frequency Detection................................................................................................. 50

Table 13. Example Digital Volume Settings ............................................................................................... 53

Table 14. ATAPI Decode ........................................................................................................................... 54

Table 15. Example ADC Input Gain Settings ............................................................................................. 55

Table 16. PLL External Component Values ............................................................................................... 62

CS42416

DS602F2 5

CS42416

1. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T

= 25° C.)

SPECIFIED OPERATING CONDITIONS

(AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)

Parameter Symbol Min Typ Max Units

DC Power Supply Analog

Digital

Serial Port Interface

Control Port Interface

Ambient Operating Temperature (power applied)

VD VLS VLC

4.75

3.13

1.8

-10 - +70 C

5.0

3.3

5.0

5.25

V V V V

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supply Analog

Digital

Serial Port Interface

Control Port Interface Input Current (Note 1)

Analog Input Voltage (Note 2)

Digital Input Voltage Serial Port Interface

(Note 2) Control Port Interface

Ambient Operating Temperature(power applied)

Storage Temperature

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

VLS VLC

IND-S

IND-C

VA VD

T T

stg

-0.3

-±10mA

AGND-0.7 VA+0.7 V

-0.3

-20

-50

-65 +150 °C

6.0

VLS+ 0.4 VLC+ 0.4

+85 +95

V V V V

V V

°C °C

Notes:

1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

2. The maximum over/under voltage is limited by the input current.

6 DS602F2

CS42416

ANALOG INPUT CHARACTERISTICS

(TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Full-scale input sine wave, 997 Hz.; PDN_PLL = 1;

OMCK = 12.288 MHz; Single-Speed Mode DAC_SCLK = 3.072 MHz; Double-Speed Mode DAC_SCLK =

6.144 MHz; Quad-Speed Mode DAC_SCLK = 12.288 MHz.)

Parameter Symbol Min Typ Max Unit

Single-Speed Mode (Fs=48 kHz) Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise

(Note 3) -1 dB

-20 dB

-60 dB Double-Speed Mode (Fs=96 kHz) Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

Total Harmonic Distortion + Noise

(Note 3) -1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB Quad-Speed Mode (Fs=192 kHz) Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

Total Harmonic Distortion+ Noise

(Note 3) -1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

Dynamic Performance for All Modes

Interchannel Isolation Interchannel Phase Deviation

DC Accuracy

Interchannel Gain Mismatch Gain Drift Offset Error HPF_FREEZE disabled

HPF_FREEZE enabled

Analog Input

Full-scale Differential Input Voltage Input Impedance (Differential) (Note 4) Common Mode Rejection Ratio

THD+N

CMRR - 82 - dB

108 105

-110- dB

- 0.0001 - Degree

-0.1-dB

- +/-100 - ppm/°C

1.05 VA 1.10 VA 1.16 VA Vpp 17 - - k

114 111

-100

-91

-51

114 111 108

-100

-91

-51

-97

114 111 108

-100

-91

-51

-97

100

-94

dB dB

dB dB dB

dB dB dB dB

dB dB dB

dB dB dB dB

LSB LSB

Notes:

3. Referred to the typical full-scale voltage.

4. Measured between AIN+ and AIN-

DS602F2 7

A/D DIGITAL FILTER CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Single-Speed Mode (2 to 50 kHz sample rates)

Passband (-0.1 dB) (Note 5)

Passband Ripple

Stopband (Note 5)

Stopband Attenuation

Total Group Delay (Fs = Output Sample Rate)

Group Delay Variation vs. Frequency

Double-Speed Mode (50 to 100 kHz sample rates)

Passband (-0.1 dB) (Note 5)

Passband Ripple

Stopband (Note 5)

Stopband Attenuation

Total Group Delay (Fs = Output Sample Rate)

Group Delay Variation vs. Frequency

Quad-Speed Mode (100 to 192 kHz sample rates)

Passband (-0.1 dB) (Note 5)

Passband Ripple

Stopband (Note 5)

Stopband Attenuation

Total Group Delay (Fs = Output Sample Rate)

Group Delay Variation vs. Frequency

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 6)

Phase Deviation @ 20 Hz (Note 6)

Passband Ripple

Filter Setting Time

t

CS42416

0 - 0.47 Fs

--0.035 dB

0.58 - - Fs

-95 - - dB

-12/Fs- s

--0.0s

0 - 0.45 Fs

--0.035 dB

0.68 - - Fs

-92 - - dB

-9/Fs- s

--0.0s

0 - 0.24 Fs

--0.035 dB

0.78 - - Fs

-97 - - dB

-5/Fs- s

--0.0s

-120-

-10-Deg

--0dB

-10

/Fs - s

Hz Hz

Notes:

5. The filter frequency response scales precisely with Fs.

6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

8 DS602F2

CS42416

ANALOG OUTPUT CHARACTERISTICS

(TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measurement

= 3 k,

dB dB dB dB

dB dB dB dB dB dB

Bandwidth 10 Hz to 20 kHz unless otherwise specified.; Full-scale output 997 Hz sine wave, Test load R C

= 30 pF; PDN_PLL = 1; OMCK = 12.288 MHz; Single-Speed Mode, DAC_SCLK = 3.072 MHz; Double-Speed

Mode, DAC_SCLK = 6.144 MHz; Quad-Speed Mode, DAC_SCLK = 12.288 MHz.)

Parameter Symbol Min Typ Max Unit

Dynamic performance for all modes

Dynamic Range (Note 7)

24-bit A-Weighted

unweighted

16-bit A-Weighted

(Note 8) unweighted

Total Harmonic Distortion + Noise

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

(Note 8) -20 dB

-60 dB Idle Channel Noise/Signal-to-Noise Ratio (A-Weighted) Interchannel Isolation (1 kHz)

THD+N

104 101

-110 - dB

-90 -dB

110 107

97 94

-100

-91

-51

-94

-74

-34

-94

Analog Output Characteristics for all modes

Unloaded Full-Scale Differential Output Voltage Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance

OUT

R C

.89 VA .94 VA .99 VA Vpp

-0.1 - dB

- 300 - ppm/°C

- 150 - 

3- -k

- - 30 pF

Notes:

7. One LSB of triangular PDF dither is added to data.

8. Performance limited by 16-bit quantization noise.

DS602F2 9

D/A DIGITAL FILTER CHARACTERISTICS

Fast Roll-Off Slow Roll-Off

Parameter

Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 10) Group Delay Passband Group Delay Deviation 0 - 20 kHz De-emphasis Error (Note 11) Fs = 32 kHz

(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 10) Group Delay Passband Group Delay Deviation 0 - 20 kHz

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 10) Group Delay Passband Group Delay Deviation 0 - 20 kHz

0 0

-0.01 - +0.01 -0.01 - +0.01 dB

0.5465 - - 0.5834 - - Fs 90 - - 64 - - dB

- 12/Fs - - 6.5/Fs - s

- - ±0.41/Fs - ±0.14/Fs s

0 0

-0.01 - 0.01 -0.01 - 0.01 dB

0.5834 - - 0.7917 - - Fs 80 - - 70 - - dB

- 4.6/Fs - - 3.9/Fs - s

- - ±0.03/Fs - ±0.01/Fs s

0 0

-0.01 - 0.01 -0.01 - 0.01 dB

0.6355 - - 0.8683 - - Fs 90 - - 75 - - dB

- 4.7/Fs - - 4.2/Fs - s

- - ±0.01/Fs - ±0.01/Fs s

0.4535

0.4998

±0.23 ±0.14 ±0.09

0.4166

0.4998

0.1046

0.4897

0 0

CS42416

UnitMin Typ Max Min Typ Max

0.4166

0.4998FsFs

±0.23 ±0.14 ±0.09

0.2083

0.4998FsFs

0.1042

0.4813FsFs

dB dB dB

Notes:

9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 39 to 62) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

10. Single- and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.

11. De-emphasis is available only in Single-Speed Mode.

10 DS602F2

CS42416

DAC_SCLK ADC_SCLK

(output)

RMCK

smd

lmd

DAC_LRCK ADC_LRCK

(output)

sckh

sckl

MSB

MSB-1

dpd

ADC_SDOUT

DAC_SDINx

lrpd

lrcks

lrckd

DAC_SCLK ADC_SCLK

(input)

DAC_LRCK ADC_LRCK

(input)

Figure 1. Serial Audio Port Master Mode Timing Figure 2. Serial Audio Port Slave Mode Timing

SWITCHING CHARACTERISTICS

(TA = -10 to +70° C; VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS,

= 30 pF)

Parameters Symbol Min Typ Max Units

RST Pin Low Pulse Width (Note 12)

PLL Clock Recovery Sample Rate Range

RMCK Output Jitter (Note 14)

RMCK Output Duty Cycle (Note 15)

OMCK Frequency (Note 13)

OMCK Duty Cycle (Note 13)

DAC_SCLK, ADC_SCLK Duty Cycle

DAC_LRCK, ADC_LRCK Duty Cycle

Master Mode

RMCK to DAC_SCLK, ADC_SCLK active edge delay

RMCK to DAC_LRCK, ADC_LRCK delay

Slave Mode

DAC_SCLK, ADC_SCLK Falling Edge to ADC_SDOUT, ADC_SDOUT Output Valid

DAC_LRCK, ADC_LRCK Edge to MSB Valid

DAC_SDIN Setup Time Before DAC_SCLK Rising Edge

DAC_SDIN Hold Time After DAC_SCLK Rising Edge

DAC_SCLK, ADC_SCLK High Time

DAC_SCLK, ADC_SCLK Low Time

DAC_SCLK, ADC_SCLK falling to DAC_LRCK, SAI_LRCK Edge

smd

lmd

dpd

lrpd

sckh

sckl

lrck

1--ms

30 - 200 kHz

- 200 - ps RMS

45 50 55 %

1.024 - 25.600 MHz

40 50 60 %

45 50 55 %

0-15ns

- (Note 16) ns

-26.5ns

10 - - ns

30 - - ns

20 - - ns

-25 - +25 ns

Notes:

12. After powering-up the CS42416, RST

should be held low after the power supplies and clocks are set-

tled.

13. See Table 1 on page 24 for suggested OMCK frequencies

14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.

15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 48 is set to Multiply by 2.

16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.

DS602F2 11

CS42416

256 Fs

---------------------

128 Fs

---------------------

64 Fs

------------------

buf

hdst

low

hdd

high

sud

Stop St art

SDA

SCL

irs

RST

hdst

sust

susp

Start

Stop

Repeated

ack

Figure 3. Control Port Timing - I²C Format

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT

(TA = -10 to +70° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC,

=30pF)

Parameter Symbol Min Max Unit

SCL Clock Frequency

Rising Edge to Start

RST

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low time

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling (Note 17)

SDA Setup time to SCL Rising

Rise Time of SCL and SDA

Fall Time SCL and SDA

Setup Time for Stop Condition

Acknowledge Delay from SCL Falling (Note 18)

hdst

low

high

sust

hdd

sud

susp

ack

scl

irs

buf

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs

0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

- (Note 19) ns

Notes:

17. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

19. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode

12 DS602F2

CS42416

dsu

sch

scl

CCLK

CDIN

css

CDOUT

csh

Figure 4. Control Port Timing - SPI Format

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT

(TA = -10 to +70° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC,

=30pF)

Parameter Symbol Min Typ Max Units

CCLK Clock Frequency

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time (Note 20)

CCLK Falling to CDOUT Stable

Rise Time of CDOUT

Fall Time of CDOUT

Rise Time of CCLK and CDIN (Note 21)

Fall Time of CCLK and CDIN (Note 21)

Notes:

20. Data must be held for sufficient time to bridge the transition time of CCLK.

21. For f

<1 MHz.

sck

csh

css

scl

sch

dsu

0-6.0MHz

1.0 - - s

20 - - ns

66 - - ns

40 - - ns

15 - - ns

--50ns

--25ns

--100ns

DS602F2 13

DC ELECTRICAL CHARACTERISTICS

(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)

Parameter Symbol Min Typ Max Units

Power Supply Current normal operation, VA = 5 V

(Note 22) VD = 5 V

VD = 3.3 V

Interface current, VLC=5 V (Note 23)

VLS=5 V

power-down state (all supplies) (Note 24)

Power Consumption (Note 22) VA=5 V, VD=VLS=VLC=3.3 V normal operation

power-down (Note 24)

VA=5 V, VD=VLS=VLC=5 V normal operation

power-down (Note 24)

Power Supply Rejection Ratio (Note 25) (1 kHz)

(60 Hz)

VQ Nominal Voltage VQ Output Impedance VQ Maximum allowable DC current

FILT+ Nominal Voltage FILT+ Output Impedance FILT+ Maximum allowable DC current

PSRR

75 85 51

250

587

1.25 866

1.25

60 40

2.7 50

0.01

5.0 35

0.01

650

960

CS42416

mA mA mA

A

mW mW mW mW

dB dB

k

Notes:

22. Current consumption increases with increasing FS and increasing OMCK. Max values are based on highest FS and highest OMCK. Variance between speed modes is negligible.

23. I

24. Power-Down Mode is defined as RST

measured with no external loading on the SDA pin.

pin = Low with all clock and data lines held static.

25. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 5.

14 DS602F2

DIGITAL INTERFACE CHARACTERISTICS

(TA = +25° C)

Parameters (Note 26) Symbol Min Typ Max Units

High-Level Input Voltage Serial Port

Control Port

Low-Level Input Voltage Serial Port

Control Port

High-Level Output Voltage at I

Low-Level Output Voltage at I Serial Port, Control Port, MUTEC, GPOx

High-Level Output Voltage at I

Low-Level Output Voltage at I

Input Leakage Current Input Capacitance MUTEC Drive Current

=2 mA (Note 27)Serial Port

Control Port

MUTEC, GPOx

=2 mA (Note 27)

=100 A (Note 27)Serial Port

Control Port

MUTEC, GPOx

=100 A (Note 27)Serial Port

Control Port

MUTEC, GPOx

CS42416

0.7xVLS

0.7xVLC

VLS-1.0

VLC-1.0

VA- 1.0

0.2xVLS

0.2xVLC

V V

V V V

--0.4V

0.8xVLS

0.8xVLC

0.8xVA

0.2xVLS

0.2xVLC

0.2xVA

V V V

--±10A

-8-pF

-3-mA

Notes:

26. Serial Port signals include: RMCK, OMCK, ADC_SCLK, ADC_LRCK, DAC_SCLK, DAC_LRCK, ADC_SDOUT, DAC_SDIN1-3, ADCI N 1/2 Con t rol Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS

, AD1/CDIN, INT, RST

27. When operating RMCK above 24.576 MHz, limit the loading on the signal to 1 CMOS load.

DS602F2 15

2. PIN DESCRIPTIONS

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

DAC_SDIN1

ADC_SCLK

ADC_LRCK

DGND

VLC

SCL/CCLK

SDA/CDOUT

AD1/CDIN

AD0/CS

INT

RST

AINR-

AINR+

AINL+

AINL-

FILT+

REFGND

NCNCNC

AGND

AOUTB3-

AOUTB3+

AOUTA3+

AOUTA3-

AOUTB2-

AOUTB2+

AOUTA2+

AOUTA2-

AOUTB1-

AOUTB1+

AOUTA1+

AOUTA1-

MUTEC

AGND

GPO7

GPO6

GPO5

GPO4

GPO3

GPO2

GPO1

LPFLT

DGND

VLS

RMCK

ADC_SDOUT

ADCIN2

ADCIN1

OMCK

DAC_LRCK

DAC_SCLK

TEST

DAC_SDIN3

DAC_SDIN2

CS42416

Pin Name # Pin Description

1 64 63

4 51

5 52

DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface.

DAC Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on

the DAC serial audio data line.

Digital Power (Input) - Positive power supply for the digital section.

Digital Ground (Input) - Ground reference. Should be connected to digital ground.

Control Port Power (Input) - Determines the required signal level for the control port.

Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up

resistor to the logic interface voltage in I²C mode as shown in the Typical Connection Diagram. Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up

resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output data line for the control port interface in SPI mode.

Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C mode; CDIN is the input data line for the control port interface in SPI mode.

Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS is the chip select signal in SPI mode.

Interrupt (Output) - The CS42416 will generate an interrupt condition as per the Interrupt Mask register. See “Interrupts” on page 37 for more details.

DAC_SDIN1 DAC_SDIN2 DAC_SDIN3

DAC_SCLK

DAC_LRCK

DGND

VLC

SCL/CCLK

SDA/CDOUT

AD1/CDIN

AD0/CS

INT

16 DS602F2

RST

AINRAINR+

AINL+ AINL-

FILT+

REFGND

AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,-

AGND

MUTEC

LPFLT

GPO7 GPO6 GPO5 GPO4 GPO3 GPO2 GPO1

VLS

RMCK

ADC_SDOUT

ADCIN1 ADCIN2

OMCK

ADC_LRCK

ADC_SCLK

TEST

Reset

13 14

15 16

36,37 35,34 32,33 31,30 28,29 27,26

24 41

25 40

42 43 44 45 46 47 48

58 57

(Input) - The device enters a low power mode and all internal registers are reset to their default

settings when low.

Differential Right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators via the AINR+/- pins.

Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators via the AINL+/- pins.

Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

Reference Ground (Input) - Ground reference for the internal sampling circuits.

Differential Analog Output (Output) - The full-scale differential analog output level is specified in the

Analog Characteristics specification table.

Analog Power (Input) - Positive power supply for the analog section.

Analog Ground (Input) - Ground reference. Should be connected to analog ground.

Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power-on con-

dition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.

PLL Loop Filter (Output) - An RC network should be connected between this pin and ground.

General Purpose Output (Output) - These pins can be configured as general purpose output pins, an

ADC overflow interrupt or Mute Control outputs according to the General Purpose Pin Control registers.

Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.

Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference

(OMCK, pin 59) or the PLL which is locked to the incoming ADC_LRCK. ADC Serial Data Output (Output) - Output for two’s complement serial audio PCM data from the output

of the internal and external ADCs. External ADC Serial Input (Input) - The CS42416 provides for up to two external stereo analog to digital

converter inputs to provide a maximum of six channels on one serial data output line when the CS42416 is placed in One-Line Mode.

External Reference Clock (Input) - External clock reference that must be within the ranges specified in the register “OMCK Frequency (OMCK Freqx)” on page 48.

ADC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the ADC serial audio data line.

ADC Serial Clock (Input/Output) - Serial clock for the ADC serial audio interface.

Test Pin (Input) - This pin must be connected to DGND.

CS42416

DS602F2 17

3. TYPICAL CONNECTION DIAGRAMS

VLS

AOUTA1+

100 µF

0.1 µF

FILT+

0.1 µF

4.7 µF

0.1 µF

+3.3 V

to +5.0 V

Analog Output Buff er

and

Mute Circuit (optional)

AOUTA1-

AOUTB1+

AOUTB1-

AOUTA2+

AOUTA2-

AOUTB2+

AOUTB2-

AOUTA3+

AOUTA3-

AOUTB3+

AOUTB3-

MUTEC

Mute Drive

(optional)

DGND

VLC

0.1 µF

+1.8V to +5V

SCL/CCLK

SDA/CDOUT

AD1/CDIN

RST

2 k

** Resistors are required for

C control port operation

OMCK

ADC_LRCK

REFGND

AD0/CS

INT

Digital Audio

Processor

Micro-

Controller

RMCK

ADCIN1

ADCIN2

CS5361

A/D Converter

CS5361

A/D Converter

ADC_SDOUT

AGNDAGND

52 40

CFILT

RFILT

LPFLT

CRIP

2700 pF*

AINL+

AINL-

AINR+

AINR-

Left Analog Input

Right Analog Input

1. See the ADC Input Filter section in the Appendix.

2. See the DAC Output Filter section in the Appendix.

3. See the PLL Filter section in the Appendix.

Connect DGND and AGND at single point near Codec

GPO1

GPO2

GPO3

GPO4

GPO5

GPO6

GPO7

DAC_SDIN1

ADC_SCLK

DAC_SDIN3

DAC_SDIN2

DAC_LRCK

DAC_SCLK

Analog

Input

Buffer

Analog

Input

Buffer

+VA

* Pull up or down as

required on startup if the

Mute Control is used .

0.1 µF

10 µF

51 41

VAVD

0.1 µF

0.01 µF

0.1 µF

10 µF

+5 V

0.01 µF

+3.3 V to +5 V

10 µF

0.1 µF 0.01 µF

S/PDIF

CS8416

Receiver

RMCK

OSC

Optional

2 k

** **

Analog Output Buff er

and

Mute Circuit (o ptional)

Analog Output Buf fer

and

Mute Circuit ( optional)

Analog Output Buff er

and

Mute Circuit (o ptional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buff er

and

Mute Circuit (o ptional)

Figure 5. Typical Connection Diagram

CS42416

18 DS602F2

CS42416

VLS

AOUTA1+

0.1 µF

10 µF

100 µF

0.1 µF

FILT+

0.1 µF

4.7 µF

10 µF

0.1 µF

AOUTA1-

AOUTB1+

AOUTB1-

AOUTA2+

AOUTA2-

AOUTB2+

AOUTB2-

AOUTA3+

AOUTA3-

AOUTB3+

AOUTB3-

MUTEC

DGND

VLC

0.1 µF

SCL/CCLK

SDA/CDOUT

AD1/CDIN

RST

OMCK

ADC_LRCK

REFGND

AD0/CS

INT

RMCK

ADCIN1

ADCIN2

ADC_SDOUT

VAVD

0.1 µF

AGNDAGND

52 40

LPFLT

AINL+

AINL-

AINR+

AINR-

GPO1

GPO2

GPO3

GPO4

GPO5

GPO6

GPO7

DAC_SDIN1

ADC_SCLK

DAC_SDIN3

DAC_SDIN2

DAC_LRCK

DAC_SCLK

0.01 µF

0.1 µF +

10 µF

+5 V

0.01 µF

+3.3 V to +5 V

10 µF

0.1 µF 0.01 µF

Analog Output Buffer

and

Mute Circuit (optional)

Mute Drive

(optional)

2700 pF*

Left Analog Input

Right Analog Input

Analog

Inpu t

Buffer

Analog

Inpu t

Buffer

+VA

* Pull up or down as

required on startup if the

Mu te Con trol is use d.

Analog Output Buffer

and

Mute Circuit (optional)

An alog Ou tpu t Bu ffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Analog Output Buffer

and

Mute Circuit (optional)

Connect DGND and AGND at single point near Codec

CFILT

RFILT

CRIP

2 k 2 k

** **

** Resistors are required for

C control port operation

1. S ee the A DC In put Filter sec tion in the Ap pendix .

2. S ee the D AC O utput F ilter sectio n in the A ppen dix.

3. See the PLL Filter section in the A ppendix.

+1.8 V

to +5 .0 V

DVD

Processor

27 MHz

Figure 6. Typical Connection Diagram using the PLL

CS42416

DS602F2 19

4. APPLICATIONS

AIN+

AIN-

Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp

4.1 V

2.7 V

1.3 V

4.1 V

2.7 V

1.3 V

Figure 7. Full-Scale Analog Input

4.1 Overview

The CS42416 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital converters (ADC), implemented using multi-bit delta-sigma techniques, and 6 digital-to-analog converters (DAC). Other functions integrated within the codec include independent digital volume controls for each DAC, digital de-emphasis filters for DAC, digital gain control for ADC channels, ADC high-pass filters, and an on-chip voltage reference. All serial data is transmitted through one configurable serial audio interface for the ADC with enhanced one-line modes of operation, allowing up to 6 channels of serial audio data on one data line. All functions are configured through a serial control port operable in SPI mode or in I²C mode.

Figure 5 and Figure 6 show the recommended connections for the CS42416.

The CS42416 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the FM bits in register “Functional Mode (address 03h)” on page 43. Single-Speed Mode (SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x.

Using the integrated PLL, a low-jitter clock is recovered from the ADC LRCK input signal. The recovered clock or an externally supplied clock attached to the OMCK pin can be used as the System Clock.

4.2 Analog Inputs

CS42416

4.2.1 Line-Level Inputs

AINR+, AINR-, AINL+, and AINL- are the line-level differential analog inputs. The analog signal must be externally biased to VQ, approximately 2.7 V, before being applied to these inputs. The level of the signal can be adjusted for the left and right ADC independently through the ADC Left and Right Channel Gain Control Registers on page 55. The ADC output data is in two’s complement binary format. For inputs above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC Overflow bit in the register “Interrupt Status (address 20h) (Read Only)” on

page 56 to be set to a ‘1’. The GPO pins may also be configured to indicate an overflow condition has

occurred in the ADC. See “General-Purpose Pin Control (addresses 29h to 2Fh)” on page 58 for proper configuration. Figure 7 shows the full-scale analog input levels. See “ADC Input Filter” on page 61 for a recommended input buffer.

20 DS602F2

4.2.2 High-Pass Filter and DC Offset Calibration

AOUT+

AOUT-

Full-Scale Output Level= (AIN+) - (AIN-)= 5 Vpp

3.95 V

2.7 V

1.45 V

3.95 V

2.7 V

1.45 V

Figure 8. Full-Scale Output

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. The high-pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by:

1. Running the CS42416 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time.

2. Disabling the high-pass filter and freezing the stored DC offset.

The high-pass filters are controlled using the HPF_FREEZE bit in the register “Misc Control (address

05h)” on page 46.

4.3 Analog Outputs

4.3.1 Line-Level Outputs and Filtering

The CS42416 contains on-chip buffer amplifiers capable of producing line-level differential outputs. These amplifiers are biased to a quiescent DC level of approximately VQ.

The delta-sigma conversion process produces high-frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low-pass filter. See “DAC Output Filter” on page 61 for a recommended output buffer. This filter configuration accounts for the normally differing AC loads on the AOUT+ and AOUT- differential output pins. It also shows an AC coupling configuration which minimizes the number of required AC coupling capacitors. Figure 8 shows the full-scale analog output levels.

CS42416

4.3.2 Interpolation Filter

To accommodate the increasingly complex requirements of digital audio systems, the CS42416 incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is avail-

DS602F2 21

able in Single-, Double-, and Quad-Speed Modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit found in the register “Misc Control (address 05h)”

on page 46 selects which filter is used. Filter response plots can be found in Figures 39 to 62.

4.3.3 Digital Volume and Mute Control



A Channel

Volume

Control

AOUTAx

AOUTBx

Left Channel

Audio Data

Right Channel

Audio Data

BChannel

Volume

Control

MUTE

DAC_SDINx

Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3)

Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to

-127 dB attenuation with 0.5 dB resolution. See “Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h,

14h)” on page 53. Volume control changes are programmable to ramp in increments of 0.125 dB at the

rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See “Volume Transition Control

(address 0Dh)” on page 51.

Each output can be independently muted via mute control bits in the register “Channel Mute (address

0Eh)” on page 52. When enabled, each XX_MUTE bit attenuates the corresponding DAC to its maximum

value (-127 dB). When the XX_MUTE bit is disabled, the corresponding DAC returns to the attenuation level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by the SZC[1:0] bits.

The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The Mute Control pin outputs high impedance during Power-Up or in Power-Down Mode by setting the PDN bit in the register “Power Control (address 02h)” on page 43 to a ‘1’. Once out of Power-Down Mode, the pin can be controlled by the user via the control port, or automatically asserted high when zero data is present on all DAC inputs, or when serial port clock errors are present. To prevent large transients on the output, it is desirable to mute the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin in the Pin Descriptions section for more information.

Each of the GPO1-GPO7 can be programmed to provide a hardware MUTE signal to individual circuits. Each pin can be programmed as an output, with specific muting capabilities as defined by the function bits in the register “General-Purpose Pin Control (addresses 29h to 2Fh)” on page 58.

CS42416

4.3.4 ATAPI Specification

The CS42416 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 14 on page 54 and Figure 9 for additional information.

22 DS602F2

4.4 Clock Generation

ADC_LRCK

(slave mo de)

PLL (256Fs)

8.192 -

49.152 MH z

PLL_LRCK bit

SW_CTRLx bits

(manual or auto

switch)

OMCK

Auto D etec t Input C lock

1,1.5, 2, 4

single

speed

256

double speed

128

quad

speed

single

speed

double speed

quad

speed

not OLM

OLM #1

DAC_FMx bits

ADC_FMx bits

DAC_OLx

or ADC_OLx bits

ADC_OLx and

ADC_SP SELx bits

ADC_SCLK

DAC_SCLK

DAC_LRCK

ADC_LRCK

RMCK

OLM #2

not OLM

OLM #1

OLM #2

128FS

256FS

128FS

256FS

Internal

MCLK

RMCK_DIVx bits

Figure 10. Clock Generation

The clock generation for the CS42416 is shown in the figure below. The internal MCLK is derived from the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock to the other source input.

CS42416

4.4.1 PLL and Jitter Attenuation

The PLL can be configured to lock onto the incoming ADC_LRCK signal from the ADC Serial Port and generate the required internal master clock frequency. There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed to have good jitter-attenuation characteristics. By setting the PLL_LRCK bit to a ‘1’ in the register “Clock

Control (address 06h)” on page 48, the PLL will lock to the incoming ADC_LRCK and generate an output

master clock (RMCK) of 256Fs. Table 2 shows the output of the PLL with typical input Fs values for ADC_LRCK.

See “Appendix B: PLL Filter” on page 62 for more information concerning PLL operation, required filter components, optimal layout guidelines, and jitter-attenuation characteristics.

DS602F2 23

4.4.2 OMCK System Clock Mode

Sample

Rate

(kHz)

OMCK (MHz)

Single-Speed

(4 to 50 kHz)

Double-Speed

(50 to 100 kHz)

Quad-Speed

(100 to 192 kHz)

256x 384x 512x 128x 192x 256x 64x 96x 128x

48 12.2880 18.4320 24.5760 - - - - - 96 - - - 12.2880 18.4320 24.5760 - - -

192 - - - - - - 12.2880 18.4320 24.5760

Table 1. Common OMCK Clock Frequencies

Sample

Rate

(kHz)

PLL Output (MHz)

Single-Speed

(4 to 50kHz)

Double-Speed (50 to 100kHz)

Quad-Speed

(100 to 192kHz)

256x 256x 256x

32 8.1920 - -

44.1 11.2896 - 48 12.2880 - 64 - 16.3840 -

88.2 - 22.5792 96 - 24.5760 -

176.4 - - 45.1584 192 - - 49.1520

A special clock-switching mode is available that allows the clock that is input through the OMCK pin to be used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register “Clock Con-

trol (address 06h)” on page 48. An advanced auto-switching mode is also implemented to maintain mas-

ter clock functionality. The clock auto-switching mode allows the clock input through OMCK to be used as a clock in the system without any disruption when the PLL loses lock, for example, when the LRCK is removed from ADC_LRCK. This clock-switching is done glitch-free. A clock adhering to the specifications detailed in the Switching Characteristics table on page 11 must be applied to the OMCK pin at all times that the FRC_PLL_LK bit is set to ‘0’ (See “Force PLL Lock (FRC_PLL_LK)” on page 49).

4.4.3 Master Mode

In Master Mode, the serial interface timings are derived from an external clock attached to OMCK or from the output of the PLL with an input reference to the ADC_LRCK input from the ADC serial port. The DAC Serial Port and ADC Serial Port can both be masters only when OMCK is used as the clock source. When using the PLL output, the ADC Serial Port must be slave and the DAC Serial Port can operate in Master Mode. Master clock selection and operation is configured with the SW_CTRL1:0 bits in the Clock Control Register (See “Clock Control (address 06h)” on page 48).

CS42416

4.4.4 Slave Mode

In Slave Mode, DAC_LRCK, DAC_SCLK and/or ADC_LRCK and ADC_SCLK operate as inputs. The Left/Right clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the supplied master clock, OMCK, or must be synchronous to the supplied ADC_LRCK used as the input to the PLL. In this latter scenario, the PLL output becomes the internal master clock. The supported PLL output frequencies are shown in Table 2.

24 DS602F2

The serial bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronous to the corresponding DAC_LRCK/ADC_LRCK and be equal to 128x, 64x, 48x or 32x Fs, depending on the interface format selected and desired speed mode.

When the device is clocked from OMCK, the frequency of OMCK must be at least twice the frequency of the fastest Slave Mode, SCLK. For example, if both serial ports are in Slave Mode with one SCLK running at 32x Fs and the other at 64x Fs, the slowest OMCK signal that can be used to clock the device is 128x Fs.

When either serial port is in Slave Mode, its respective LRCK signal must be present for proper device operation.

In Slave Mode, One-Line Mode #1 is supported; One-Line Mode #2 is not.

The sample rate to OMCK ratios and OMCK frequency requirements for Slave Mode operation are shown in Table 1. Refer to Table 3 for required clock ratios.

Single-Speed Double-Speed Quad-Speed One-Line Mode #1

OMCK/LRCK Ratio

SCLK/LRCK Ratio

256x, 384x, 512x 128x, 192x, 256x 64x, 96x, 128x 256x

32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x 128x

Table 3. Slave Mode Clock Ratios

4.5 Digital Interfaces

4.5.1 Serial Audio Interface Signals

The CS42416 interfaces to an external Digital Audio Processor via two independent serial ports, the DAC serial port, DAC_SP, and the ADC serial port, ADC_SP. The digital output of the internal ADCs use the ADC_SDOUT pin and can be configured to use either the ADC or DAC serial port timings. These configuration bits and the selection of Single-, Double- or Quad-Speed Mode for DAC_SP and ADC_SP are found in register “Functional Mode (address 03h)” on page 43.

CS42416

The serial interface clocks, ADC_SCLK for ADC_SP and DAC_SCLK for DAC_SP, are used for transmitting and receiving audio data. Either ADC_SCLK or DAC_SCLK can be generated by the CS42416 (Master Mode), or it can be input from an external source (Slave Mode). Master or Slave Mode selection is made using bits DAC_SP M/S

The Left/Right clock (ADC_LRCK or DAC_LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS42416 (Master Mode), or it may be generated by an external source (Slave Mode). As described in later sections, particular modes of operation do allow the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other.

The serial data interface format selection (Left/Right-Justified, I²S or One-Line Mode) for the ADC serial port data out pin, ADC_SDOUT, and the DAC input pins, DAC_SDIN1:3, is configured using the appropriate bits in the register “Interface Formats (address 04h)” on page 45. The serial audio data is presented in two's complement binary form with the MSB first in all formats.

DAC_SDIN1, DAC_SDIN2, and DAC_SDIN3 are the serial data input pins supplying the internal DAC. ADC_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs and, when configured for one-line mode, up to four additional ADC channels attached externally to the signals ADCIN1 and ADCIN2 (typically two CS5361 stereo ADCs). When operated in One-Line Mode, 6 channels of DAC data are input on DAC_SDIN1 and 6 channels of ADC data are output on ADC_SDOUT. Table 4 on page 26 outlines the serial port channel allocations.

and ADC_SP M/S in register “Misc Control (address 05h)” on page 46.

DS602F2 25

Serial Inputs / Outputs

DAC_SDIN1 left channel

right channel

One-Line Mode DAC_SDIN2 left channel

right channel

One-Line Mode

DAC_SDIN3 left channel

right channel

One-Line Mode

ADC_SDOUT left channel

right channel

One-Line Mode ADCIN1 left channel

right channel

ADCIN2 left channel

right channel

Table 4. Serial Audio Port Channel Allocations

CS42416

DAC #1 DAC #2 DAC channels 1,2,3,4,5,6

DAC #3 DAC #4 not used

DAC #5 DAC #6 not used

ADC #1 ADC #2 ADC channels 1,2,3,4,5,6

External ADC #3 External ADC #4

External ADC #5 External ADC #6

26 DS602F2

4.5.2 Serial Audio Interface Formats

Left Chann el

Right Channel

6543210987

15 14 13 12 11 10

6543210987

15 14 13 12 11 10

DAC_SDINx

ADC_SDOUT

DAC_LRCK ADC_LRCK

DAC_SCLK ADC_SCLK

Figure 11. Right-Justified Serial Audio Formats

Right-Justified Mode, Data Valid on Rising Edge of SCLK

Bits/Sample SCLK Rate(s) Notes

Master Slave

64 Fs 48, 64, 128 Fs Single-Speed Mode

64 Fs 64 Fs Double-Speed Mode

64 Fs 64 Fs Quad-Speed Mode

64, 128, 256 Fs 64, 128 Fs Single-Speed Mode

64 Fs 64 Fs Double-Speed Mode

64 Fs 64 Fs Quad-Speed Mode

The DAC_SP and ADC_SP digital audio serial ports support five formats with varying bit depths from 16 to 24 as shown in Figures 11 to 15. These formats are selected using the configuration bits in the registers,

“Functional Mode (address 03h)” on page 43 and “Interface Formats (address 04h)” on page 45. For the

diagrams below, Single-Speed Mode is equivalent to Fs = 32, 44.1, 48 kHz; Double-Speed Mode is for Fs = 64, 88.2, 96 kHz; and Quad-Speed Mode is for Fs = 176.4, 196 kHz.

CS42416

DS602F2 27

Left Channel

Right Channel

DAC_SDINx

ADC_SDOUT

+3 +2 +1+5 +4

-1

-2 -3 -4 -5

+3 +2 +1+5 +4

-1

-2 -3 -4

MSB

LSB LSB

DAC_LRCK ADC_LRCK

DAC_SCLK ADC_SCLK

Figure 12. I²S Serial Audio Formats

I²S Mode, Data Valid on Rising Edge of SCLK

Bits/Sample SCLK Rate(s) Notes

Master Slave

64 Fs 48, 64, 128 Fs Single-Speed Mode

64 Fs 64 Fs Double-Speed Mode

64 Fs 64 Fs Quad-Speed Mode

18 to 24

64, 128, 256 Fs 48, 64, 128 Fs Single-Speed Mode

64 Fs 64 Fs Double-Speed Mode

64 Fs 64 Fs Quad-Speed Mode

DAC_LRCK ADC_LRCK

DAC_SCLK ADC_SCLK

Left Channel

Right Channel

DAC_SDINx

ADC_SDOUT

+3 +2 +1+5 +4

-1 -2 -3 -4 -5

+3 +2 +1+5 +4

-1

-2 -3 -4

MSB LSB MSB LSB

Figure 13. Left-Justified Serial Audio Formats

Left-Justified Mode, Data Valid on Rising Edge of SCLK

Bits/Sample SCLK Rate(s) Notes

Master Slave

64 Fs 32, 48, 64, 128 Fs Single-Speed Mode

64 Fs 32, 64 Fs Double-Speed Mode

64 Fs 32, 64 Fs Quad-Speed Mode

18 to 24

64, 128, 256 Fs 48, 64, 128 Fs Single-Speed Mode

64 Fs 64 Fs Double-Speed Mode

64 Fs 64 Fs Quad-Speed Mode

CS42416

28 DS602F2

CS42416

DAC_LRCK ADC_LRCK

DAC_SCLK ADC_SCLK

LSBMSB

20 clks

64 clks 64 clks

LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB

DAC1 DAC3 DAC5 DAC2 DAC4 DAC6

20 clks

20 clks 20 clks 20 clks 20 clks

Left Channel Right Channel

20 clks

ADC1 ADC3 ADC5 ADC2 ADC4 ADC6

20 clks

20 clks 20 clks 20 clks 20 clks

ADC_SDOUT

DAC_SDIN1

Figure 14. One-Line Mode #1 Serial Audio Format

One Line Data Mode #1, Data Valid on Rising Edge of SCLK

Bits/Sample

SCLK Rate(s) Notes

Master Slave

128 Fs 128 Fs Single-Speed Mode

128 Fs 128Fs Double-Speed Mode

DAC_LRCK ADC_LRCK

DAC_SCLK ADC_SCLK

LSBMSB

24 clks

128 clks

LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB

DAC1 DAC3 DAC5 DAC2 DAC4 DAC6

24 clks

24 clks 24 clks 24 clks 24 clks

Left Channel Right Channel

24 clks

ADC1 ADC3 ADC5 ADC2 ADC4 ADC6

24 clks

24 clks 24 clks 24 clks 24 clks

ADC_SDOUT

128 clks

DAC_SDIN1

Figure 15. One-Line Mode #2 Serial Audio Format

One Line Data Mode #2, Data Valid on Rising Edge of SCLK

Bits/Sample SCLK Rate(s) Notes

Master Slave

24 256 Fs not supported Single-Speed Mode

DS602F2 29

4.5.3 ADCIN1/ADCIN2 Serial Data Format

DAC_LRCK ADC_LRCK

DAC_SCLK ADC_SCLK

Left Channel

Right Channel

ADCIN1/2

+3 +2 +1+5 +4

-1 -2 -3 -4 -5

+3 +2 +1+5 +4

-1

-2 -3 -4

MSB LSB MSB LSB

Figure 16. ADCIN1/ADCIN2 Serial Audio Format

Left-Justified Mode, Data Valid on Rising Edge of SCLK

Bits/Sample SCLK Rate(s) Notes

64, 128 Fs Single-Speed Mode, Fs= 32, 44.1, 48 KHz

64 Fs Double-Speed Mode, Fs= 64, 88.2, 96 KHz

not supported Quad-Speed Mode, Fs= 176.4, 192 KHz

The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port configuration register bit settings. These serial data lines are used when supporting One-Line Mode of operation with external ADCs attached. If these signals are not being used, they should be tied together and wired to GND via a pull-down resistor.

CS42416

For proper operation, the CS42416 must be configured to select which SCLK/LRCK is being used to clock the external ADCs. The EXT ADC SCLK bit in register “Misc Control (address 05h)” on page 46 must be set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the DAC_SP clocks. If the ADCs are wired to use the ADC_SP clocks, set this bit to ‘0’.

30 DS602F2

4.5.4 One-Line Mode (OLM) Configurations

SCLK_PORT1

LRCK_PORT1

SDIN_PORT1

SCLK_POR T2

LRCK_PORT2

SDOUT1_PORT2

SDOUT2_PORT2

SDOUT3_PORT2

ADC_SCLK

ADC_LRCK

DAC_SCLK

DAC_LRCK

ADC_SDOUT

DAC_SDIN1

DAC_SDIN2

DAC_SDIN3

RMCK

ADCIN1

ADCIN2

MCLK

SDOUT1

SDOUT2

LRCK

SCLK

64Fs

ADC Data

64Fs,128Fs, 256Fs

DIGITAL AUDIO

PROCESSOR

CS5361

MCLK

Figure 17. OLM Configuration #1

CS42416

4.5.4.1 OLM Config #1

One-Line Mode Configuration #1 can support up to 6 channels of DAC data, and 6 channels of ADC data. This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC.

Functional Mode Register (addr = 03h)

Set DAC_FMx = ADC_FMx = 00,01,10 Set ADC_CLK_SEL = 0

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Set ADC_OLx bits = 00,01,10

Set DAC_OLx bits = 00,01,10

Misc. Control Register (addr = 05h)

Set DAC_SP M/S = 1 Set ADC_SP M/S = 1

Set EXT ADC SCLK = 0

DAC_LRCK must equal ADC_LRCK; sample rate conversion not supported

Configure ADC_SDOUT to be clocked from the DAC_SP clocks.

Select the digital interface format when not in One-Line Mode

Select ADC operating mode, see table below for valid combinations

Select DAC operating mode, see table below for valid combinations

CS42416

Configure DAC Serial Port to Master Mode.

Configure ADC Serial Port to Master Mode.

Identify external ADC clock source as SAI Serial Port.

ADC Mode

Not One-

Line Mode

One-Line

Mode #1

One-Line

Mode #2

DAC Mode

Not One-Line Mode One-Line Mode #1 One-Line Mode #2

DAC_SCLK=64Fs DAC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs DAC_LRCK=SSM/DSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK

DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK

DAC_SCLK=128Fs DAC_LRCK=SSM/DSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK

not valid

DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=DAC_LRCK

DS602F2 31

4.5.4.2 OLM Config #2

SCLK_PORT1

LRCK_PORT1

SDIN_PORT1

SCLK_PORT2

LRCK_PORT2

SDOUT1_PORT2

SDOUT2_PORT2

SDOUT3_PORT2

RMCK

ADCIN1

ADCIN2

MCLK

SDOUT1

SDOUT2

LRCK

SCLK

64Fs,128Fs

ADC Data

64Fs,128Fs,

256Fs

DIGITAL AUDIO

PROCESSOR

CS5361

ADC_SCLK

ADC_LRCK

ADC_SDOUT

DAC_SCLK

DAC_LRCK

DAC_SDIN1

DAC_SDIN2

DAC_SDIN3

MCLK

Figure 18. OLM Configuration #2

CS42416

This configuration will support up to 6 channels of DAC data or 6 channels of ADC data and will handle up to 20-bit samples at a sampling-frequency of 96 kHz on all channels for both the DAC and ADC. The output data stream of the internal and external ADCs is configured to use the ADC_SDOUT output and run at the DAC Serial Port sample frequency.

Functional Mode Register (addr = 03h)

Set DAC_FMx = 00,01,10

Set ADC_FMx = 00,01,10

Set ADC_CLK_SEL = 1

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Set ADC_OLx bits = 00,01,10

Set DAC_OLx bits = 00,01

Misc. Control Register (addr = 05h)

Set DAC_SP M/S = 1

Set ADC_SP M/S = 1

Set EXT ADC SCLK = 1

CS42416

DAC_LRCK can run at SSM, DSM or QSM independent of ADC_LRCK

ADC_LRCK can run at SSM, DSM or QSM independent of DAC_LRCK

Configure ADC_SDOUT to be clocked from the ADC_SP clocks.

Select the digital interface format when not in One-Line Mode

Select ADC operating mode, see table below for valid combinations

Select DAC operating mode, see table below for valid combinations

Set DAC Serial Port to Master Mode.

Set ADC Serial Port to Master Mode.

Identify external ADC clock source as DAC Serial Port.

ADC Mode

Not One-

Line Mode

One-Line

Mode #1

One-Line

Mode #2

DAC Mode

Not One-Line Mode One-Line Mode #1 One-Line Mode #2

DAC_SCLK=64Fs DAC_LRCK=SSM/DSM/QSM ADC_SCLK=64Fs ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=64Fs DAC_LRCK=SSM/DSM ADC_SCLK=128Fs ADC_LRCK=DAC_LRCK

DAC_SCLK=64Fs DAC_LRCK=SSM ADC_SCLK=256Fs ADC_LRCK=DAC_LRCK

DAC_SCLK=128Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs DAC_LRCK=SSM ADC_SCLK=128Fs ADC_LRCK=DAC_LRCK

not valid not valid

not valid

32 DS602F2

4.5.4.3 OLM Config #3

SCLK_PORT1

LRCK_PORT1

SDIN_PORT1

SCLK_PORT2

LRCK_PORT2

SDOUT1_PORT2

SDOUT2_PORT2

SDOUT3_PORT2

RMCK

ADCIN1

ADCIN2

MCLK

SDOUT1

SDOUT2

LRCK

SCLK

64Fs,128Fs,256Fs

64Fs,128Fs

DIGITAL AUDIO

PROCESSOR

CS5361

ADC_SCLK

ADC_LRCK

ADC_SDOUT

DAC_SCLK

DAC_LRCK

DAC_SDIN1

DAC_SDIN2

DAC_SDIN3

MCLK

Figure 19. OLM Configuration #3

CS42416

This configuration will support up to 6 channels of DAC data and 6 channels of ADC data. OLM Config #3 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz. Since the ADC’s data stream is configured to use the ADC_SDOUT output and the internal and external ADCs are clocked from the ADC_SP, the sample rate for the DAC Serial Port can be different from the sample rate of the ADC serial port.

Functional Mode Register (addr = 03h)

Set DAC_FMx = 00,01,10

Set ADC_FMx = 00,01,10

Set ADC_CLK_SEL = 1

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Set ADC_OLx bits = 00,01

Set DAC_OLx bits = 00,01,10

Misc. Control Register (addr = 05h)

Set DAC_SP M/S = 1

Set ADC_SP M/S = 0 or 1

Set EXT ADC SCLK = 0

CS42416

DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK

ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK

Configure ADC_SDOUT to be clocked from the ADC_SP clocks.

Select the digital interface format when not in One-Line Mode

Select ADC operating mode, see table below for valid combinations

Select DAC operating mode, see table below for valid combinations

Set DAC Serial Port to Master Mode.

Set ADC Serial Port to Master Mode or Slave Mode.

Identify external ADC clock source as ADC Serial Port.

DAC Mode

Not One-Line Mode One-Line Mode #1 One-Line Mode #2

ADC Mode

Not One-

Line Mode

One-Line

Mode #1

One-Line

Mode #2

DAC_SCLK=64Fs DAC_LRCK=SSM/DSM/QSM ADC_SCLK=64Fs ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=64Fs DAC_LRCK=SSM/DSM/QSM ADC_SCLK=128Fs ADC_LRCK=SSM

not valid not valid not valid

DAC_SCLK=128Fs DAC_LRCK=SSM/DSM ADC_SCLK=64Fs ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs DAC_LRCK=SSM/DSM ADC_SCLK=128Fs ADC_LRCK=SSM

DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=128Fs ADC_LRCK=SSM

DS602F2 33

CS42416

4.5.4.4 OLM Config #4

This One-Line Mode configuration can support up to 6 channels of DAC data on 2 DAC_SDIN pins and 2 channels of ADC data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC. The output data stream of the internal ADCs can be configured to run at the DAC_SP clock speeds or to run at the ADC_SP rate. The DAC_SP and ADC_SP can operate at different Fs rates.

Functional Mode Register (addr = 03h)

Set DAC_FMx = 00,01,10 DAC_LRCK can run at SSM, DSM, or QSM independent of

ADC_LRCK

Set ADC_FMx = 00,01,10 ADC_LRCK can run at SSM, DSM, or QSM independent of

DAC_LRCK

Set ADC_CLK_SEL = 0 or 1 Configure ADC_SDOUT to be clocked from the ADC_SP or

DAC_SP clocks.

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format Select the digital interface format when not in One-Line Mode

Set ADC_OLx bits = 00 Set ADC operating mode to Not One-Line Mode since only 2

channels of ADC are supported

Set DAC_OLx bits = 00,01,10 Select DAC operating mode, see table below for valid combina-

tions

Misc. Control Register (addr = 05h)

Set DAC_SP M/S = 0 or 1 Set DAC Serial Port to Master Mode or Slave Mode.

Set ADC_SP M/S = 0 or 1 Set ADC Serial Port to Master Mode or Slave Mode.

Set EXT ADC SCLK = 0 External ADCs are not used. Leave bit in default state.

ADC Mode

Not One-

Line Mode

One-Line

Mode #1

One-Line

Mode #2

DAC Mode

Not One-Line Mode One-Line Mode #1 One-Line Mode #2

DAC_SCLK=64Fs/128Fs DAC_LRCK=SSM/DSM/QSM ADC_SCLK=64Fs/128Fs ADC_LRCK=SSM/DSM/QSM

not valid not valid not valid

DAC_SCLK=128Fs DAC_LRCK=SSM/DSM ADC_SCLK=64Fs/128Fs ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=256Fs DAC_LRCK=SSM ADC_SCLK=64Fs/128Fs ADC_LRCK=SSM/DSM/QSM

34 DS602F2

4.6 Control Port Description and Timing

SCLK_PORT1

LRCK_PORT1

SDIN_PORT1

SDIN_PORT2

SCLK_PORT2

LRCK_PORT2

SDOUT1_PORT2

SDOUT2_PORT2

SDOUT3_PORT2

RMCK

ADCIN1

ADCIN2

64Fs,128Fs, 256Fs

DIGITAL AUDIO

PROCESSOR

ADC_SCLK

ADC_LRCK

ADC_SDOUT

DAC_SCLK

DAC_LRCK

DAC_SDIN1

DAC_SDIN2

DAC_SDIN3

64Fs,128Fs

MCLK

Figure 20. OLM Configuration #4

CS42416

The control port is used to access the registers, allowing the CS42416 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.

CS42416

The control port has two modes: SPI and I²C, with the CS42416 acting as a slave device. SPI mode is selected if there is a high-to-low transition on the AD0/CS mode is selected by connecting the AD0/CS

pin through a resistor to VLC or DGND, thereby permanently

pin after the RST pin has been brought high. I²C

selecting the desired AD0 bit address state.

4.6.1 SPI Mode

In SPI mode, CS is the CS42416 chip-select signal; CCLK is the control port bit clock (input into the CS42416 from the microcontroller); CDIN is the input data line from the microcontroller, and CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.

Figure 21 shows the operation of the control port in SPI mode. To write to a register, bring CS

low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W

), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired.

There is a MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS as desired. To begin a read, bring CS

DS602F2 35

The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear consecutively.

high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not,

low, send out the chip address and set the read/write bit (R/W) high.

4.6.2 I²C Mode

MAP

MSB

LSB

DATA

byte 1

byte n

R/W

ADDRESS

CHIP

ADDRESS

CHIP

CDIN

CCLK

CDOUT

MSB

LSB

MSB

LSB

1001111

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

Figure 21. Control Port Timing in SPI Mode

4 5 6 7 24 25

SCL

CHIP ADDRESS (WRITE) MAP BYTE DATA

DATA +1

START

ACK

STOP

ACKACKACK

1 0 0 1 1 AD1 AD0 0

SDA

INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0

0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28

DATA +n

Figure 22. Control Port Timing, I²C Write

In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS42416 is being reset.

The signal timings for a read and write cycle are shown in Figure 22 and Figure 23. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42416 after a Start condition consists of a 7-bit chip address field and a R/W for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42416, the chip address field, which is the first byte sent to the CS42416, should match 10011, followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS42416 after each input byte is read and is input to the CS42416 from the microcontroller after each transmitted byte.

CS42416

pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should

bit (high for a read, low

bit. If the operation is a write, the

36 DS602F2

CS42416

SCL

CHIP ADDRESS (W RITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

1 0 0 1 1 AD1 AD0 0

SDA

1 0 0 1 1 AD1 AD0 1

CHIP ADDRESS (READ)

START

INCR 6 5 4 3 2 1 0

7 0 7 0 7 0

168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24

26 27 28

2 3 10 11 17 18 19 2 5

ACK

DATA + n

STOP

Figure 23. Control Port Timing, I²C Read

Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 23, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition.

Send 10011xx0 (chip address & write operation).

Receive acknowledge bit.

Send MAP byte, auto increment off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 10011xx1(chip address & read operation).

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.

4.7 Interrupts

The CS42416 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with no active pull-up transistor. This last mode is used for active low, wired-OR hook-ups, with multiple peripherals connected to the microcontroller interrupt input pin.

Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Interrupt

Status (address 20h) (Read Only)” on page 56). Each source may be masked off through mask register bits.

In addition, each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer.

DS602F2 37

4.8 Reset and Power-Up

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be activated if the analog or digital supplies drop below the recommended operating condition to prevent power-glitch-related issues.

CS42416

When RST control port and registers, and the outputs are muted. When RST tional, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control Register will then cause the part to leave the low-power state and begin operation. If the internal PLL is selected as the clock source, the serial audio outputs will be enabled after the PLL has settled (see “Power Control (address 02h)” on page 43 for more details).

The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RST much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time delay of approximately 80 ms is required after applying power to the device or after exiting a reset state. During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.

is low, the CS42416 enters a low-power mode and all internal states are reset, including the

4.9 Power Supply, Grounding, and PCB Layout

As with any high-resolution converter, the CS42416 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 5 and 6 show the recommended power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD.

For applications where the output of the PLL is required to be low jitter, use a separate, low-noise analog +5 V supply for VA, decoupled to AGND. In addition, a separate region of analog ground plane around the FILT+, VQ, LPFLT, REFGND, AGND, and VA pins is recommended.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42416 as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42416 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB42428 evaluation board demonstrates the optimum layout and power supply arrangements.

is high, the control port becomes opera-

pin high. However, the voltage reference will take

38 DS602F2

CS42416

5. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

01h

02h

03h

04h

05h

06h

07h

08h

09h-

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

page 42

default Power Control

page 43

default Functional Mode

page 43

default Interface Formats

page 45

default

Misc Control

page 46

default Clock Con-

trol

page 48

default OMCK/PLL_ CLK Ratio

page 49

default Clock Status

page 50

default

Reserved

default X X X X X X X X Volume Control

page 51

default Channel Mute

page 52

default Vol. Control A1

page 53

default Vol. Control B1

page 53

default Vol. Control A2

page 53

default Vol. Control B2

page 53

default

Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0

1110XXXX

Reserved PDN_PLL PDN_ADC Reserved PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN

0 0 00000 1

DAC_FM1 DAC_FM0 ADC_FM1 ADC_FM0 Reserved ADC_CLK

0 0 00000 0

DIF1 DIF0 ADC_OL1 ADC_OL0 DAC_OL1 DAC_OL0 Reserved CODEC_RJ16

0 1 00000 0

Ext ADC

SCLK

0 0 00000 0

RMCK_DIV1 RMCK_DIV0 OMCK

0 0 00000 0

RATIO7 RATIO6 RATIO5 RATIO4 RATIO3 RATIO2 RATIO1 RATIO0

XXXXXXX X

Reserved Reserved Reserved Reserved Active_CLK PLL_CLK2 PLL_CLK1 PLL_CLK0

XXXXXXX X

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Reserved SNGVOL SZC1 SZC0 AMUTE Reserved RAMP_UP RAMP_DN

0 0 00100 0

Reserved Reserved B3_MUTE A3_MUTE B2_MUTE A2_MUTE B1_MUTE A1_MUTE

0 0 00000 0

A1_VOL7 A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0

0 0 00000 0

B1_VOL7 B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0

0 0 00000 0

A2_VOL7 A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0

0 0 00000 0

B2_VOL7 B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0

0 0 00000 0

HiZ_RMCK Reserved FREEZE FILTSEL HPF_

Freq1

OMCK

Freq0

PLL_LRCK SW_CTRL1 SW_CTRL0 FRC_PLL_LK

SEL

FREEZE

DAC_DEM Reserved

DAC_SP

M/S

ADC_SP

M/S

DS602F2 39

CS42416

Addr Function 7 6 5 4 3 2 1 0

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

Vol. Control A3

page 53

default Vol. Control B3

page 53

default Reserved

page 53

default Reserved

page 53

default Channel Invert

page 53

default Mixing Ctrl Pair 1

page 53

default Mixing Ctrl Pair 2

page 53

default Mixing Ctrl Pair 3

page 53

default Reserved

page 53

default ADC Left Ch. Gain

page 55

default ADC Right Ch. Gain

page 55

default Interrupt Control

page 55

default Reserved

default Interrupt Status

page 56

default Interrupt Mask

page 57

default Interrupt Mode MSB

page 57

default

A3_VOL7 A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0

0 0 00000 0

B3_VOL7 B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0

0 0 00000 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0 0 00000 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0 0 00000 0

Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

0 0 00000 0

P1_A=B Reserved Reserved P1_ATAPI4 P1_ATAPI3 P1_ATAPI2 P1_ATAPI1 P1_ATAPI0

0 0 00100 1

P2_A=B Reserved Reserved P2_ATAPI4 P2_ATAPI3 P2_ATAPI2 P2_ATAPI1 P2_ATAPI0

0 0 00100 1

P3_A=B Reserved Reserved P3_ATAPI4 P3_ATAPI3 P3_ATAPI2 P3_ATAPI1 P3_ATAPI0

0 0 00100 1

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0 0 00100 1

Reserved Reserved LGAIN5 LGAIN4 LGAIN3 LGAIN2 LGAIN1 LGAIN0

0 0 00000 0

Reserved Reserved RGAIN5 RGAIN4 RGAIN3 RGAIN2 RGAIN1 RGAIN0

0 0 00000 0

SP_SYNC Reserved DE-EMPH1 DE-EMPH0 INT1 INT0 Reserved Reserved

0 0 00000 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0 0 00000 0

UNLOCK Reserved Reserved Reserved Reserved Reserved OverFlow Reserved

XXXXXXX X

UNLOCKM Reserved Reserved Reserved Reserved Reserved OverFlowM Reserved

0 0 00000 0

UNLOCK1 Reserved Reserved Reserved Reserved Reserved OF1 Reserved

0 0 00000 0

40 DS602F2

CS42416

Addr Function 7 6 5 4 3 2 1 0

23h

24h-

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

Interrupt Mode LSB

page 57

default

Reserved

default

MUTEC

page 57

default GPO7

page 58

default GPO6

page 58

default GPO5

page 58

default GPO4

page 58

default GPO3

page 58

default GPO2

page 58

default GPO1

page 58

default

UNLOCK0 Reserved Reserved Reserved Reserved Reserved OF0 Reserved

0 0 00000 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0 0 00000 0

Reserved Reserved MCPolarity M_AOUTA1 M_AOUTB1 M_AOUTA2

M_AOUTB2

0 0 01111 1

Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0

0 0 00000 0

Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0

0 0 00000 0

Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0

0 0 00000 0

Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0

0 0 00000 0

Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0

0 0 00000 0

Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0

0 0 00000 0

Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0

0 0 00000 0

M_AOUTA3 M_AOUTB3

Reserved

DS602F2 41

CS42416

6. REGISTER DESCRIPTION

All registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, Clock Status and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description.

6.1 Memory Address Pointer (MAP)

Not a register

76543210

INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0

6.1.1 INCREMENT (INCR)

Default = 1

Function:

Memory Address Pointer auto increment control

0 - MAP is not incremented automatically. 1 - Internal MAP is automatically incremented after each read or write.

6.1.2 MEMORY ADDRESS POINTER (MAPX)

Default = 0000001

Function:

Memory Address Pointer (MAP). Sets the register address that will be read or written by the control port.

6.2 Chip I.D. and Revision Register (address 01h) (Read Only)

76543210

Chip_ID3 Chip_ID2 Chip_ID1 CHIP_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0

6.2.1 CHIP I.D. (CHIP_IDX)

Default = 1110

Function:

I.D. code for the CS42416. Permanently set to 1110.

6.2.2 CHIP REVISION (REV_IDX)

Default = xxxx

Function:

CS42416 revision level.

Revision C1 is coded as 0101 Revision C is coded as 0011.

42 DS602F2

CS42416

6.3 Power Control (address 02h)

76543210

Reserved PDN_PLL PDN_ADC Reserved PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN

6.3.1 POWER DOWN PLL (PDN_PLL)

Default = 0 Function:

When enabled, the PLL is held in a reset state. It is advised that any change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility of audible artifacts.

6.3.2 POWER DOWN ADC (PDN_ADC)

Default = 0

Function:

When enabled the stereo analog to digital converter will remain in a reset state. It is advised that any change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility of audible artifacts.

6.3.3 POWER DOWN DAC PAIRS (PDN_DACX)

Default = 0

Function:

When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.

6.3.4 POWER DOWN (PDN)

Default = 1

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur.

6.4 Functional Mode (address 03h)

76543210

DAC_FM1 DAC_FM0 ADC_FM1 ADC_FM0 Reserved ADC_SP SEL DAC_DEM Reserved

6.4.1 DAC FUNCTIONAL MODE (DAC_FMX)

Default = 00

00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 192 kHz sample rates) 11 - Reserved Function:

Selects the required range of sample rates for all converters clocked from the DAC serial port (DAC_SP). Bits must be set to the corresponding sample rate range when the DAC_SP is in Master or Slave Mode.

DS602F2 43

6.4.2 ADC FUNCTIONAL MODE (ADC_FMX)

Default = 00

00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 192 kHz sample rates) 11 - Reserved Function:

Selects the required range of sample rates for the ADC serial port (ADC_SP). These bits must be set to the corresponding sample rate range when the ADC_SP is in Master or Slave Mode.

6.4.3 ADC CLOCK SOURCE SELECT (ADC_CLK SEL)

Default = 0

0 - ADC_SDOUT clocked from the DAC_SP. 1 - ADC_SDOUT clocked from the ADC_SP. Function:

Selects the desired clocks for the ADC serial output.

6.4.4 DAC DE-EMPHASIS CONTROL (DAC_DEM)

Default = 0

Function:

CS42416

Enables the digital filter to maintain the standard 15s/50s digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a ‘1’b, the auto-detect sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-EMPH bits in the Interrupt Control (address 1Eh) register to set the appropriate sample rate.

DAC_DEM

reg03h[1]

0 X XX No De-Emphasis 1 0 XX Auto-Detect Fs 11 00

FRC_PLL_LK

reg06h[0]

Table 5. DAC De-Emphasis

DE-EMPH[1:0]

reg1Eh[5:4]

01 10 11

De-Emphasis

Mode

Reserved

32 kHz

44.1 kHz 48 kHz

44 DS602F2

CS42416

6.5 Interface Formats (address 04h)

76543210

DIF1 DIF0 ADC_OL1 ADC_OL0 DAC_OL1 DAC_OL0 Reserved CODEC_RJ16

6.5.1 DIGITAL INTERFACE FORMAT (DIFX)

Default = 01

Function:

These bits select the digital interface format used for the ADC & DAC Serial Port when not in One-Line Mode. The required relationship between the Left/Right clock, serial clock, and serial data is defined by the Digital Interface Format and the options are detailed in Figures 11-13.

DIF1 DIF0 Description Format Figure

00 01 10 11

Left-Justified, up to 24-bit data I²S, up to 24-bit data Right-Justified, 16-bit or 24-bit data Reserved

Table 6. Digital Interface Formats

0 13 1 2 11

6.5.2 ADC ONE_LINE MODE (ADC_OLX)

Default = 00

Function:

These bits select which mode the ADC will use. By default, One-Line Mode is disabled, but it can be selected using these bits. Please see Figures One-Line Mode 2.

ADC_OL1 ADC_OL0 Description Format Figure

00 01

DIF: take the DIF setting from reg04h[7:6] One-Line #1 One-Line #2

Reserved

Table 7. ADC One-Line Mode

6.5.3 DAC ONE_LINE MODE (DAC_OLX)

Default = 00

Function:

These bits select which mode the DAC will use. By default, One-Line Mode is disabled, but it can be selected using these bits. Please see Figures One-Line Mode 2.

DAC_OL1 DAC_OL0 Description Format Figure

00 01

DIF: take the DIF setting from reg04h[7:6] One-Line #1

One-Line #2 Reserved

Table 8. DAC One-Line Mode

14 and 15 to see the format of One-Line Mode 1 and

-3

14 15

14 and 15 to see the format of One-Line Mode 1 and

-3

14 15

DS602F2 45

CS42416

6.5.4 CODEC RIGHT-JUSTIFIED BITS (CODEC_RJ16)

Default = 0

Function:

This bit determines how many bits to use during Right-Justified Mode for the DAC and ADC. By default, the DAC and ADC will be in RJ24 bits, but can be set to RJ16 bits.

0 - 24 bit mode. 1 - 16 bit mode.

6.6 Misc Control (address 05h)

76543210

Ext ADC SCLK HiZ_RMCK Reserved FREEZE FILT_SEL HPF_FREEZE DAC_SP

M/S

6.6.1 EXTERNAL ADC SCLK SELECT (EXT ADC SCLK)

Default = 0

Function:

This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using One-Line Mode of operation.

ADC_SP

M/S

0 - ADC_SCLK is used as external ADC SCLK. 1 - DAC_SCLK is used as external ADC SCLK.

6.6.2 RMCK HIGH IMPEDANCE (HIZ_RMCK)

Default = 0

Function:

This bit is used to create a high-impedance output on RMCK when the clock signal is not required.

6.6.3 FREEZE CONTROLS (FREEZE)

Default = 0

Function:

This function will freeze the previous output of, and allow modifications to be made to, the Volume Control (address 0Fh-16h), Channel Invert (address 17h), and Mixing Control Pair (address 18h-1Bh) registers without the changes taking effect until the FREEZE is disabled. To make multiple changes in these control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

46 DS602F2

6.6.4 INTERPOLATION FILTER SELECT (FILT_SEL)

Default = 0

Function:

This feature allows the user to select whether the DAC interpolation filter has a fast- or slow roll-off. For filter characteristics, please See “D/A Digital Filter Characteristics” on page 10.

0 - Fast roll-off. 1 - Slow roll-off.

6.6.5 HIGH-PASS FILTER FREEZE (HPF_FREEZE)

Default = 0

Function:

When this bit is set, the internal high-pass filter for the selected channel will be disabled. The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “A/D Dig-

ital Filter Characteristics” on page 8.

CS42416

6.6.6 DAC SERIAL PORT MASTER/SLAVE SELECT (DAC_SP M/S

Default = 0

Function:

In Master Mode, DAC_SCLK and DAC_LRCK are outputs. Internal dividers will divide the master clock to generate the serial clock and left/right clock. In Slave Mode, DAC_SCLK and DAC_LRCK become inputs.

If the DAC_SP is in Slave Mode, DAC_LRCK must be present for proper device operation.

6.6.7 ADC SERIAL PORT MASTER/SLAVE SELECT (ADC_SP M/S

Default = 0

Function:

In Master Mode, ADC_SCLK and ADC_LRCK are outputs. Internal dividers will divide the master clock to generate the serial clock and left/right clock. In Slave Mode, ADC_SCLK and ADC_LRCK become inputs.

If the ADC_SP is in Slave Mode, ADC_LRCK must be present for proper device operation.

To use the PLL to lock to ADC_LRCK, the ADC_SP must be in Slave Mode. When using the PLL to lock to LRCK, if ADC_SDOUT is configured to be clocked by the ADC_SP, both ADC_SCLK and ADC_LRCK must be present. If ADC_SDOUT is configured to be clocked by the DAC_SP, only the ADC_LRCK signal must be applied.

)

DS602F2 47

CS42416

6.7 Clock Control (address 06h)

76543210

RMCK_DIV1 RMCK_DIV0 OMCK Freq1 OMCK Freq0 PLL_LRCK SW_CTRL1 SW_CTRL0 FRC_PLL_LK

6.7.1 RMCK DIVIDE (RMCK_DIVX)

Default = 00

Function:

Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.

RMCK_DIV1 RMCK_DIV0 Description

00 01 10 11

Table 9. RMCK Divider Settings

6.7.2 OMCK FREQUENCY (OMCK FREQX)

Default = 00

Function:

Divide by 1 Divide by 2 Divide by 4

Multiply by 2

Sets the appropriate frequency for the supplied OMCK.

OMCK Freq1 OMCK Freq0 Description

0 0 11.2896 MHz or 12.2880 MHz 0 1 16.9344 MHz or 18.4320 MHz 1 0 22.5792 MHz or 24.5760 MHz 11Reserved

Table 10. OMCK Frequency Settings

6.7.3 PLL LOCK TO LRCK (PLL_LRCK)

Default = 0 0 - Disabled 1 - Enabled

Function:

When enabled, the internal PLL of the CS42416 will lock to the ADC_LRCK of the ADC serial port (ADC_LRCK) while the ADC_SP is in Slave Mode.

48 DS602F2

6.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX)

Default = 00

Function:

These two bits, along with the UNLOCK bit in register “Interrupt Status (address 20h) (Read Only)”

on page 56, determine the master clock source for the CS42416. When SW_CTRL1 and SW_CTRL0

are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes unlocked, RMCK will equal OMCK, but all internal and serial port timings are not valid.

When the FRC_PLL_LK bit is set to ‘1’b, the SW_CTRLX bits must be set to ‘00’b. If the PLL becomes unlocked when the FRC_PLL_LK bit is set to ‘1’b, RMCK will not equal OMCK.

SW_CTRL1 SW_CTRL0 UNLOCK Description

0 0 X Manual setting, MCLK sourced from PLL. 0 1 X Manual setting, MCLK sourced from OMCK.

Table 11. Master Clock Source Select

0 1

Hold, keep same MCLK source.Auto switch, MCLK sourced from OMCK.

Auto switch, MCLK sourced from PLL. Auto switch, MCLK sourced from OMCK.

6.7.5 FORCE PLL LOCK (FRC_PLL_LK)

CS42416

Default = 0

Function:

This bit is used to enable the PLL to lock to the ADC_LRCK with the absence of a clock signal on OMCK. When set to a ‘1’b, the auto-detect sample frequency feature will be disabled and the SW_CTRLX bits must be set to ‘00’b. The OMCK/PLL_CLK Ratio (address 07h) (Read Only) register contents are not valid, and the PLL_CLK[2:0] bits will be set to ‘111’b. Use the DE-EMPH[1:0] bits to properly apply de-emphasis filtering.

6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only)

76543210

RATIO7(2

6.8.1 OMCK/PLL_CLK RATIO (RATIOX)

)RATIO6(20)RATIO5(2-1)RATIO4(2-2) RATIO3(2-3)RATIO2(2-4) RATIO1(2-5)RATIO0(2-6)

Default = xxxxxxxx

Function:

This register allows the user to find the exact absolute frequency of the recovered MCLK coming from the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.

DS602F2 49

CS42416

6.9 Clock Status (address 08h) (Read Only)

76543210

Reserved Reserved Reserved Reserved Active_CLK PLL_CLK2 PLL_CLK1 PLL_CLK0

6.9.1 SYSTEM CLOCK SELECTION (ACTIVE_CLK)

Default = x 0 - Output of PLL 1 - OMCK

Function:

This bit identifies the source of the internal system clock (MCLK).

6.9.2 PLL CLOCK FREQUENCY (PLL_CLKX)

Default = xxx

Function:

The CS42416 detects the ratio between the OMCK and the recovered clock from the PLL. Given the absolute frequency of OMCK, this ratio may be used to determine the absolute frequency of the PLL clock.

If a 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz clock is applied to OMCK and the OMCK_FREQX bits are set accordingly (see “OMCK Frequency (OMCK Freqx)” on page 48), the absolute frequency of the PLL clock is reflected in the PLL_CLKX bits according to Table 14. If the absolute frequency of the PLL clock does not match one of the frequencies given in Table 14, these bits will reflect the clos- est available value.

If the frequency of OMCK is not equal to 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz, the contents of the PLL_CLKX bits will be inaccurate and should be disregarded. In this case, an external controller may use the contents of the OMCK/PLL_CLK ratio register and the known OMCK frequency to determine the absolute frequency of the PLL clock.

Note: These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.

PLL_CLK2 PLL_CLK1 PLL_CLK0 Description

0 0 0 8.1920 MHz 0 0 1 11.2896 MHz 0 1 0 12.288 MHz 0 1 1 16.3840 MHz 1 0 0 22.5792 MHz 1 0 1 24.5760 MHz 1 1 0 45.1584 MHz 1 1 1 49.1520 MHz

Table 12. PLL Clock Frequency Detection

50 DS602F2

CS42416

6.10 Volume Transition Control (address 0Dh)

76543210

Reserved SNGVOL SZC1 SZC0 AMUTE MUTE

ADC_SP

6.10.1 SINGLE VOLUME CONTROL (SNGVOL)

Default = 0

Function:

The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control register and the other Volume Control registers are ignored.

6.10.2 SOFT RAMP AND ZERO CROSS CONTROL (SZCX)

Default = 00

00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function:

RAMP_UP RAMP_DN

Immediate Change

When Immediate Change is selected, all level changes will take effect immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level-change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

Soft Ramp

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.

Soft Ramp on Zero Crossing

Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

DS602F2 51

6.10.3 AUTO-MUTE (AMUTE)

Default = 1

0 - Disabled 1 - Enabled Function:

The digital-to-analog converters of the CS42416 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained, and the MUTEC pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).

6.10.4 SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)

Default = 0

0 - Disabled 1 - Enabled Function:

An un-mute will be performed after executing a filter mode change, after a MCLK/LRCK ratio change or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an immediate un-mute is performed in these instances.

CS42416

Note: For best results, it is recommended that this bit be used in conjunction with the RMP_DN bit.

6.10.5 SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)

Default = 0

0 - Disabled 1 - Enabled Function:

A mute will be performed prior to executing a filter mode or de-emphasis mode change. When this feature is enabled, this mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an immediate mute is performed prior to executing a filter mode or de-emphasis mode change.

Note: For best results, it is recommended that this bit be used in conjunction with the RMP_UP bit.

6.11 Channel Mute (address 0Eh)

76543210

Reserved Reserved B3_MUTE A3_MUTE B2_MUTE A2_MUTE B1_MUTE A1_MUTE

6.11.1 INDEPENDENT CHANNEL MUTE (XX_MUTE)

Default = 0

0 - Disabled 1 - Enabled Function:

The digital-to-analog converter outputs of the CS42416 will mute when enabled. The quiescent voltage on the outputs will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]).

52 DS602F2

CS42416

6.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h)

76543210

xx_VOL7 xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0

6.12.1 VOLUME CONTROL (XX_VOL)

Default = 0

Function:

The Digital Volume Control registers allow independent control of the signal levels in 0.5 dB increments from 0 to -127 dB. Volume settings are decoded as shown in Table 13. The volume changes are implemented as dictated by the Soft and Zero Cross bits (SZC[1:0]). All volume settings less than

-127 dB are equivalent to enabling the MUTE bit for the given channel.

Binary Code Decimal Value Volume Setting

00000000 0 0 dB 00101000 40 -20 dB 01010000 80 -40 dB

01111000 1 2 0 -60 dB

10110100 180 -90 dB

Table 13. Example Digital Volume Settings

6.13 Channel Invert (address 17h)

76543210

Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

6.13.1 INVERT SIGNAL POLARITY (INV_XX)

Default = 0

0 - Disabled 1 - Enabled Function:

When enabled, these bits will invert the signal polarity of their respective channels.

6.14 Mixing Control Pair 1 (Channels A1 & B1) (address 18h) Mixing Control Pair 2 (Channels A2 & B2) (address 19h) Mixing Control Pair 3 (Channels A3 & B3) (address 1Ah)

76543210

Px_A=B Reserved Reserved Px_ATAPI4 Px_ATAPI3 Px_ATAPI2 Px_ATAPI1 Px_ATAPI0

6.14.1 CHANNEL A VOLUME = CHANNEL B VOLUME (PX_A=B)

Default = 0

0 - Disabled 1 - Enabled Function:

The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control registers when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Volume Control registers (per A-B pair), and the B Channel Volume Control registers are ignored when this function is enabled.

DS602F2 53

6.14.2 ATAPI CHANNEL-MIXING AND MUTING (PX_ATAPIX)

Default = 01001

Function:

The CS42416 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 14 and Figure 9 for additional information.

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx

00000 MUTE MUTE 00001 MUTE bR 00010 MUTE bL 00011 MUTE b[(L+R)/2] 00100 aR MUTE 00101 aR bR 00110 aR bL 00111 aR b[(L+R)/2] 01000 aL MUTE 01001 aL bR 01010 aL bL 01011 aL b[(L+R)/2] 01100 a[(L+R)/2] MUTE 0 1 1 0 1 a[(L+R)/2] bR 0 1 1 1 0 a[(L+R)/2] bL 0 1 1 1 1 a[(L+R)/2] b[(L+R)/2] 10000 MUTE MUTE 10001 MUTE bR 10010 MUTE bL 10011 MUTE [(aL+bR)/2] 10100 aR MUTE 10101 aR bR 10110 aR bL 10111 aR [(bL+aR)/2] 11000 aL MUTE 11001 aL bR 11010 aL bL 11011 aL [(aL+bR)/2] 1 1 1 0 0 [(aL+bR)/2] MUTE 1 1 1 0 1 [(aL+bR)/2] bR 1 1 1 1 0 [(bL+aR)/2] bL 1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2]

Table 14. ATAPI Decode

CS42416

54 DS602F2

CS42416

6.15 ADC Left Channel Gain (address 1Ch)

76543210

Reserved Reserved LGAIN5 LGAIN4 LGAIN3 LGAIN2 LGAIN1 LGAIN0

6.15.1 ADC LEFT CHANNEL GAIN (LGAINX)

Default = 00h

Function:

The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown in Table 15.

6.16 ADC Right Channel Gain (address 1Dh)

76543210

Reserved Reserved RGAIN5 RGAIN4 RGAIN3 RGAIN2 RGAIN1 RGAIN0

6.16.1 ADC RIGHT CHANNEL GAIN (RGAINX)

Default = 00h

Function:

The level of the right analog channel can be adjusted in 1 dB increments as dictated by the Soft and Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown in Table 15.

Binary Code Decimal Value Volume Setting

001111 +15 +15 dB 001010 +10 +10 dB 000101 +5 +5 dB 000000 0 0 dB

111011 -5 -5 dB

110110 -10 -10 dB

110001 -15 -15 dB

Table 15. Example ADC Input Gain Settings

6.17 Interrupt Control (address 1Eh)

76543210

SP_SYNC Reserved DE-EMPH1 DE-EMPH0 INT1 INT0 Reserved Reserved

6.17.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)

Default = 0 0 - DAC & ADC Serial Port timings not in phase 1 - DAC & ADC Serial Port timings are in phase

Function:

Forces the LRCK and SCLK from the DAC & ADC Serial Ports to align and operate in phase. This function will operate when both ports are running at the same sample rate or when operating at different sample rates.

DS602F2 55

6.17.2 DE-EMPHASIS SELECT BITS (DE-EMPHX)

Default = 00 00 - Reserved 01 - De-Emphasis for 32 kHz sample rate. 10 - De-Emphasis for 44.1 kHz sample rate. 11 - De-Emphasis for 48 kHz sample rate.

Function:

Used to specify which de-emphasis filter to apply when the “Force PLL Lock (FRC_PLL_LK)” on

page 49 is enabled.

6.17.3 INTERRUPT PIN CONTROL (INTX)

Default = 00 00 - Active high; high output indicates interrupt condition has occurred 01 - Active low; low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved

Function:

Determines how the interrupt pin (INT) will indicate an interrupt condition.

CS42416

6.18 Interrupt Status (address 20h) (Read Only)

76543210

UNLOCK Reserved Reserved Reserved Reserved Reserved OverFlow Reserved

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always be “0” in this register.

6.18.1 PLL UNLOCK (UNLOCK)

Default = 0

Function:

PLL unlock status bit. This bit will go high if the PLL becomes unlocked.

6.18.2 ADC OVERFLOW (OVERFLOW)

Default = 0

Function:

Indicates that there is an over-range condition anywhere in the CS42416 ADC signal path.

56 DS602F2

CS42416

6.19 Interrupt Mask (address 21h)

76543210

UNLOCKM Reserved Reserved Reserved Reserved Reserved OverFlowM Reserved

Default = 00000000

Function:

The bits of this register serve as a mask for the interrupt sources found in the register “Interrupt Status

(address 20h) (Read Only)” on page 56. If a mask bit is set to 1, the error is unmasked, meaning that

its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Interrupt Status register.

6.20 Interrupt Mode MSB (address 22h) Interrupt Mode LSB (address 23h)

76543210

UNLOCK1 Reserved Reserved Reserved Reserved Reserved OF1 Reserved UNLOCK0 Reserved Reserved Reserved Reserved Reserved OF0 Reserved

Default = 00000000

Function:

The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits located in the register “Interrupt Control

(address 1Eh)” on page 55.

00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved

6.21 Mutec Pin Control (address 28h)

76543210

Reserved Reserved MCPolarity M_AOUTA1 M_AOUTB1 M_AOUTA2

M_AOUTB2

6.21.1 MUTEC POLARITY SELECT (MCPOLARITY)

Default = 0 0 - Active low 1 - Active high

Function:

M_AOUTA3 M_AOUTB3

Reserved

Determines the polarity of the MUTEC pin.

DS602F2 57

CS42416

6.21.2 CHANNEL MUTES SELECT (M_AOUTXX)

Default = 1111 0 - Channel mute is not mapped to the MUTEC pin 1 - Channel mute is mapped to the MUTEC pin

Function:

Determines which channel mutes will be mapped to the MUTEC pin. If no channel mute bits are mapped, then the MUTEC pin is driven to the “active” state as defined by the POLARITY bit. These Channel Mute Select bits are “ANDed” together in order for the MUTEC pin to go active. This means that if multiple Channel Mutes are selected to be mapped to the MUTEC pin, all corresponding channels must be muted before the MUTEC will go active.

6.22 General-Purpose Pin Control (addresses 29h to 2Fh)

76543210

Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0

6.22.1 MODE CONTROL (MODEX)

Default = 00 00 - Reserved 01 - Mute Mode 10 - GPO/Overflow Mode 11 - GPO, Drive High Mode Function:

Mute Mode Function bits.

GPO, Drive Low / ADC Overflow Mode or as a dedicated ADC overflow pin indicating an over-range condition anywhere in the ADC signal path for either the left or right channel. The Functionx bits determine the operation of the pin. When configured as a GPO with the output driven low, the driver is a CMOS driver. When configured to identify an ADC Overflow condition, the driver is an open drain driver requiring a pull-up resistor.

GPO, Drive High Mode

6.22.2 POLARITY SELECT (POLARITY)

Default = 0

Function:

Mute Mode polarity of the mapped pin according to the following

0 - Active low 1 - Active high

GPO, Drive Low / ADC Overflow Mode Mode pin, the polarity bit is ignored. It is recommended that in this mode this bit be set to 0.

GPO, Drive High ignored. It is recommended that in this mode this bit be set to 0.

- The pin is configured as a dedicated mute pin. The muting function is controlled by the

- The pin is configured as a general purpose output driven high.

- If the pin is configured as a dedicated mute output pin, the polarity bit determines the

- If the pin is configured as a general-purpose output driven high, the polarity bit is

- The pin is configured as a general-purpose output driven low

- If the pin is configured as a GPO, Drive Low / ADC Overflow

58 DS602F2

6.22.3 FUNCTIONAL CONTROL (FUNCTIONX)

Default = 00000 Function:

CS42416

Mute Mode

- If the pin is configured as a dedicated mute pin, the functional bits determine which chan-

nel mutes will be mapped to this pin according to the following table.

0 - Channel mute is not mapped to the GPOx pin 1 - Channel mute is mapped to the GPOx pin:

GPOx Reg Address Function4 Function3 Function2 Function1 Function0

GPO7 pin 42

GPO6 pin 43

GPO5 pin 44 GPO4 pin 45 GPO3 pin 46 GPO2 pin 47 GPO1 pin 48

29h M_AOUTA1 M_AOUTB1

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

M_AOUTA1 M_AOUTB1

M_AOUTA1 M_AOUTB1 M_AOUTA1 M_AOUTB1 M_AOUTA1 M_AOUTB1 M_AOUTA1 M_AOUTB1 M_AOUTA1 M_AOUTB1

GPO, Drive Low / ADC Overflow Mode

M_AOUTA2 M_AOUTB2

M_AOUTA2 M_AOUTB2 M_AOUTA2 M_AOUTB2

- If the pin is configured as a GPO, Drive Low / ADC Overflow

M_AOUTA2 M_AOUTB2

M_AOUTA3 M_AOUTB3 Reserved

M_AOUTA3

M_AOUTB3

M_AOUTA3

M_AOUTB3

M_AOUTA3

M_AOUTB3

M_AOUTA3

M_AOUTB3

M_AOUTA3

M_AOUTB3

Reserved Reserved

Reserved

Mode pin, the Function1 and Function0 bits determine how the output will behave according to the following table. It is recommended that in this mode the remaining functional bits be set to 0.

Function1 Function0 GPOx Driver Type

0 0 Drive Low CMOS 1 1 OVFL R or L Open Drain

GPO, Drive High

- If the pin is configured as a general-purpose output, the functional bits are ignored

and the pin is driven high. It is recommended that in this mode all the functional bits be set to 0.

DS602F2 59

7. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.

CS42416

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

60 DS602F2

8. APPENDIX A: EXTERNAL FILTERS

100

F

100 k



10 k

3.32 k

2.8 k

0.1 F 100 F

470 pF

C0G

634



634 

91 

2700 pF

C0G

AINL1+

AINL1-

AINR1+

AINR1-

100

F

100 k



10 k

3.32 k

2.8 k

0.1 F 100 F

470 pF

C0G

634



634 

91 

2700 pF

C0G

332 

Figure 24. Recommended Analog Input Buffer

AINL

AINR

AOUT +

AOUT -

390 pF

C0G

1 k 

22 F

6.19 k

1800 pF

C0G

887 

2.94 k

5.49 k

1.65 k

1.87 k

22 F

1200 pF

C0G

5800 pF

C0G

47.5 k 

Analog

Out

Figure 25. Recommended Analog Output Buffer

8.1 ADC Input Filter

The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n

 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to Figure 24 for a recommended

analog input buffer that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors that have a large voltage coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity.

CS42416

8.2 DAC Output Filter

The CS42416 is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.

DS602F2 61

9. APPENDIX B: PLL FILTER

RFILT (k)CFILT (F) CRIP (pF)

2.55 0.047 2200

Table 16. PLL External Component Values

9.1 External Filter Components

9.1.1 General

The PLL behavior is affected by the external filter component values in the Typical Connection Diagrams. Figure 5 and Figure 6 show the recommended configuration of the two capacitors and one resistor that comprise the PLL filter. The external PLL component values listed in Table 16 have a high corner-frequency jitter-attenuation curve, take a short time to lock, and offer good output jitter performance. Lock times are worst case for an Fsi transition of 192 kHz.

It is important to treat the LPFILT pin as a low-level analog input. It is suggested that the ground end of the PLL filter be returned directly to the AGND pin independently of the digital ground plane.

9.1.2 Capacitor Selection

CS42416

The type of capacitors used for the PLL filter can have a significant effect on PLL performance. Large or exotic film capacitors are not necessary because their leads, and the required longer circuit board traces, add undesirable inductance to the circuit. Surface-mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the LPFLT pin to minimize trace inductance. For CRIP, a C0G or NPO dielectric is recommended; and for CFILT, an X7R dielectric is preferred. Avoid capacitors with large temperature co-coefficient, or capacitors with high dielectric constants, that are sensitive to shock and vibration. These include the Z5U and Y5V dielectrics.

62 DS602F2

9.1.3 Circuit Board Layout

AGND

LPFLT

CFILT

RFILT

CRIP

0.1 µF

0.01 µF

10 µF

= via to ground plane

Figure 26. Recommended Layout Example

Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure 26 illustrates a suggested layout for the PLL filter components and for bypassing the analog supply voltage. The 10 µF bypass capacitor is an electrolytic in a surface-mount case A or thru-hole package. RFILT, CFILT, CRIP, and the 0.1 µF decoupling capacitor are in an 0805 form factor. The 0.01 µF decoupling capacitor is in the 0603 form factor. The traces are on the top surface of the board with the IC so that there is no via inductance. The traces themselves are short to minimize the inductance in the filter path. The VA and AGND traces extend back to their origin and are shown only in truncated form in the drawing.

CS42416

DS602F2 63

10.APPENDIX C: ADC FILTER PLOTS

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

Figure 27. Single-Speed Mode Stopband Rejection Figure 28. Single-Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0. 53 0.54 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.1 5 0 .20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 29. Single-Speed Mode Transition Band (Detail) Figure 30. Single-Speed Mode Passband Ripple

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70

Frequency (normalized to Fs)

Amplitude (dB)

Figure 31. Double-Speed Mode Stopband Rejection Figure 32. Double-Speed Mode Transition Band

CS42416

64 DS602F2

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.40 0.43 0.45 0.48 0.50 0.53 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 33. Double-Speed Mode Transition Band (Detail) Figure 34. Double-Speed Mode Passband Ripple

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.2 0.25 0.3 0. 35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8

Frequency (normalized to Fs)

Amplitude (dB)

Figure 35. Quad-Speed Mode Stopband Rejection Figure 36. Quad-Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25

Frequency (normalized to Fs)

Amplitude (dB)

Figure 37. Quad-Speed Mode Transition Band (Detail) Figure 38. Quad-Speed Mode Passband Ripple

CS42416

DS602F2 65

11.APPENDIX D: DAC FILTER PLOTS

0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 39. Single-Speed (fast) Stopband Rejection Figure 40. Single-Speed (fast) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

Figure 41. Single-Speed (fast) Transition Band (detail) Figure 42. Single-Speed (fast) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 43. Single-Speed (slow) Stopband Rejection Figure 44. Single-Speed (slow) Transition Band

CS42416

Amplitude (dB)

100

120

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

0.02

0.015

0.01

0.005

Frequency(normalized to Fs)

Amplitude (dB)

0.005

0.01

0.015

0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

Amplitude (dB)

100

66 DS602F2

120

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

Frequency(normalized to Fs)

CS42416

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

Figure 45. Single-Speed (slow) Transition Band (detail) Figure 46. Single-Speed (slow) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 47. Double-Speed (fast) Stopband Rejection Figure 48. Double-Speed (fast) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 49. Double-Speed (fast) Transition Band (detail) Figure 50. Double-Speed (fast) Passband Ripple

DS602F2 67

CS42416

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 51. Double-Speed (slow) Stopband Rejection Figure 52. Double-Speed (slow) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

Figure 53. Double-Speed (slow) Transition Band (detail) Figure 54. Double-Speed (slow) Passband Ripple

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 55. Quad-Speed (fast) Stopband Rejection Figure 56. Quad-Speed (fast) Transition Band

Amplitude (dB)

100

120

0.2 0.3 0.4 0.5 0.6 0.7 0.

0.02

0.015

0.01

0.005

Frequency(normalized to Fs)

Amplitude (dB)

0.005

0.01

0.015

0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.3

Amplitude (dB)

100

120

68 DS602F2

0.2 0.3 0.4 0.5 0.6 0.7 0.

Frequency(normalized to Fs)

CS42416

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25

0.2

0.15

0.1

0.05

0.1

0.15

0.2

Frequency(normalized to Fs)

Amplitude (dB)

Figure 57. Quad-Speed (fast) Transition Band (detail) Figure 58. Quad-Speed (fast) Passband Ripple

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 59. Quad-Speed (slow) Stopband Rejection Figure 60. Quad-Speed (slow) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.02 0.04 0.06 0.08 0.1 0.12

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 61. Quad-Speed (slow) Transition Band (detail) Figure 62. Quad-Speed (slow) Passband Ripple

DS602F2 69

12.PACKAGE DIMENSIONS

64L LQFP PACKAGE DRAWING



CS42416

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A --- 0.55 0.063 --- 1.40 1.60

A1 0.002 0.004 0.006 0.05 0.10 0.15

B 0.007 0.008 0.011 0.17 0.20 0.27 D 0.461 0.472 BSC 0.484 11.70 12.0 BSC 12.30

D1 0.390 0.393 BSC 0.398 9.90 10.0 BSC 10.10

E 0.461 0.472 BSC 0.484 11.70 12.0 BSC 12.30

E1 0.390 0.393 BSC 0.398 9.90 10.0 BSC 10.10

e* 0.016 0.020 BSC 0.024 0.40 0.50 BSC 0.60

L 0.018 0.024 0.030 0.45 0.60 0.75



0.000° 4° 7.000° 0.00° 4° 7.00°

* Nominal pin pitch is 0.50 mm

Controlling dimension is mm. JEDEC Designation: MS026

THERMAL CHARACTERISTICS

Parameter Symbol Min Typ Max Units

Allowable Junction Temperature

Junction to Ambient Thermal Impedance



--+135C

-48 -°C/Watt

70 DS602F2

CS42416

13.ORDERING INFORMATION

Product Description Package Pb-Free Grade Temp Range Container Order #

CS42416 110 dB, 192 kHz

6-Ch Codec with PLL

CDB42428 CS42416 Evaluation Board No - - - CDB42428

64-pin LQFP

Yes Commercial -10° to +70° C Tray CS42416-CQZ

Tape & Reel CS42416-CQZR

14.REFERENCES

1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997.

http://www.cirrus.com/products/papers/meas/meas.html

2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices Version 6.0, February 1998.

3) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997.

4) Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988.

5) Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989.

6) Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989.

7) Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.

8) Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

9) Philips Semiconductor, The I2C-Bus Specification: Version 2.1

, January 2000. http://www.semicon-

ductors.philips.com

, by D.R. Welland, B.P. Del

,by

, by I. Fujimori,

DS602F2 71

15.REVISION HISTORY

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

SPI is a trademark of Motorola, Inc.

Release Date Changes

F1 November 2005 Final Release

• Added Revision History table on page 71.

• Updated registers 6.6.6 and 6.6.7 on page 47.

• Updated registers 6.7.4 and 6.7.5 on page 49.

• Updated PLL components in Table 16 on page 62.

• Added OMCK Frequency specification in the Switching Characteristics table on page 11.

• Updated ADC Input Impedance and Offset Error specifications in the Analog Input Characteristics table on page 7.

• Updated the DAC Full-Scale Voltage, Output Impedance, and Gain Drift specifications in the Analog Output Characteristics table on page 9.

• Updated specification conditions for the analog input characteristics on page 7.

• Updated specification conditions for the analog output characteristics on page 9.

• Updated specification of t

page 11.

• Corrected reference to the SW_CTRL[1:0] bits in section 4.4.3 on page 24.

• Moved the VQ and FILT+ specifications from the Analog Input Characteristics table on page 7 to the DC Electrical Characteristics table on page 14.

• Updated the Power Supply Current and Power Consumption specifications in the DC Electrical Characteristics table on page 14.

• Updated Section 4.4.4 on page 24.

• Corrected default value of the Chip_ID[3:0] bits in register 01h on pages 39 and 42.

• Updated default value of the Rev_ID[3:0] bits in register 01h on pages 39 and 42.

• Updated PLL_CLK[2:0] bit description on page 49.

F2 March 2014 • Removed references to automotive-class products.

• Changed Note 7 in “Analog Output Characteristics” on page 9 to “One LSB of triangular PDF dither is added to data.”

• Added 100 A spec for VOH and VOL in “Digital Interface Characteristics” on page 15.

• Updated legal statement on the last page.

, tdh, t

dpd

, and t

lrpd

CS42416

in the Switching Characteristics table on

72 DS602F2

Cirrus Logic CS42416 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. CHARACTERISTICS AND SPECIFICATIONS

SPECIFIED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

ANALOG INPUT CHARACTERISTICS

A/D DIGITAL FILTER CHARACTERISTICS

ANALOG OUTPUT CHARACTERISTICS

D/A DIGITAL FILTER CHARACTERISTICS

Figure 1. Serial Audio Port Master Mode Timing Figure 2. Serial Audio Port Slave Mode Timing

SWITCHING CHARACTERISTICS

Figure 3. Control Port Timing - I²C Format

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT

Figure 4. Control Port Timing - SPI Format

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT

DC ELECTRICAL CHARACTERISTICS

DIGITAL INTERFACE CHARACTERISTICS

2. PIN DESCRIPTIONS

3. TYPICAL CONNECTION DIAGRAMS

Figure 5. Typical Connection Diagram

Figure 6. Typical Connection Diagram using the PLL

4. APPLICATIONS

Figure 7. Full-Scale Analog Input

4.1 Overview

4.2 Analog Inputs

4.2.1 Line-Level Inputs

4.2.2 High-Pass Filter and DC Offset Calibration

Figure 8. Full-Scale Output

4.3 Analog Outputs

4.3.1 Line-Level Outputs and Filtering

4.3.2 Interpolation Filter

4.3.3 Digital Volume and Mute Control

Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3)

4.3.4 ATAPI Specification

4.4 Clock Generation

Figure 10. Clock Generation

4.4.1 PLL and Jitter Attenuation

4.4.2 OMCK System Clock Mode

Table 1. Common OMCK Clock Frequencies

4.4.3 Master Mode

4.4.4 Slave Mode

Table 3. Slave Mode Clock Ratios

4.5 Digital Interfaces

4.5.1 Serial Audio Interface Signals

Table 4. Serial Audio Port Channel Allocations

4.5.2 Serial Audio Interface Formats

Figure 11. Right-Justified Serial Audio Formats

Figure 12. I²S Serial Audio Formats

Figure 13. Left-Justified Serial Audio Formats

Figure 14. One-Line Mode #1 Serial Audio Format

Figure 15. One-Line Mode #2 Serial Audio Format

4.5.3 ADCIN1/ADCIN2 Serial Data Format

Figure 16. ADCIN1/ADCIN2 Serial Audio Format

4.5.4 One-Line Mode (OLM) Configurations

Figure 17. OLM Configuration #1

Figure 18. OLM Configuration #2

Figure 19. OLM Configuration #3

4.6 Control Port Description and Timing

Figure 20. OLM Configuration #4

4.6.1 SPI Mode

4.6.2 I²C Mode

Figure 21. Control Port Timing in SPI Mode

Figure 22. Control Port Timing, I²C Write

Figure 23. Control Port Timing, I²C Read

4.7 Interrupts

4.8 Reset and Power-Up

4.9 Power Supply, Grounding, and PCB Layout

5. REGISTER QUICK REFERENCE

6. REGISTER DESCRIPTION

Table 5. DAC De-Emphasis

Table 6. Digital Interface Formats

Table 7. ADC One-Line Mode

Table 8. DAC One-Line Mode

Table 9. RMCK Divider Settings

Table 10. OMCK Frequency Settings

Table 11. Master Clock Source Select

Table 12. PLL Clock Frequency Detection

Table 13. Example Digital Volume Settings