Cirrus Logic CS4234 User Manual

Gain / Volume

AIN4 (± )

AIN3 (± )

AIN2 (± )

AIN1 (± )

Inter polation

Filter

Channel Volume ,

Mute, Invert,

Noise Gate

Multi-bit 
Modul ators

AOUT1 ( ±)
AOUT2 ( ±)
AOUT3 ( ±)
AOUT4 ( ±)

I2C Control

Data

Contr ol Por t

Level Transl ator

VL

1. 8 to 5.0 VDC

RSTINT

SDIN1SDOU Tx









Group

Delay

0-500 uS

Master Clock In

Fr ame Sync

Clock / LRCK

SDIN 2

Seri al Cl ock

In / Out

LDO Analog Supply

2.5 V

VA

5.0 VDC

VD

2.5 VDC

Low -Latency

Demux

5th DAC

Input Advi sory

DAC &
Analog

Filters

Tr acki ng

SMPS
Enable

Sample

& Hol d

Mute, Invert ,

Noise Gate

Master
Volume
Contr ol

Seri al Audio I nterface

AOUT 5 (±)

(SMPS Contr ol )

DAC &
Analog

Filters

Master

Vol. C ntrl

Select

Master Volume

0 dB

TPS

GAIN

Filter
Select

X

Inter polation F ilter

Sample & Hold

Max

Detect

Envel ope
Tracking

Mute, Invert ,

Noise Gate

DAC

Volume

Multi-bit 
Modul ators

Mode
Select

Ful l Scal e Code

DC Of fset

X

Digital Filters

Multi-bit
 ADC

-2

X

Gain

Select

-1

CS4234

4 In/5 Out CODEC with Programmable Class H Controller

DAC Features

 Advanced multibit Delta–Sigma modulator
 24-bit resolution
 Differential or single-ended outputs
 -109 dB dynamic range (A-weighted)
 -90 dB THD+N
 2 Vrms full-scale output into 3-k AC load
 Rail-to-rail operation
 Programmable group delay in 4-channel audio

output path

ADC Features

 Advanced multibit Delta–Sigma modulator
 24-bit resolution
 Differential inputs
 -105 dB dynamic range (A-weighted)
 - 88 dB THD+N
 2 Vrms full-scale input

System Features

 TDM, left justified, and I2S serial inputs and outputs
 Nondelayed low-latency path
 Supports sample rates up to 96 kHz

Class H Controller Features

 Can be used with any integrated Class AB amplifier

IC or discrete amplifier solution.

 Increases efficiency of Class AB amplifiers
 Creates audio tracking reference signal for external

switch-mode power supply

 Internal envelope tracking of up to 32 channels
 Input path for externally generated tracking signal

Common Applications

 Discrete Class H automotive audio amplifiers
 Automotive head units with internal Class H

amplifiers

 Audio mixing consoles
 Audio effects processors

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2012

(All Rights Reserved)

MAR ‘12

DS899F1

CS4234

General Description

The CS4234 is a highly versatile CODEC that combines 4 channels of high performance analog to digital conver­sion, 4 channels of high performance digital to analog conversion for audio, and 1 channel of digital to analog
conversion to provide a nondelayed audio reference signal to an external Class H tracking power supply. If not used
to drive a tracking power supply, the 5
specifications identical to that of the 4 DACs in the audio path. Additionally, the CS4234 includes tunable group de­lay for each of the 4 audio DAC paths to provide lead time for the external switch-mode power supply, and a
nondelayed path into the DAC outputs for input signals requiring a low-latency path to the outputs.

Targeting the automotive audio market, this controller was specifically designed to work with Apex Precision Power’s
CS44417 Class AB audio amplifier, but remains flexible enough to allow any standard Class AB amplifier to be op­erated as a Class H amplifier in order to maximize efficiency. Class H control provides significant efficiency gains
over traditional Class AB amplifiers, while avoiding the increased electromagnetic interference (EMI) and cost of
Class D amplifiers.

The Class H controller provides a reference signal which tracks the envelope of the maximum (on a sample by sam­ple basis) of up to 32 channels of serial data in the TDM slots input on the SDINx lines. This reference signal is sent
to the 5
ages to an external Class AB amplifier, thereby turning any standard Class AB amplifier into a Class H amplifier. If
desired, the internal tracking power supply circuitry can be bypassed, which allows a DSP generated tracking signal
to be used to control the SMPS. This feature allows an unlimited number of channels to be tracked, using a DSP to
create the tracking signal.

This product is available in a 40-pin QFN package in Automotive (-40 °C to +105 °C) temperature grade. See “Or-

dering Information” on page 74 for complete details.

th

DAC to create an analog reference signal for an external switch-mode power supply that supplies rail volt-

th

DAC can instead be used as a standard audio grade DAC, with performance

DS899F1 2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ............................................................................................................................ 6

1.1 I/O Pin Characteristics ..................................................................................................................... 7

2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 8

3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 9

RECOMMENDED OPERATING CONDITIONS .................................................................................... 9

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 9

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 10

TYPICAL CURRENT CONSUMPTION ............................................................................................... 11

ANALOG INPUT CHARACTERISTICS .............................................................................................. 12

ADC DIGITAL FILTER CHARACTERISTICS ...................................................................................... 14

ANALOG OUTPUT CHARACTERISTICS ........................................................................................... 15

COMBINED DAC INTERPOLATION AND ON-CHIP ANALOG FILTER RESPONSE ........................ 16

DIGITAL I/O CHARACTERISTICS ...................................................................................................... 17

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE .................................................... 18

SWITCHING SPECIFICATIONS - CONTROL PORT .......................................................................... 20

4. APPLICATIONS ................................................................................................................................... 21

4.1 Power Supply Decoupling, Grounding, and PCB Layout ............................................................... 21

4.2 Recommended Power-Up and Power-Down Sequence ................................................................ 21

4.3 I²C Control Port .............................................................................................................................. 25

4.4 System Clocking ............................................................................................................................ 26

4.5 Serial Port Interface ....................................................................................................................... 28

4.6 Internal Signal Path ....................................................................................................................... 32

4.7 Reset Line ...................................................................................................................................... 47

4.8 Error Reporting and Interrupt Behavior .......................................................................................... 47

5. REGISTER QUICK REFERENCE ........................................................................................................ 50

6. REGISTER DESCRIPTIONS ................................................................................................................ 52

6.1 Device I.D. A and B (Address 01h) (Read Only)
Device I.D. C and D (Address 02h) (Read Only)

Device I.D. E and F (Address 03h) (Read Only) ...............................................................................52

6.2 Revision I.D. (Address 05h) (Read Only) ....................................................................................... 52

6.3 Clock and SP Select (Address 06h) ............................................................................................... 53

6.4 Sample Width Select (Address 07h) .............................................................................................. 54

6.5 Serial Port Control (Address 08h) .................................................................................................. 55

6.6 Serial Port Data Select (Address 09h) ........................................................................................... 56

6.7 Serial Data Input 1 Mask 1 (Address 0Ah) ..................................................................................... 57

6.8 Serial Data Input 1 Mask 2 (Address 0Bh) ..................................................................................... 57

6.9 Serial Data Input 2 Mask 1 (Address 0Ch) .................................................................................... 58

6.10 Serial Data Input 2 Mask 2 (Address 0Dh) ..................................................................................58

6.11 Tracking Power Supply Control (Address 0Eh) ........................................................................... 59

6.12 ADC Control 1 (Address 0Fh) ...................................................................................................... 60

6.13 ADC Control 2 (Address 10h) ...................................................................................................... 61

6.14 Low Latency Path Control (Address 11h) ....................................................................................61

6.15 DAC Control 1 (Address 12h) ...................................................................................................... 62

6.16 DAC Control 2 (Address 13h) ...................................................................................................... 63

6.17 DAC Control 3 (Address 14h) ...................................................................................................... 63

6.18 DAC Control 4 (Address 15h) ...................................................................................................... 64

6.19 Volume Mode (Address 16h) ....................................................................................................... 65

6.20 Master and DAC1-5 Volume Control (Address 17h, 18h, 19h, 1Ah, 1Bh, and 1Ch) ................... 66

6.21 Interrupt Control (Address 1Eh) ..........................................................................................

6.22 Interrupt Mask 1 (Address 1Fh) ................................................................................................... 67

6.23 Interrupt Mask 2 (Address 20h) ................................................................................................... 68

6.24 Interrupt Notification 1 (Address 21h) (Read Only) ...................................................................... 68

CS4234

......... 66

DS899F1 3

6.25 Interrupt Notification 2 (Address 22h) (Read Only) ...................................................................... 69

7. ADC FILTER PLOTS ............................................................................................................................ 70

8. DAC FILTER PLOTS ............................................................................................................................ 71

9. PACKAGE DIMENSIONS ................................................................................................................... 73

10. ORDERING INFORMATION .............................................................................................................. 74

11. APPENDIX A:INTERNAL TRACKING POWER SUPPLY SIGNAL .................................................. 74

11.1 Voltage Headroom ....................................................................................................................... 76

11.2 Lead Time .................................................................................................................................... 76

11.3 Gain Matching .............................................................................................................................. 76

11.4 SMPS (TPS) Modes ..................................................................................................................... 77

12. REVISION HISTORY .......................................................................................................................... 79

LIST OF FIGURES

Figure 1. CS4234 Pinout ............................................................................................................................. 6

Figure 2. Typical Connection Diagram ........................................................................................................ 8

Figure 3. Test Circuit for ADC Performance Testing ................................................................................. 13

Figure 4. PSRR Test Configuration ........................................................................................................... 13

Figure 5. Equivalent Output Test Load ..................................................................................................... 15

Figure 6. TDM Serial Audio Interface Timing ............................................................................................ 19

Figure 7. PCM Serial Audio Interface Timing ............................................................................................ 19

Figure 8. I²C Control Port Timing .............................................................................................................. 20

Figure 9. System Level Initialization and Power-up / Power-down Sequence .......................................... 23

Figure 10. DAC DC Loading ..................................................................................................................... 24

Figure 11. Timing, I²C Write ...................................................................................................................... 25

Figure 12. Timing, I²C Read ...................................................................................................................... 25

Figure 13. Master Mode Clocking ............................................................................................................. 27

Figure 14. TDM System Clock Format ...................................................................................................... 28

Figure 15. 32-bit Receiver Channel Block ................................................................................................. 29

Figure 16. Serial Data Coding and Extraction Options within the TDM Streams ...................................... 30

Figure 17. Left Justified Format ................................................................................................................ 31

Figure 18. I²S Format ................................................................................................................................ 31

Figure 19. Audio Path Routing .................................................................................................................. 32

Figure 20. Conventional SDOUT1 (Left) vs. Sidechain SDOUT1 (Right) Configuration ........................... 33

Figure 21. DAC1-4, Low Latency, and DAC5 Path Serial Data Source Selection .................................... 34

Figure 22. Example Serial Data Source Selection .................................................................................... 35

Figure 23. ADC Path ................................................................................................................................. 38

Figure 24. DAC1-4 Path ............................................................................................................................ 39

Figure 25. De-emphasis Curve ................................................................................................................. 40

Figure 26. Low-latency Path ..................................................................................................................... 40

Figure 27. DAC5 Path ............................................................................................................................... 41

Figure 28. Volume Implementation for the DAC1-4 and Low-latency Path ............................................... 43

Figure 29. Volume Implementation for the DAC5 Path .............................................................................43

Figure 30. Soft Ramp Behavior ................................................................................................................. 45

Figure 31. Interrupt Behavior and Example Interrupt Service Routine ...................................................... 49

Figure 32. ADC Stopband Rejection ......................................................................................................... 70

Figure 33. ADC Transition Band ............................................................................................................... 70

Figure 34. ADC Transition Band (Detail) ................................................................................................... 70

Figure 35. ADC Passband Ripple ............................................................................................................. 70

Figure 36. ADC HPF (48 kHz) ................................................................................................................... 70

Figure 37. ADC HPF (96 kHz) ................................................................................................................... 70

Figure 38. SSM DAC Stopband Rejection ................................................................................................ 71

Figure 39. SSM DAC Transition Band ...................................................................................................... 71

Figure 40. SSM DAC Transition Band (Detail) .......................................................................................... 71

CS4234

DS899F1 4

Figure 41. SSM DAC Passband Ripple .................................................................................................... 71

Figure 42. DSM DAC Stopband Rejection ................................................................................................ 72

Figure 43. DSM DAC Transition Band ...................................................................................................... 72

Figure 44. DSM DAC Transition Band (Detail) .......................................................................................... 72

Figure 45. DSM DAC Passband Ripple .................................................................................................... 72

Figure 46. Package Drawing ..................................................................................................................... 73

Figure 47. Progression of the Tracking Signal Through the DAC5 Path ................................................... 75

Figure 48. Directly Proportional vs. Indirectly Proportional Modes of Operation ....................................... 77

Figure 49. DAC5 TPS Modes of Operation ............................................................................................... 78

Figure 50. DAC5 Volume and TPS Offset Controls .................................................................................. 78

LIST OF TABLES

Table 1. Speed Modes .............................................................................................................................. 26

Table 2. Common Clock Frequencies ....................................................................................................... 27

Table 3. Master Mode Left Justified and I²S Clock Ratios ........................................................................ 27

Table 4. Slave Mode Left Justified and I²S Clock Ratios .......................................................................... 28

Table 5. Slave Mode TDM Clock Ratios ................................................................................................... 28

Table 6. Unmasking SDIN1 Data from DAC5 Path ...................................................................................36

Table 7. Unmasking SDIN2 Data from DAC5 Path ...................................................................................37

Table 8. Soft Ramp Rates ......................................................................................................................... 46

Table 9. Noise Gate Bit Depth Settings .................................................................................................... 46

Table 10. Error Reporting and Interrupt Behavior Details ......................................................................... 47

CS4234

DS899F1 5

1. PIN DESCRIPTIONS

AD0

AD2/SDOUT2

AOUT5+

VA

AIN3+

AIN4-

AIN3-

AIN2+

AIN2-

AIN1-

AIN1+

FILT+

SDA

MCLK

SDOUT 1

VL

GND

SDIN1

SDIN2

12

11

13

14

15

16

17

18

19

20

29

30

28

27

26

25

24

23

22

21

394038

37

36

35

34

33

32

31

2

1

3

4

5

6

7

8

9

10

AOUT1+

SCLK

VDREG

AOUT2+

AOUT2-

AOUT3+

AOUT3-

AOUT4-

AOUT4+

VBIAS

VREF

VQ

GND

AOUT5-

AOUT1-

SCL

FS/LRCK

AD1

INT

RST

AIN4+

Top-Down

(Though Package)

View

CS4234

Figure 1. CS4234 Pinout

Pin Name Pin # Pin Description

SDA 1

Serial Control Data (Input/Output) - Bidirectional data I/O for the I²C

SDINx 2,3 Serial Data Input (Input) - Input channels serial audio and low latency data.

FS/LRCK 4

Frame Synchronization Clock/Left/Right Clock (Input/Output) - Determines which channel or

frame is currently active on the serial audio data line.

MCLK 5 Master Clock (Input) -Clock source for the internal logic, processing, and modulators.
SCLK 6 Serial Clock (Input/Output) -Serial Clock for the serial data port.

SDOUT1 7

VL 8 Interface Power (Input) - Positive power for the digital interface level shifters.

GND 9,21

VDREG 10 Digital Power (Output) - Internally generated positive power supply for digital section.

AINx+

AINx-

FILT+ 19 Positive Voltage Reference (Output) - Positive reference voltage for the internal ADCs.
VA 20 Analog Power (Input) - Positive power for the analog sections.
VQ 22 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
VREF 23 Analog Power Reference (Input) - Return pin for the VBIAS cap.

DS899F1 6

11,13,15,

12,14,16,

Serial Data Output 1 (Output) - ADC data output into a multi-slot TDM stream or AIN1 and AIN2

ADC data output in Left Justified and I²S modes.

Ground (Input) - Ground reference for the I/O and digital, analog sections.

Positive Analog Input (Input) - Positive input signals to the internal analog to digital converters.

17

The full scale analog input level is specified in the Analog Input Characteristics table.

Negative Analog Input (Input) - Negative input signals to the internal analog to digital converters.

18

The full scale analog input level is specified in the Analog Input Characteristics table.

TM

control port.

Pin Name Pin # Pin Description

VBIAS 24 Positive Voltage Reference (Output) - Positive reference voltage for the internal DACs.

AOUTx-

AOUTx+

RST

INT

AD2/SDOUT2 37

AD1 38 I²C Address Bit 1 (Input) - Sets the I²C address bit 1.
AD0 39 I²C Address Bit 0 (Input) - Sets the I²C address bit 0.
SCL 40 Serial Control Port Clock (Input) - Serial clock for the I²C control port.

GND -

25,27,29,

31, 33

26,28,30,

32, 34

Negative Analog Output (Output) - Negative output signals from the internal digital to analog con-

verters. The full scale analog output level is specified in the Analog Output Characteristics table.

Positive Analog Output (Output) - Positive output signals from the internal digital to analog con-

verters. The full scale analog output level is specified in the Analog Output Characteristics table.

35 Reset (Input) - Applies reset to the internal circuitry when pulled low.
36 Interrupt (Output) - Sent to DSP to indicate an interrupt condition occurred.

I²C Address Bit 2/Serial Data Output 2 (Input/Output) - Sets the I²C address bit 2 at reset. Func-

tions as Serial Data Out 2 for AIN3 and AIN4 ADC data output in Left Justified and I²S modes. High
impedance in TDM mode. See Section 4.3 I²C Control Port for more details concerning this mode of
operation.

Thermal Pad - The thermal pad on the bottom of the device should be connected to the ground
plane via an array of vias.

1.1 I/O Pin Characteristics

CS4234

Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.

Power Supply Pin Name I/O Driver

SCL Input - Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis

CMOS/Open

Drain

CMOS/Open

Drain

VL

SDA Input/Output

INT

RST

MCLK Input - Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis

FS/LRCK Input/Output 5.0 V CMOS- Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis

SCLK Input/Output 5.0 V CMOS- Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis

SDOUT1 Output 5.0 V CMOS Weak Pull-down (~500k

SDINx Input - Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
AD0,1 Input - (Note 2) 5.0 V CMOS

AD2/SDOUT2 Input/Output 5.0 V CMOS- (Note 2) 5.0 V CMOS

Output

Input - (Note 2) 5.0 V CMOS, with Hysteresis

Internal Connections

(Note 1)

Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis

(Note 2) -

Receiver

Notes:

1. Internal connection valid when device is in reset.

2. This pin has no internal pull-up or pull-down resistors. External pull-up or pull-down resistors should
be added in accordance with Figure 2.

DS899F1 7

CS4234

CS4234

AIN 4-

AIN 3+

AIN 2-

AIN 3-

VA

FILT+

AIN 1+

AIN 1-

AIN 2+

AIN 4+

SDOUT1VLGND

FS/LRCK

MCLK

SDIN2

SDIN1

SDA

VDREG

SCLK

AD 2

INT

AOUT1-

AOUT5-

AOUT1+

AOUT5+

RST

AD 0

AD 1

SCL

35

AO UT3-

AO UT4+

GND

VRE F

VQ

VBIAS

AO UT4-

AO UT2-

AO UT3+

AO UT2+

32 31

5.0 VD C

0.1uF

Pull Up or Down

Based upon

Desired Address.

0.1uF

10uF

3k(x5 )

40 38 37 3639

13264

5

7

8

17 18141311 15 16

5.0 V DC

Switch-Mode Power Supply

(Includes SMPS Controller with PWM

Mod ulator, Gate Drive( s), Power

De vice s, Ma gnetics )

3334

VB ATT

+V P

-VP

22 uF

22 uF

22 uF

22 uF

22 uF

22 uF

22 uF

22 uF

30

282726

25

222923

0.1uF 10uF

5.0 V DC

1uF

20

24

10uF

0.1uF

10

9

12

5.0 VD C

10 uF

0.1 uF

19

40k 

10uF

C2C1

C2 C1

C2C1

C2 C1

C2C1

C2 C1

C2C1

C2 C1

Bulk & Bypass Cap acitors

C1: 0.1uF Ceramic X7R

C2: 47uF Electrolytic

5.0 VDC

0.1uF

10uF

Pull Up or Down

Based upon

Des i re d A d dre s s .

3.3 uF

Digital Signal

Processor

CS44417

IMON1

IMON2

AIN2+

INT

AIN1+

RST

SDA

SCL

AIN2-

AIN1-

OUT1-

VP+

OUT2+

OUT2-

VP+

VP-

OUT1+

VL

DIAG_RAMP

VP-

22

21

19

18

14

AIN3-

IMON3

IMON4

MUTE

IREF

STBY

GND

VA

AIN4+

AIN3+

3

785

4

VP+

OUT3+

AD2/SD OUT2

VP+

OUT4+

OUT4-

VP-

VP-

OUT3-

VP-

AIN4-

AD0

1

2

VP-

AD1

20

(Heat Slug)

23

31

29

33

36

38

34

43

27

13

17

16

6

11910

15

12

41

39

35

37

32

30

24

26

28

40

42

44

25

R

T

R

REF

R

T

R

T

R

T

21

Figure 2. Typical Connection Diagram

2. TYPICAL CONNECTION DIAGRAM

DS899F1 8

CS4234

3. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V; all voltages with respect to ground. (Note 3)

Parameters Symbol Min Typ Max Units

DC Power Supply

Analog Core VA

Level Translator VL 1.71 - 5.25 V

3.135

4.75

3.3
5

3.465

5.25

V
V

Temperature

Ambient Operating Temperature - Power Applied T

Junction Temperature T

A

J

-40 - +105 C

-40 - +150 C

Notes: 3. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or

implied outside of these limits. Operation outside of these limits may adversely affect device reliability.

ABSOLUTE MAXIMUM RATINGS

GND = 0 V; all voltages with respect to ground.

Parameters Symbol Min Max Units

DC Power Supply

Analog Core VA -0.3 5.5 V

Level Translator VL -0.3 5.5 V

VDREG Current (Note 4) I

VDREG

Inputs

Input Current (Note 5) I

Analog Input Voltage (Note 6) V

Logic Level Input Voltage (Note 6) V

Temperature

Ambient Operating Temperature - Power Applied T

Storage Temperature T

in

INA

IND

A

stg

-10A

-±10mA

- 0.3 VA + 0.4 V

-0.3 VL + 0.4 V

-55 +125 °C

-65 +150 °C

WARNING:

OPERATION BEYOND THESE LIMITS MAY RESULT IN PERMANENT DAMAGE TO THE DEVICE.

Notes: 4. No external loads should be connected to the VDREG pin. Any connection of a load to this point may

result in errant operation or performance degradation in the device.

5. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.

6. The maximum over/under voltage is limited by the input current.

DS899F1 9

DC ELECTRICAL CHARACTERISTICS

GND = 0 V; all voltages with respect to ground.

Parameters Min Typ Max Units

VDREG (Note 7)

Nominal Voltage
Output Impedance

FILT+

Nominal Voltage
Output Impedance
DC Current Source/Sink

VQ

Nominal Voltage
Output Impedance
DC Current Source/Sink

Notes:

7. No external loads should be connected to the VDREG pin. Any connection of a load to this point may
result in errant operation or performance degradation in the device.

CS4234

-

-

-

-

-

-

-

-

2.5

0.5

VA

23

-

0.5•VA
77

-

-

-

-

-

1

-

-

0

V



V
k
A

V
k
A

DS899F1 10

CS4234

TYPICAL CURRENT CONSUMPTION

This table represents the power consumption for individual circuit blocks within the CS4234. CS4234 is configured as
shown in Figure 2 on page 8. VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC; F

DAC load is 3 k; All input signals are zero (digital zero for SDINx inputs and AC coupled to ground for AINx
inputs) .

= 100 kHz; MCLK = 25.6 MHz;

S

Typical Current [mA]

(unless otherwise noted)

(Note 9), (Note 12)

Functional Block

Reset Overhead

1

(All lines held static, RST

Power Down Overhead

2

(All lines clocks and data lines active, RST

PLL(Note 10)

3

(Current drawn resulting from PLL being active. PLL is active for 256x and 384x)

DAC Overhead

4

(Current drawn whenever any of the five DACs are powered up.)

DAC Channel (Note 8)

5

(Current drawn per each DAC powered up.)

ADC Overhead

6

(Current drawn whenever any of the four ADCs are powered up.)

ADC Group

7

(Current drawn due to an ADC “group” being powered up. See (Note 11))

ADC Channel

8

(Current drawn per each ADC powered up.)

line pulled low.)

line pulled high, All PDNx bits set high.)

Notes:

8. Full-scale differential output signal.

9. Current consumption increases with increasing F

and increasing MCLK. Values are based on FS of

S

100 kHz and MCLK of 25.6 MHz. Current variance between speed modes is small.

10. PLL is activated by setting the MCLK RATE bit to either 000 (operating in 256x mode) or 001 (operating
in 384 kHz).

11. Internal to the CS4234, the analog to digital converters are grouped together in stereo pairs. ADC1 and
ADC2 are grouped together as are ADC3 and ADC4. The ADC group current draw is the current that
is drawn whenever one of these groups become active.

12. To calculate total current draw for an arbitrary amount of ADCs or DACs, the following equations apply:

VA/ VL

5 0.030 0.001

3.3 0.020 0.001
5 5 0.101

3.3 5 0.101
51 -

3.3 1 ­550 -

3.3 45 ­55 -

3.3 4 ­511 -

3.3 11 ­52 -

3.3 2 ­5 2 0.109

3.3 2 0.066

i

VA

i

VL

Total Running Current Draw from VA Supply = Power Down Overhead + PLL (If Applicable)+ DAC Current Draw + ADC Current Draw

DAC Current Draw = DAC Overhead + (Number of DACs x DAC Channel)

ADC Current Draw = ADC Overhead + (Number of active ADC Groups x ADC Group) + (Number of active ADC Channels x ADC Channel)

Total Running Current Draw from V

L Supply = PDN Overhead + (Number of active ADC Channels x ADC Channel)

where

and

DS899F1 11

CS4234

ANALOG INPUT CHARACTERISTICS
Test Conditions (unless otherwise specified): Device configured as shown in Figure 2 on page 8. Input sine wave:

1kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T
to 20 kHz unless otherwise specified; Sample Rate = 48 kHz; all Power Down ADCx bits = 0.

VA, VREF = 3.3 V VA, VREF = 5.0 V

Parameter

Min Typ Max Min Typ Max Unit

Dynamic Range

A-weighted

unweighted

93
90

101

98

Total Harmonic Distortion + Noise

-1 dBFS

-60 dBFS

-

-

-95

-38

Other Analog Characteristics

Interchannel Gain Mismatch - 0.2 - - 0.2 - dB
Gain Drift - ±100 - - ±100 ­Offset Error (Note 13)

High Pass Filter On
High Pass Filter Off

-

-

0.0001

0.25
Interchannel Isolation - 90 - - 90 - dB
Full-scale Input Voltage

(Differential Inputs) 1.58•VA 1.66•VA 1.74•VA 1.58•VA 1.66•VA 1.74•VA Vpp
Input Impedance - 40 - - 40 - k
Common Mode Rejection

-60- -60- dB

(Differential Inputs)
PSRR (Note 14)

1 kHz

60 Hz

-

-

45
20

= -40 to +105 C; Measurement Bandwidth is 20 Hz

A

-

-

-87

-30

-

-

-

-

97
94

105
102

-

-

-

-

-

-

-88

-42

0.0001

0.25

45
20

-

-

-80

-34

-

-

-

-

dB
dB

dB
dB

ppm/°C

% Full Scale
% Full Scale

dB
dB

Notes:

13. AINx+ connected to AINx-.

14. Valid with the recommended capacitor values on FILT+ and VQ. See Figure 4 for test configuration.

DS899F1 12

CS4234

100 k

4.7 uF

100 k

100 k

470 pF

634 

90 .9 

Analog Signal +

+

-

100 k

4.7 uF

100 k

100 k

470 pF

634 

90 .9 

Analog S ignal -

+

-

VA

VA

2700 pF

Figure 3. Test Circuit for ADC Performance Testing

CS4234 AINx +

CS4234 AINx -

Operational

Amplifier

OUT

GND

Power DAC

Analog

Out

GND

PWR

DUT

+Vcc

+Vcc

+

-

OUT

Test Equipment

Analog Generator Analyzer

-Vcc

Digital

Out

+

-

+

-

+

-

Figure 4. PSRR Test Configuration

DS899F1 13

CS4234

ADC DIGITAL FILTER CHARACTERISTICS

Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. Input sine
wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T

20 Hz to 20 kHz unless otherwise specified. See filter plots in Section 7. on page 70.

Parameter (Note 15) Min Typ Max Unit

Passband (Frequency Response) to -0.1 dB corner 0 - 0.4535 Fs

Passband Ripple -0.09 - 0.17 dB

Stopband 0.6 - - Fs

Stopband Attenuation 70 - - dB

Single-Speed Mode

ADC Group Delay (Note 16) - 9.5/Fs - s

High-Pass Filter Characteristics (48 kHz Fs)

Frequency Response -3.0 dB

-0.13 dB

Phase Deviation @ 20 Hz - 10 - Deg

Passband Ripple -0.09 - 0.17 dB

Filter Settling Time (Note 17)

Double-Speed Mode

ADC Group Delay (Note 16) - 9.5/Fs - s

High-Pass Filter Characteristics (96 kHz Fs)

Frequency Response -3.0 dB

-0.13 dB

Phase Deviation @ 20 Hz - 10 - Deg

Passband Ripple -0.15 - 0.17 dB

Filter Settling Time (Note 17)

= -40 to +105 C; Measurement Bandwidth is

A

-

-

-

-

-

-

2

11

25000/Fs

4

22

25000/Fs

-

-

-s

-

-

-s

Hz
Hz

Hz
Hz

Note:

15. Response is clock dependent and will scale with Fs.

16. The ADC group delay is measured from the time the analog inputs are sampled on the AINx pins to
the FS/LRCK rising transition after the last bit of that group of samples has been transmitted on
SDOUT1.

17. The amount of time from input of half-full-scale step function until the filter output settles to 0.1% of
full scale.

DS899F1 14

CS4234

AOUTx

GND

22 µF

V

OUT

R

L

C

L

Figure 5. Equivalent Output Test Load

ANALOG OUTPUT CHARACTERISTICS

Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. VA_SEL = 0 for
VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T

Measurement Bandwidth is 20 Hz to 20 kHz; Specifications apply to all channels unless otherwise indicated; all

Power Down DACx bits = 0. See (Note 19).

= -40 to +105 C; Full-scale 1 kHz input sine wave; Sample Rate = 48 kHz;

A

VA, VREF= 3.3 V

(Differential/Single-ended)

VA, VREF= 5.0 V

(Differential/Single-ended)

Parameter Min Typ Max Min Typ Max Unit

Dynamic Performance

Dynamic Range
18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

98/94
95/91

87
84

106/102

103/99

95
92

-

-

-

-

101/97

98/94

87
84

109/105
106/102

95
92

-

-

-

-

dB
dB
dB
dB

Total Harmonic Distortion + Noise - -90/-88 -82/-80 - -90/-88 -82/-80 dB

Full-scale Output Voltage

1.48•VA/

0.74•VA

1.56•VA/

0.78•VA

1.64•VA/

0.82•VA

1.48•VA/

0.74•VA

1.56•VA/

0.78•VA

1.64•VA/

0.82•VA

Vpp

Interchannel Isolation (1 kHz) - 100 - - 100 - dB

Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB

Gain Drift - ±100 - - ±100 - ppm/°C

AC-Load Resistance (R

Load Capacitance (C

)(Note 19) 3- -3- -k

L

)(Note 19) - - 100 - - 100 pF

L

Parallel DC-Load Resistance(Note 20) 10 - - 10 - - k

Output Impedance - 100 - - 100 - 

PSRR (Note 21) 1 kHz

60 Hz

-

-

60
60

-

-

-

-

60
60

-

-

dB
dB

Notes:

18. One LSB of triangular PDF dither added to data.

19. Loading configuration is given in Figure 5 below.

20. Parallel combination of all DAC DC loads. See Section 4.2.3.

21. Valid with the recommended capacitor values on FILT+ and VQ. See Figure 4 for test configuration.

DS899F1 15

CS4234

COMBINED DAC INTERPOLATION AND ON-CHIP ANALOG FILTER RESPONSE

Test Conditions (unless otherwise specified): VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC. The filter charac­teristics have been normalized to the sample rate (F

plying the given characteristic by F

. See filter plots in Section 8. on page 71.

S

Parameter Min Typ Max Unit

Single-Speed Mode

Passband (Note 22) to -0.05 dB corner

Frequency Response 20 Hz to 20 kHz -0.01 - +0.12 dB
StopBand 0.5465 - - F
StopBand Attenuation (Note 23) 102 - - dB
DAC1-4 Group Delay (Note 24) (Note 25) -11/Fs-s
DAC5 Group Delay (Note 25)

(w/ interpolation filter)
(w/ sample and hold)

Low-Latency Group Delay (Note 25) -2/Fs-s

Double-Speed Mode

Passband (Note 22) to -0.1 dB corner

Frequency Response 20 Hz to 20 kHz -0.05 - +0.2 dB
StopBand 0.5770 - - F
StopBand Attenuation (Note 23) 80 - - dB
DAC1-4 Group Delay (Note 24) (Note 25) -7/Fs-s
DAC5 Group Delay (Note 25)

(w/ interpolation filter)
(w/ sample and hold)

Low-latency Group Delay (Note 25) - 2.5/Fs - s

) and can be referenced to the desired sample rate by multi-

S

to -3 dB corner

to -3 dB corner

0
0

-

-

0
0

-

-

-

-

11/ Fs

2/Fs

-

-

7/Fs

2.5/Fs

0.4780

0.4996

-

-

0.4650

0.4982

-

-

F

S

F

S

S

s
s

F

S

F

S

S

s
s

22. Response is clock dependent and will scale with F

23. For Single-Speed Mode, the measurement bandwidth is 0.5465 F
For Double-Speed Mode, the measurement bandwidth is 0.577 F

.

S

to 3 FS.

S

to 1.4 FS.

S

24. This specification is in addition to any delay added via the “GROUP DELAY[3:0]” bits in the "TPS

Control" register.

25. The DAC group delay is measured from the FS/LRCK rising transition before the first bit of a group of
samples is transmitted on the SDINx pins to the time it appears on the AOUTx pins.

DS899F1 16

CS4234

DIGITAL I/O CHARACTERISTICS

Parameters Symbol Min Typ Max Units

High-Level Input Voltage (all input pins except

(VL=1.8V)

High-Level Input Voltage (all input pins except

(VL=2.5V, 3.3V, or 5V)

Low-Level Input Voltage (all input pins except

High-Level Input Voltage (

Low-Level Input Voltage (

High-Level Output Voltage at I

Low-Level Output Voltage at I

RST pin) V

RST pin) V

=2mA (% of VL) V

o

=2mA (% of VL) V

o

Input Leakage Current I

Input Capacitance - 8 - pF

RST)(% of VL)

RST)(% of VL)

RST)(% of VL)V

V

IH

V

IH

IL

IH

IL

OH

OL

in

75% - - V

70% - - V

--30%V

1.2 - - V

--0.3V

80% - - V

--20%V

--±10A

DS899F1 17

CS4234

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE

VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.

Parameters Symbol Min Max Units

RST pin Low Pulse Width (Note 26) 1

MCLK Frequency

(Note 27) 7.68 25.6 MHz

MCLK Duty Cycle 45 55 %
SCLK Duty Cycle 45 55 %
Input Sample Rate (FS/LRCK pin) Single-Speed Mode

Double-Speed Mode
SCLK Falling Edge to SDOUTx Valid (VL = 1.8 V) t
SCLK Falling Edge to SDOUTx Valid (VL = 2.5 V) t
SCLK Falling Edge to SDOUTx Valid (VL = 3.3 V or 5 V) t

F
F

dh2

dh2

dh2

S

S

30
60

-31ns

-22ns

-17ns

TDM Slave Mode

SCLK Frequency

FS/LRCK High Time Pulse (Note 29)

FS/LRCK Rising Edge to SCLK Rising Edge t
SDINx Setup Time Before SCLK Rising Edge t
SDINx Hold Time After SCLK Rising Edge t

(Note 28) 256x 512x F

t

lpw

lcks

dh1

ds

1/f

SCLK

5-ns
3-ns
5-ns

PCM Slave Mode

SCLK Frequency 32x 64x F
FS/LRCK Duty Cycle 45 55 %
FS/LRCK Edge to SCLK Rising Edge t
SDINx Setup Time Before SCLK Rising Edge t
SDINx Hold Time After SCLK Rising Edge t

lcks

ds

dh1

5-ns
3-ns
5-ns

PCM Master Mode

SCLK Frequency 64x 64x F
FS/LRCK Duty Cycle 45 55 %
FS/LRCK Edge to SCLK Rising Edge t
SDINx Setup Time Before SCLK Rising Edge t
SDINx Hold Time After SCLK Rising Edge

(VL=1.8V)

SDINx Hold Time After SCLK Rising Edge

(VL=2.5V, 3.3V, or 5V)

lcks

t

dh1

t

dh1

ds

5-ns
5-ns

11 - ns

10 - ns

-ms

50

100

(n-1)/f

SCLK

(Note 30)

kHz
kHz

S

ns

S

S

Notes:

26. After applying power to the CS4234,

RST should be held low until after the power supplies and MCLK

are stable.

27. MCLK must be synchronous to and scale with F

.

S

28. The SCLK frequency must remain less than or equal to the MCLK frequency. For this reason, SCLK
may range from 256x to 512x only in single speed mode. In double speed mode, 256x is the only ratio
supported.

29. The MSB of CH1 is always aligned with the second SCLK rising edge following FS/LRCK rising edge.

30. Where “n” is equal to the MCLK to LRCK ratio (set by the Master Clock Rate register bits), i.e. in 256x
mode, n = 256, in 512x mode, n = 512, etc.

DS899F1 18

CS4234

SDOUT1

(output )

SDINx

(input )

t

ds

SCLK

(input )

FS/LRCK

(input )

MSB

t

dh1

MSB-1

t

lcks

t

dh2

MSB MSB-1

t

dh2

t

LPW

~~~

t

ds

MSB

t

dh1

t

dh2

MSB-1

t

lcks

FS/LRCK

(input /output)

SCLK

(input /output)

SDINx

(input)

SDOUTx

(output)

MSB

MSB-1

Figure 7. PCM Serial Audio Interface Timing

Figure 6. TDM Serial Audio Interface Timing

DS899F1 19

CS4234

t

buf

t

hdst

t

hdst

t

low

t

r

t

f

t

hdd

t

high

t

sud

t

sust

t

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

t

irs

RST

Figure 8. I²C Control Port Timing

SWITCHING SPECIFICATIONS - CONTROL PORT

Test conditions (unless otherwise specified): Inputs: Logic 0 = GND = 0 V, Logic 1 = VL; SDA load capacitance equal to maxi­mum value of Cb specified below (Note 31).

Parameters Symbol Min Max Unit

SCL Clock Frequency f

RESET

Rising Edge to Start t

Bus Free Time Between Transmissions t

Start Condition Hold Time (prior to first clock pulse) t

Clock Low time t

Clock High Time t

Setup Time for Repeated Start Condition t

SDA Input Hold Time from SCL Falling (Note 33) t

SDA Output Hold Time from SCL Falling t

SDA Setup time to SCL Rising t

Rise Time of SCL and SDA t

Fall Time SCL and SDA t

Setup Time for Stop Condition t

SDA Bus Load Capacitance

SDA Pull-Up Resistance

scl

irs

buf

hdst

low

high

sust

hddi

hddo

sud

r

f

susp

C

R

p

b

- 550 kHz

(Note 32) -ns

1.3 - µs

0.6 - µs

1.3 - µs

0.6 - µs

0.6 - µs

00.9µs

0.2 0.9 µs

100 - ns

-300ns

-300ns

0.6 - µs

-400pF

500 - 

Notes:

31. All specifications are valid for the signals at the pins of the CS4234 with the specified load capacitance.

32. 2 ms + (3000/MCLK). See Section 4.2.1.

33. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

f

DS899F1 20

4. APPLICATIONS

4.1 Power Supply Decoupling, Grounding, and PCB Layout

As with any high-resolution converter, the CS4234 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 2 shows the recommended power ar­rangements, with VA connected to clean supplies. VDREG, which powers the digital circuitry, is generated
internally from an on-chip regulator from the VA supply. The VDREG pin provides a connection point for the
decoupling capacitors, as shown in Figure 2.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS4234 as pos­sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
side of the board as the CS4234 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+, VBIAS, and VQ pins in order to avoid unwanted coupling into the modulators.
The FILT+, VBIAS, and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize
the electrical path from their respective pins and GND.

For optimal heat dissipation from the package, it is recommended that the area directly under the device be
filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the back­side ground is also recommended.

4.2 Recommended Power-Up and Power-Down Sequence

CS4234

The initialization and Power-Up/Down sequence flow chart is shown in Figure 9. For the CS4234 Reset is
defined as all lines held static,
held static,

RST line is high, all PDNx bits are ‘1’. Running is defined as RST line high, all PDNx bits are ‘0’.

4.2.1 Power-up

The CS4234 enters a reset state upon the initial application of VA and VL. When these power supplies
are initially applied to the device, the audio outputs, AOUTxx, are clamped to VQ which is initially low.
Additionally, the interpolation and decimation filters, delta-sigma modulators and control port registers are
all reset and the internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and
low-pass filters are powered down. The device remains in the reset state until the

Once

RST is brought high, the control port address is latched after 2 ms + (3000/MCLK). Until this latching

transition is complete, the device will not respond to I²C reads or writes, but the I²C bus may still be used
during this time. Once the latching transition is complete, the address is latched and the control port is
accessible. At this point and the desired register settings can be loaded per the interface descriptions de­tailed in the Section 4.3 I²C Control Port. To ensure specified performance and timing, the VA_SEL must
be set to “0” for VA = 3.3 VDC and “1” for VA = 5.0 VDC before audio output begins.

After the
nominal quiescent voltage. VQ will charge to VA/2 upon initial power up. The time that it takes to charge
up to VA/2 is governed by the size of the capacitor attached to the VQ pin. With the capacitor value shown
in the typical connection diagram, the charge time will be approximately 250 ms. The gradual voltage
ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the qui­escent DC voltage. Once FS/LRCK is valid, MCLK occurrences are counted over one F
mine the MCLK/F
references will transition to their nominal voltage. Power is applied to the D/A converters and filters, and
the analog outputs are unclamped from the quiescent voltage, VQ. Afterwards, normal operation begins.

RST pin is brought high and MCLK is applied, the outputs begin to ramp with VQ towards the

RST line is pulled low. Power Down is defined as all lines (excluding MCLK)

RST pin is brought high.

period to deter-

ratio. With MCLK valid and any of the PDNx bits cleared, the internal voltage

S

S

DS899F1 21

CS4234

4.2.2 Power-down

To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn­ing off the power. In order to do this in a controlled manner, it is recommended that all the converters be
muted to start the sequence. Next, set PDNx for all converters to 1 to power them down internally. Then,
FS/LRCK and SCLK can be removed if desired. Finally, the “VQ RAMP” bit in the "DAC Control 4" register
must be set to ‘1’ for a period of 50 ms before applying reset or removing power or MCLK. During this
time, voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this
50 ms time period has passed, a transient will occur and a slight click or pop may be heard. There is no
minimum time for a power cycle. Power may be reapplied at any time.

It is important to note that all clocks should be applied and removed in the order specified in Figure 9. If
MCLK is removed or applied before
result. If either SCLK or FS/LRCK is removed or applied before all PDNx bits are set to “1”, audible pops,
clicks and/or distortion can result.

Note: Timings are approximate and based upon the nominal value of the passive components specified in the

“Typical Connection Diagram” on page 8. See Section 4.6.6.2 for volume ramp behavior.

RST has been pulled low, audible pops, clicks and/or distortion can

DS899F1 22

System

Operational

System

Unpowered

DAC1-4 Fully

Operational

ADC D ata

Available on

SDOUT1

50 ms

Apply VL, VA, and MCLK

Clear PDN DACx & ADCx bits

Apply logic level high to Mute Pin

and RC network on Standby Pin

Clear MUTE_CHx bits

Start SCLK, FS/LRCK, SDINx

Write all required configuration

settings to Control Port

Clear reset to SMPS controller

Clear Mute DAC1-4 bits

Run Speaker Diagnostics by

setting the RUN DIAG bit

(if de sired)

Ramp SMPS rails to +/- 4V

Write VA_SEL bit (in 0Fh)

appr opriat ely for VA

Clear Mute ADCx bits

Apply lo gic level low to Mute Pin
and RC network on Standby Pin

Ramp SMPS rails to +/- 4V

Set Mute ADCx bits

Set all PDN DAC & ADC bits

Stop SC LK, FS/L RCK, SDINx

Set VQ_RAM P bit

Remove VL, VA, and MCLK

Set Mute DAC1-4 bits

Set reset to SMPS controller

CS4234 C ontrol

CS44417 C ontrol

SMPS Control

CS4234 and CS 44417 Cont rol

Clear PDN_CHx bits

delay dependent
on RAM P_D IAG

pin capac itor

delay depend ent on

STBY pi n RC fi lter

delay dependent on

STBY pi n RC fi lter

VQ Ready

(> 90% of Typical)

I2C Add ress

Captured & Contr ol

Port Ready

250 ms

delay dependent

on DAC mute /

unmute beha vior

delay dependent

on DAC mute /

unmute behav ior

2 ms + (3000 /M CLK)

2 ms +

(3000 /MC LK)

250m s

DAC5 Fully
Operational

Clear Mute DAC5 (to SMPS)

delay dep endent

on DAC mute/

unmute behav ior

Set Mute DAC5 (to SMPS)

delay dependent

on DAC mute /

unmute behav ior

Set MUTE_CHx bits

Set PDN_CHx bits

Write all required configuration

settings to Control Port

Set RST

Set RST

Clear RST

CS4234

DS899F1 23

Figure 9. System Level Initialization and Power-up / Power-down Sequence

4.2.3 DAC DC Loading

~140kΩ

VA

VQ

NET

~140kΩ

S1±

RL

1+

CL

1+

AOUT1+

RL

1-

CL

1-

AOUT1-

S2±

RL

2+

CL

2+

AOUT2+

RL

2-

CL

2-

AOUT2-

S3±

RL

3+

CL

3+

AOUT3+

RL

3-

CL

3-

AOUT3-

S4±

RL

4+

CL

4+

AOUT4+

RL

4-

CL

4-

AOUT4-

S5±

RL

5+

CL

5+

AOUT5+

RL

5-

CL

5-

AOUT5-

External VQ

capacitor

Figure 10. DAC DC Loading

Figure 10 shows the analog output configuration during power-up, with the AOUTx± pins clamped to VQ

to prevent pops and clicks. Thus any DC loads (RL
es are closed. These DC loads will pull the VQ voltage down towards ground. If the parallel combination
of all DC loads exceeds the specification shown in the Analog Output Characteristics table, the VQ voltage
will never rise to its minimum operating voltage. If the VQ voltage never rises above this minimum oper­ating voltage, the device will not finish the power-up sequence and normal operation will not begin.

Also note that any AOUTx± pin(s) with a DC load must remain powered up (PDN DACx = 0) to keep the
VQ net at its nominal voltage during normal operation, otherwise clipping may occur on the outputs.

CS4234

) on the output pins will be in parallel when the switch-

x

Note that the load capacitors (CL

) are also in parallel during power-up. The amount of total capacitance

x

on the VQ net during power-up will affect the amount of time it takes for the VQ voltage to rise to its nom­inal operating voltage after VA power is applied. The time period can be calculated using the time constant
given by the internal series resistor and the load capacitors.

DS899F1 24