Cirrus Logic CS4224 User Manual

CS4223 CS4224
24-Bit 105 dB Audio Codec with Volume Control
105 dB Dynamic Range A/D Converters
105 dB Dynamic Range D/A Converters
110 dB DAC Signal-to-Noise Ratio (EIAJ)
Analog Volume Control (CS4224 only)
Differential Inputs / Outputs
On-chip Anti-aliasing and Output Smoothing
Filters
De-emphasis for 32, 44.1 and 48 kHz
Supports Master and Slave Modes
Single +5 V power supply
On-Chip Crystal Oscillator
3-5VDigitalInterface
I

Description

The CS4223/4 is a highly integrated, high performance, 24-bit, audio codec providing stereo analog-to-digital and stereo digital-to-analog converters using delta-sigma conversion techniques. The device operates from a sin­gle +5 V power supply, and features low power consumption. Selectable de-emphasis filter for 32, 44.1, and 48 kHz sample rates is also included.
The CS4224 includes an analog volume control capable of 113.5 dB attenuation in 0.5 dB steps. The analog vol­ume control architecture preserves dynamic range during attenuation. Volume control changes are imple­mented using a “soft” ramping or zero crossing technique.
Applications include digital effects processors, DAT, and multitrack recorders.
ORDERING INFORMATION
CS4223-KS -10 to +70 °C 28-pin SSOP CS4223-BS -40 to +85 °C 28-pin SSOP CS4223-DS -40 to +85 °C 28-pin SSOP CS4224-KS -10 to +70 °C 28-pin SSOP CDB4223/4 Evaluation Board
Cirrus Logic, Inc.
http://www.cirrus.com
RST
LRCK
SCLK
SDIN
SDOUT
(
)(
DIF1
SCL/CCLK SDA/CDIN AD0/CS MCLK VD VA
Serial Audio Data I nterface
)(
DIF0
Cont rol Port
Digital Filters
with De-Emphasis
Digital Filters
Clock OSC
XTI XTO
)
(
DEM0
Left
DAC
Right
DAC
Left
ADC
Right
ADC
( ) = CS4223
)
DEM1
2
IC/SPI
CopyrightCirrus Logic, Inc. 2002
V
L
Volume
Cont rol
Volume
Cont rol
DGND AGND
= CS4224
*
(All Rights Reserved)
*
*
Voltag e
Reference
Analog Low Pass
and Output St age
AOUTL+ AOUTL-
AOUTR+ AOUTR-
AINL­AINL+
AINR­AINR+
JAN ‘03
DS290F1
1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
SPECIFIED OPERATING CONDITIONS ................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
ANALOG CHARACTERISTICS ................................................................................................ 5
SWITCHING CHARACTERISTICS .......................................................................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224) ..................... 9
SWITCHING CHARACTERISTICS - CONTROL PORT - I
2. TYPICAL CONNECTION DIAGRAM CS4223 ...................................................................11
3. TYPICAL CONNECTION DIAGRAM CS4224 ...................................................................12
4. REGISTER QUICK REFERENCE - CS4224 .......................................................................... 13
5. REGISTER DESCRIPTIONS - CS4224 .................................................................................. 14
5.1 ADC Control (address 01h)............................................................................................... 14
5.1.1 Power Down ADC (PDN)............................................................................................... 14
5.1.2 Left and Right channel High Pass Filter Defeat (HPDR-HPDL)..................................... 14
5.1.3 Left and Right Channel ADC Muting (ADMR-ADML)..................................................... 14
5.1.4 Calibration Control (CAL)...............................................................................................14
5.1.5 Calibration Status (CALP) (Read Only) ......................................................................... 14
5.1.6 Clocking Error (CLKE) (Read Only) ............................................................................... 15
5.2 DAC Control (address 02h)............................................................................................... 15
5.2.1 Mute on Consecutive Zeros (MUTC) ............................................................................. 15
5.2.2 Mute Control (MUTR-MUTL).......................................................................................... 15
5.2.3 Soft RAMP Control (SOFT)............................................................................................ 15
5.2.4 Soft RAMP Step Rate (RMP).........................................................................................16
5.3 Left Channel Output Attenuator Level (address 03h) ....................................................... 16
5.4 Right Channel Output Attenuator Level (address 04h) ....................................................16
5.4.1 Attenuation level (ATT7-ATT0) ...................................................................................... 16
5.5 DSP Port Mode (address 05h) .......................................................................................... 17
5.5.1 De-emphasis Control (DEM).......................................................................................... 17
5.5.2 Serial Input/Output Data SCLK Polarity Select (DSCK)................................................. 17
CS4223 CS4224
2
C MODE (CS4224) .................... 10
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product information describes products that are in product ion, but for which full charact erization data is not yet available. "Advance" product informa­tion describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") bel ieve that the information contained in this document is accurate and r eliable. However, the information is subject to change without notice and is provided "AS IS" wi thout warranty of any kind (express or i mplied). Customers are advised to obtain the latest version of relevant informati on to verify, before placing orders, that informati on being rel ied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of l iability. No responsibility is assumed by Cirrus for the use of this informati on, including use of this information as the basis for manufactur e or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirr us and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intel lectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for gener al distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies descri bed in thismaterial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of t he Chinese Government if any of the products or technologies described in thi s material is subj ect to t he PRC Foreign Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP­ERTY OR ENVIRONMENTAL DAMAGE ( "CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESI GNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RI SK.
Purchase of I those components in a standard I
Cirrus Logic, Cirrus, and the Cirrus Logi c logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names i n this document may be trademarks or servi ce marks of their respective owners.
2 DS290F1
2
C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philli ps I2C Patent Rights to use
2
Csystem.
CS4223 CS4224
5.5.3 Serial Data Output Format (DOF).................................................................................. 17
5.5.4 Serial Data Input Format (DIF) ...................................................................................... 17
5.6 Converter Status Report (Read Only) (address 06h) ....................................................... 18
5.6.1 Left and Right Channel Acceptance Bit (ACCR-ACCL) ................................................ 18
5.6.2 Left and Right Channel ADC Output Level (LVR and LVL) ........................................... 18
5.7 Master Clock Control (address 07h)................................................................................. 18
5.7.1 Master Clock Control (MCK).......................................................................................... 18
6. PIN DESCRIPTIONS CS4223 ............................................................................................ 19
7. PIN DESCRIPTIONS CS4224 ............................................................................................ 21
8. APPLICATIONS ..................................................................................................................... 23
8.1 Overview .......................................................................................................................... 23
8.2 Grounding and Power Supply Decoupling ....................................................................... 23
8.3 High Pass Filter ...............................................................................................................23
8.4 Analog Outputs ................................................................................................................23
8.5 Master vs. Slave Mode .................................................................................................... 23
8.6 De-emphasis ................................................................................................................... 23
8.7 Power-up / Reset / Power Down Calibration ................................................................... 23
8.8 Control Port Interface (CS4224 only) .............................................................................. 24
8.8.1 SPI Mode ............................................................................................................ 24
2
8.8.2 I
8.9 Memory Address Pointer (MAP)....................................................................................... 25
8.9.1 Auto-Increment Control (INCR) ..................................................................................... 25
8.9.2 Register Pointer (MAP).................................................................................................. 25
9. ADC/DAC FILTER RESPONSE.............................................................................................. 29
10. PARAMETER DEFINITIONS................................................................................................. 30
11. PACKAGE DIMENSIONS ..................................................................................................... 31
C Mode ............................................................................................................. 24

LIST OF FIGURES

Figure 1. Serial Audio Port Data I/O Timing ............................................................................ 8
Figure 2. SPI Control Port Timing............................................................................................ 9
Figure 3. I
Figure 4. CS4223 Recommended Connection Diagram ....................................................... 11
Figure 5. CS4224 Recommended Connection Diagram ....................................................... 12
Figure 6. Control Port Timing, SPI mode............................................................................... 25
Figure 7. Control Port Timing, I
Figure 8. Serial Audio Format 0 (I2S).................................................................................... 26
Figure 9. Serial Audio Format 1............................................................................................. 26
Figure 10. Serial Audio Format 2............................................................................................. 26
Figure 11. Serial Audio Format 3............................................................................................. 27
Figure 12. Optional Input Buffer .............................................................................................. 27
Figure 13. Single-ended Input Application............................................................................... 27
Figure 14. 2- and 3-Pole Butterworth Filters............................................................................ 28
Figure 15. De-emphasis Curve................................................................................................ 28
Figure 16. Hybrid Analog/Digital Attenuation........................................................................... 28
Figure 17. ADC Filter Response.............................................................................................. 29
Figure 18. ADC Passband Ripple............................................................................................ 29
Figure 19. ADC Transition Band.............................................................................................. 29
Figure 20. DAC Filter Response.............................................................................................. 29
Figure 21. DAC Passband Ripple............................................................................................ 29
Figure 22. DAC Transition Band.............................................................................................. 29
2
C Control Port Timing .......................................................................................... 10
2
C mode ............................................................................... 25
DS290F1 3

LIST OF TABLES

Table 1. Example Volume Settings ...............................................................................................16
Table 2. Common Clock Frequencies ........................................................................................... 19
Table 3. Digital Interface Format - DIF1 and DIF0 .......................................................................20
Table 4. De-emphasis Control.......................................................................................................20
Table 5. Common Clock Frequencies ........................................................................................... 21
CS4223 CS4224
4 DS290F1
CS4223 CS4224

1. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T

SPECIFIED OPERATING CONDITIONS

(AGND, DGND = 0 V, all voltages with respect to 0 V.)
Power Supplies Digital
Ambient Operating Temperature Commercial (-KS)

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.)

Power Supplies Digital
Input Current (Note 1) - ±10 mA
Analog Input Voltage (Note 2) -0.7 VA + 0.7 V
Digital Input Voltage (Note 2) -0.7 VD + 0.7 V
Ambient Temperature Power Applied -55 +125 °C
Storage Temperature -65 +150 °C
=25°C.)
A
Parameter Symbol Min Nom Max Unit
VD
Analog
Digital
|VA-VD|
Industrial (-BS/-DS)
Parameter Symbol Min Max Unit
Analog
VA VL
T
T
VD
VA
AC
AI
4.75
4.75
2.7
-
-10
-40
-0.3
-0.3
5.0
5.0
5.0
-
-
-
6.0
6.0
5.25
5.25
5.25
0.4
70 85
V V V V
°C °C
V V
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 1. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR
latch-up.
2. The maximum over or under voltage is limited by the input current.
DS290F1 5
CS4223 CS4224

ANALOG CHARACTERISTICS (Full Scale Input Sine wave, 997 Hz; Fs = 48 kHz; Measurement

Bandwidth is 20 Hz to 20 kHz; Local components as shown in Figures 4 and 5.)
CS4223/4 - KS CS4223/4 - BS/ - DS
Parameter Symbol
Analog Input Characteristics
Total Harmonic Distortion THD - 0.0014 - - 0.0014 - %
Dynamic Range A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 3) THD+N - -97 -90 - -97 -87 dB
Interchannel Isolation (1 kHz) - 90 - - 90 - dB
Interchannel Gain Mismatch - - 0.1 - - 0.1 dB
Offset Error with High Pass Filter - - 0 - - 0 LSB
Full Scale Input Voltage (Differential) 1.9 2.0 2.1 1.9 2.0 2.1 Vrms
Gain Drift - 100 - - 100 - ppm/°C
Input Resistance 10 - - 10 - - k
Input Capacitance - - 15 - - 15 pF
Common Mode Input Voltage - 2.3 - - 2.3 - V
Common Mode Rejection Ratio CMRR 75 - - 75 - - dB
A/D Decimation Filter Characteristics
Passband (Note 4) 0 - 21.8 0 - 21.8 kHz
Passband Ripple - - ±0.01 - - ±0.01 dB
Stopband (Note 4) 30 - 6114 30 - 6114 kHz
Stopband Attenuation (Note 5) 80 - - 80 - - dB
Group Delay (Fs = Output Sample Rate) Left (Note 6) Right
Group Delay Variation vs. Frequency ∆t
High Pass Filter Characteristics
Frequency Response -3 dB (Note 4)
-0.1 dB
Phase Deviation @ 20 Hz (Note 4) - 10 - - 10 - Degree
Passband Ripple - - 0 - - 0 dB
t
gd_L
t
gd_R
gd
98 95
105 102
-
18/Fs
-
17/Fs
--0--0µs
-
-
3.7 20
-
-
-
-
-
-
95 92
105 102
-
18/Fs
-
17/Fs
-
-
3.7 20
UnitMin Typ Max Min Typ Max
-
-
-
-
-
-
dB dB
s s
Hz Hz
Notes: 3. Referenced to typical full-scale differential input voltage (2 Vrms).
4. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the
0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs.
5. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz ±21.8 kHz where n = 0,1,2,3...).
6. Group delay for Fs = 48 kHz, t
6 DS290F1
= 18/48 kHz = 375 µs.
gd
CS4223 CS4224
ANALOG CHARACTERISTICS (CONTINUED)
CS4223/4 - KS CS4223/4 - BS/ - DS
Parameter Symbol
Analog Output Characteristics - Minimum Attenuation, 10 k, 100 pF load; unless otherwise specified.
Signal-to-Noise, Idle-Channel Noise (CS4224 only) DAC muted, A-weighted
Dynamic Range DAC not muted, A-weighted
DAC not muted, unweighted
Total Harmonic Distortion THD - 0.0014 - - 0.0014 - %
Total Harmonic Distortion + Noise THD+N - -97 -92 - -97 -87 dB
Interchannel Isolation (1 kHz) - 90 - - 90 - dB
Interchannel Gain Mismatch - - 0.1 - - 0.1 dB
Attenuation Step Size All Outputs 0.35 0.5 0.65 0.35 0.5 0.65 dB
Programmable Output Attenuation Span 110 113.5 - 110 113.5 - dB
Differential Offset Voltage - ±10 - - ±10 - mV
Common Mode Output Voltage - 2.4 - - 2.4 - V
Full Scale Output Voltage 1.8 1.9 2.0 1.8 1.9 2.0 Vrms
Gain Drift - 100 - - 100 - ppm/°
Out-of-Band Energy Fs/2 to 2 Fs - -60 - - -60 - dBFs
Analog Output Load Resistance
Capacitance
Combined Digital and Analog Filter Characteristics
Frequency Response10 Hz to 20 kHz - ±0.1 - - ±0.1 - dB
Deviation from Linear Phase - ±0.5 - - ±0.5 - Degree
Passband: to 0.01 dB corner (Notes 7 and 8) 0 - 21.8 0 - 21.8 kHz
Passband Ripple (Note 8) - - ±0.01 - - ±0.01 dB
Stopband (Notes 7 and 8) 26.2 - - 26.2 - - kHz
Stopband Attenuation (Note 9) 70 - - 70 - - dB
Group Delay (Fs = Input Sample Rate) Left
Right
Power Supply
Power Supply Current VA
Total Power Down
Power Supply Rejection Ratio 1 kHz - 65 - - 65 - dB
VD
VL
t
gd_L
t
gd_R
102 110 - 97 110 - dB
10097105
102
10
-
-
-
-
-
-
-
-
-
26/Fs 27/Fs
46
9 3
0.4
-
-
-
100
-
-
60 20
5
-
95 92
10
105 102
-
-
-
-
-
-
-
-
-
26/Fs 27/Fs
46
9 3
0.4
100
60 20
UnitMin Typ Max Min Typ Max
-
-
-
-
-
5
-
dB dB
C
k pF
s s
mA mA mA mA
Notes: 7. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 48 kHz,
the 0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.5465x Fs.
8. Digital filter characteristics.
9. Measurement bandwidth is 10 Hz to 3 Fs.
DS290F1 7
CS4223 CS4224
DIGITAL CHARACTERISTICS
Parameter Symbol Min Max Unit
High-level Input Voltage VL = 5V
VL = 3V
Low-level Input Voltage V
High-level Output Voltage at I
Low-level Output Voltage at I
=-2.0mA V
O
=2.0mA V
O
V
IH
V
IH
IL
OH
OL
2.8
2.0
-0.3 0.8 V
VL - 1.0 - V
-0.5V
Input Leakage Current Digital Inputs - 10 µA
Output Leakage Current High Impedance Digital Outputs - 10 µA
VL + 0.3 VL + 0.3
V V
8 DS290F1
CS4223 CS4224

SWITCHING CHARACTERISTICS (Outputs loaded with 30 pF)

Parameter Symbol Min Typ Max Unit
Audio ADC’s and DAC’s Sample Rate Fs 4 - 50 kHz
XTI Frequency XTI = 256, 384, or 512 Fs 1.024 - 26 MHz
XTI Pulse Width High XTI = 512 Fs
XTI = 384 Fs XTI = 256 Fs
XTI Pulse Width Low XTI = 512 Fs
XTI = 384 Fs XTI = 256 Fs
XTI Jitter Tolerance - 500 - psRMS
Low Time (Note 10) 10 - - ms
RST
SCLK falling edge to SDOUT output valid DSCK = 0 t
LRCK edge to MSB valid t
SDIN setup time before SCLK rising edge DSCK = 0 t
SDIN hold time after SCLK rising edge DSCK = 0 t
SCLK Period t
SCLK High Time t
SCLK Low Time t
SCLK rising to LRCK edge DSCK = 0 t
LRCK edge to SCLK rising DSCK = 0 t
dpd
lrpd
ds
dh
sckw
sckh
sckl
lrckd
lrcks
13 21 31
13 21 31
-- ns
-
-
-
-
-
-
-
-
-
-
-
-
1
---------------------- 2 0+ (384) Fs
ns ns ns
ns ns ns
--45ns
25 - - ns
25 - - ns
1
---------------------­(128) Fs
--ns
40 - - ns
40 - - ns
35 - - ns
40 - - ns
Notes: 10. After powering up the CS4223/4, PDN should be held low for 10 ms to allow the power supply to settle.
LRCK
t
lrckd
SCLK*
SDIN
SDOUT
*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.
t
lrpd
t
lrcks
t
ds
t
sckh
t
dh
MSB MSB-1
t
sckw
t
sckl
t
dpd

Figure 1. Serial Audio Port Data I/O Timing

DS290F1 9
CS4223 CS4224

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224)

(Inputs: Logic 0 = DGND, Logic 1 = VD; CL=30pF)
Parameter Symbol Min Max Unit
SPI Mode (SPI
/I2C = 0)
CCLK Clock Frequency f
RST
rising edge to CS falling (Note 11) t
CCLK edge to CS
High Time between transmissions t
CS
CS
falling to CCLK edge t
falling (Note 12) t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK rising setup time t
CCLKrisingtoDATAholdtime (Note13) t
Rise time of CCLK and CDIN (Note 14) t
Fall time of CCLK and CDIN (Note 14) t
Notes: 11. Not tested but guaranteed by design.
12. t
only needed before first falling edge of CS after RST rising edge. t
spi
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F
SCK
<1MHz.
sck
srs
spi
csh
css
scl
sch
dsu
dh
r2
f2
-6MHz
41 - µs
500 - ns
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
- 100 ns
- 100 ns
= 0 at all other times.
spi
RST
CS
CCLK
CDIN
t
srs
t
t
css
spi
t
r2

Figure 2. SPI Control Port Timing

t
t
scl
t
t
f2
dsu
sch
t
dh
t
csh
10 DS290F1
CS4223 CS4224

SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MODE (CS4224)

(Inputs: Logic 0 = DGND, Logic 1 = VD; CL=30pF)
Parameter Symbol Min Max Unit
2C®
Mode (SPI/I2C = 1)
I
SCL Clock Frequency f
RST
rising edge to Start (Note 15)
Bus Free Time between transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup time for repeated Start Condition t
SDAholdtimeforSCLfalling (Note16) t
SDA setup time to SCL rising t
Rise time of SCL t
Fall time of SCL t
Rise time of SDA t
Fall time of SDA t
Setup time for Stop Condition t
scl
t
irs
buf
hdst
low
high
sust
hdd
sud
rc
fc
rd
fd
susp
- 100 kHz
50 - µs
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-25ns
-25ns
-1µs
- 300 ns
4.7 - µs
Notes: 15. Not tested but guaranteed by design.
16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t
irs
Stop Start
SDA
SCL
t
buf
t
t
hdst
low
t
hdd
t
high
t
sud
Repeated
Start
t
sust
t
hdst
t
rd
t
fc
t
rc
Stop
t
fd
t
susp

Figure 3. I2C Control Port Timing

DS290F1 11
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