Cirrus Logic CS4221 User Manual

CS4220 CS4221
24-Bit Stereo Audio Codec with 3V Interface

Features

l 100 dB Dynamic Range A/D Converters l 100 dB Dynamic Range D/A Converters l 105 dB DAC Signal-to-Noise Ratio (EIAJ) l Analog Volume Control (CS4221 only) l Differential Inputs / Outputs l On-chip Anti-aliasing and Output Smoothing
Filters
l De-emphasis for 32, 44.1 and 48 kHz l Supports Master and Slave Modes l Single +5 V powe r supp l y l On-Chip Crystal Oscillator l 3 - 5 V Digital Interface
I

Description

The CS4220/1 is a hig hly integ rated , high p erforma nce, 24-bit, audio codec providing stereo analog-to-digital and stereo digital-to -analog converters using del ta-sig­ma conversion te chniques. The de vice opera tes from a single +5 V power supply, and features low power con­sumption. Selectable de-emphasis filter for 32, 44.1, and 48 kHz sample rates is also included.
The CS4221 also includes an analog volume control ca­pable of 113.5 dB attenuation in 0.5 dB steps. The analog volume control architecture preserves dynamic range during atte nuation. Volume control changes are
implemented using a “soft” ramping or zero crossing technique.
Applications include digital effects processors, DAT, and multitrack recorders.
ORDERING INFORMATION
CS4220-KS -10 to +70 °C 28-pin SSOP CS4221-KS -10 to +70 °C 28-pin SSOP CDB4220/1 Evaluation Board
(
)(
DIF1
SCL/CCLK SDA/CDIN AD0/CS MCLK VD VA
RST
LRCK
SCLK
SDIN
SDOUT
Serial AudioData Interface
Preliminary Product Information
)(
DIF0
Control Port
Digital Filters
with De-Emphasis
Digital Filters
Clock OSC
XTI XTO
)
(
DEM0
DEM1
2
IC/SPI
Left
DAC
Right
DAC
Left
ADC
Right
ADC
()=CS4220
)
*
V
L
Volume
Control
Volume
Control
DGND AGND
=CS4221
*
*
Voltage
Reference
Analog Low Pass
AOUTL+ AOUTL-
AOUTR+
and Output Stage
AOUTR-
AINL­AINL+
AINR­AINR+
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
APR ‘00
DS284PP3
1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS .................................. ....... ...... ....... ...... ....... ..... 4
ANALOG CHARACTERISTICS ............................................................................................... 4
ABSOLUTE MAXIMUM RATINGS ..........................................................................................6
RECOMMENDED OPERATING CONDITIONS ...................................................................... 6
SWITCHING CHARACTERISTICS ................... ....... ...... ...... ....................................... ....... ..... 7
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221) ....................8
SWITCHING CHARACTERISTICS - CONTROL PORT - I
2. TYPICAL CONNECTION DIAGRAM — CS4220 ...................................................................10
3. TYPICAL CONNECTION DIAGRAM — CS4221 ...................................................................11
4. REGISTER QUICK REFERENCE - CS4221 ..........................................................................12
5. REGISTER DESCRIPTIONS - CS4221 ..................................................................................13
5.1 ADC Control (address 01h) ..............................................................................................13
5.1.1 Power Down ADC (PDN) ....................................................................................... 13
5.1.2 Left and Right channel High Pass Filter Defeat (HPDR-HPDL) .............................13
5.1.3 Left and Right Channel ADC Muting (ADMR-ADML) .............................................13
5.1.4 Calibration Control (CAL) .......................................................................................13
5.1.5 Calibration Status (CALP) (Read Only) ..................................................................13
5.1.6 Clocking Error (CLKE) (Read Only) .......................................................................14
5.2 DAC Control (address 02h) ..............................................................................................14
5.2.1 Mute on Consecutive Zeros (MUTC) ...................................................................... 14
5.2.2 Mute Control (MUTR-MUTL) ..................................................................................14
5.2.3 Soft RAMP Control (SOFT) ....................................................................................14
5.2.4 Soft RAMP Step Rate (RMP) .................................................................................15
5.3 Left Channel Output Attenuator Level (address 03h) ......................................................15
5.4 Right Channel Output Attenuator Level (address 04h) ...................................................15
5.4.1 Attenuation level (ATT7-ATT0) ............................................................................... 15
5.5 DSP Port Mode (address 05h) .........................................................................................16
5.5.1 De-emphasis Control (DEM) ..................................................................................16
5.5.2 Serial Input/Output Data SCLK Polarity Select (DSCK) .........................................16
5.5.3 Serial Data Output Format (DOF) ..........................................................................16
5.5.4 Serial Data Input Format (DIF) ...............................................................................16
5.6 Converter Status Report (Read Only) (address 06h) .......................................................17
5.6.1 Left and Right Channel Acceptance Bit (ACCR-ACCL) .........................................17
5.6.2 Left and Right Channel ADC Output Level (LVR and LVL) .................................... 17
5.7 Master Clock Control (address 07h) ................................................................................ 17
CS4220 CS4221
2
C MODE (CS4221) .....................9
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I2C is a registered trademark of Ph ilips Semiconductor. SPI is a registered trademark of International Business Machines Corporation.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor­mation describes pr oducts which are in development and subj ect t o devel opment changes. Ci rrus Logic, Inc. has made best efforts to e nsure that the infor­mation contained i n this document is accurate and reli able. However, the information i s subject to chang e without notice an d is provided “AS IS” without
warranty of any kind (ex p res s or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this in for mation, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reprod uced, stor ed i n a retr i eval system, or transmitted, in any form or by any means (electronic, mechanical, pho­tographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (elec­tronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of an y item s witho ut the pri o r wr it ten consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in so me ju ris diction s. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS284PP3
5.7.1 Master Clock Control (MCK) .................................................................................. 17
6. PIN DESCRIPTIONS — CS4220 ............................................................................................ 18
7. PIN DESCRIPTIONS — CS4221 ............................................................................................ 20
8. APPLICATIONS ..................................................................................................................... 22
8.1 Overview .......................................................................................................................... 22
8.2 Grounding and Power Supply Decoupling ....................................................................... 22
8.3 High Pass Filter ............................................................................................................... 22
8.4 Analog Outputs ................................................................................................................ 22
8.5 Master vs. Slave Mode .................................................................................................... 22
8.6 De-emphasis ................................................................................................................... 22
8.7 Power-up / Reset / Power Down Calibration ................................................................... 22
8.8 Control Port Interface (CS4221 only) .............................................................................. 23
8.8.1 SPI Mode ............................................................................................................ 23
8.8.2 I
8.9 Memory Address Pointer (MAP) ...................................................................................... 24
8.9.1 Auto-Increment Control (INCR) .............................................................................. 24
8.9.2 Register Pointer (MAP) .......................................................................................... 24
9. ADC/DAC FILTER RESPONSE ............................................................................................. 28
10. PARAMETER DEFINITIONS ................................................................................................ 29
11. PACKAGE DIMENSIONS .................................................................................................... 30
LIST OF FIGURES
CS4220 CS4221
2
C Mode ............................................................................................................. 23
Figure 1. Serial Audio Port Data I/O Timing .................................................................................. 7
Figure 2. SPI Control Port Timing ................................................................................................. 8
Figure 3. I
Figure 4. CS4220 Recommended Connection Diagram ............................................................. 10
Figure 5. CS4221 Recommended Connection Diagram ............................................................. 11
Figure 6. Control Port Timing, SPI mode .................................................................................... 24
Figure 7. Control Port Timing, I
Figure 8. Serial Audio Format 0 (I2S) .........................................................................................25
Figure 9. Serial Audio Format 1 .................................................................................................. 25
Figure 10. Serial Audio Format 2 ................................................................................................ 25
Figure 11. Serial Audio Format 3 ................................................................................................ 26
Figure 12. Optional Input Buffer .................................................................................................. 26
Figure 13. Single-ended Input Application .................................................................................. 26
Figure 14. 2- and 3-Pole Butterworth Filters ............................................................................... 27
Figure 15. Hybrid Digital/Analog Attenuation .............................................................................. 27
Figure 16. De-emphasis Curve ................................................................................................... 27
Figure 17. Hybrid Analog/Digital Attenuation .............................................................................. 27
Figure 18. ADC Filter Response ................................................................................................. 28
Figure 19. ADC Passband Ripple ............................................................................................... 28
Figure 20. ADC Transition Band ................................................................................................. 28
Figure 21. DAC Filter Response ................................................................................................. 28
Figure 22. DAC Passband Ripple ............................................................................................... 28
Figure 23. DAC Transition Band ................................................................................................. 28
2
C Control Port Timing .................................................................................................. 9
LIST OF TABLES
2
C mode ..................................................................................... 24
Table 1. Example Volume Settings............................................................................................... 15
Table 2. Common Clock Frequencies........................................................................................... 18
Table 3. Digital Interface Format - DIF1 and DIF0....................................................................... 19
Table 4. De-emphasis Control ...................................................................................................... 19
Table 5. Common Clock Frequencies........................................................................................... 20
DS284PP3 3

1. CHARACTERISTICS AND SPECIFICATIONS

CS4220 CS4221

ANALOG CHARACTERISTICS (T

Fs = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in Figures 4 and 5; SPI mode, Format 0, unless otherwise specified.)
Parameter Symbol
= 25° C; VA, VD = +5 V; Full Scale Input Sine wave, 997 Hz;
A
CS4220/1 - KS
UnitMin Typ Max
Analog Input Characteristics
ADC Resolution - - 24 Bits Total Harmonic Distortion THD - 0.003 - % Dynamic Range A-weighted
unweighted Total Harmonic Distortion + Noise (Note 1) THD+N - -92 -87 dB Interchannel Isolation (1 kHz) - 90 - dB Interchannel Gain Mismatch - - 0.1 dB Offset Error with High Pass Filter - - 0 LSB Full Scale Input Voltage (Differential) 1.9 2.0 2.1 Vrms Gain Drift - 100 - ppm/°C Input Resistance 10 - - k Input Capacitance - - 15 pF Common Mode Input Voltage - 2.3 - V
95 92
100
97
-
-
dB
A/D Decimation Filter Characteristics
Passband (Note 2) 0 - 21.8 kHz Passband Ripple - - ±0.01 dB Stopband (Note 2) 30 - 6114 kHz Stopband Attenuation (Note 3) 80 - - dB Group Delay (Fs = Output Sampl e Rate)
(Note 4)
Group Delay Variation vs. Frequency t
t
gd
gd
-15/Fs- s
--0µs
High Pass Filter Characteristics
Frequency Response -3 dB (Note 2)
-0.1 dB Phase Deviation @ 20 Hz (Note 2) - 10 - Degree Passband Ripple - - 0 dB
-
-
3.7 20
-
-
Hz
Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms).
2. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the
0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs.
3. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz ±21.8 kHz where n = 0,1,2,3...).
4. Group delay for Fs = 48 kHz, t
4 DS284PP3
= 15/48 kHz = 312 µs.
gd
CS4220 CS4221
ANALOG CHARACTERISTICS (CONTINUED)
CS4220/1 - KS
Parameter Symbol
Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified.
DAC Resolution - - 24 Bits Signal-to-Noise, Idle-Channel Noise (CS4221 only) DAC
muted, A-weighted
Dynamic Range DAC not muted, A-weighted
DAC not muted, unweighted Total Harmonic Distortion THD - 0.003 - % Total Harmonic Distortion + Noise THD+N - -92 -87 dB Interchannel Isolation (1 kHz) - 90 - dB Interchannel Gain Mismatch - - 0.1 dB Attenuation Step Size All Outputs 0.35 0.5 0.65 dB Programmable Output Attenuation Span 110 113.5 - dB Differential Offset Voltage - ±10 - mV
Common Mode Output Voltage - 2.4 - V Full Scale Output Voltage 1.8 1.9 2.0 Vrms Gain Drift - 100 - ppm/°
Out-of-Band Energy Fs/2 to 2 Fs - -60 - dBFs Analog Output Load Resistance
Capacitance
97 105 - dB
95 92
10
-
100
97
-
-
-
-
-
100
Combined Digital and Analog Filter Characteristics
Frequency Response10 Hz to 20 kHz - ±0.1 - dB Deviation from Linear Phase - ±0.5 - Degree Passband: to 0.01 dB corner (Notes 5 and 6) 0 - 21.8 kHz Passband Ripple (Note 6) - - ±0.01 dB Stopband (Notes 5 and 6) 26.2 - - kHz Stopband Attenuation (Note 7) 70 - - dB Group Delay (Fs = Input Word Rate) t
gd
-16/Fs- s
Power Supply
Power Supply Current VA
VD
VL
Total Power Down
Power Supply Rejection Ratio 1 kHz - 65 - dB
-
-
-
-
46
9 3
0.4
60 20
5
-
UnitMin Typ Max
dB
C
k pF
mA
Notes: 5. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 48 kHz,
the 0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.5465x Fs.
6. Digital filter characteristics.
7. Measurement bandwidth is 10 Hz to 3 Fs.
DS284PP3 5
CS4220 CS4221
DIGITAL CHARACTERISTICS (T
= 25° C; VA, VD = 4.75V - 5.25V)
A
Parameter Symbol Min Max Unit
High-level Input Voltage VL = 5V
VL = 3V Low-level Input Voltage V High-level Output Voltage at I
Low-level Output Voltage at I
= -2.0 mA V
O
= 2.0 mA V
O
V
IH
V
IH IL
OH OL
2.8
2.0
VL + 0.3 VL + 0.3
-0.3 0.8 V
VL - 1.0 - V
-0.5V
Input Leakage Current Digital Inputs - 10 µA Output Leakage Current High Impedance Digital Outputs - 10 µA

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.)

Parameter Symbol Min Max Unit
Power Supplies Digital
Analog Input Current (Note 8) - ±10 mA Analog Input Voltage (Note 9) -0.7 VA + 0.7 V Digital Input Voltage (Note 9) -0.7 VD + 0.7 V Ambient Temperature Power Applied -55 +125 °C Storage Temperature -65 +150 °C
VD
VA
-0.3
-0.3
6.0
6.0
V V
V

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND = 0 V, all voltages with respect to 0 V.)
Parameter Symbol Min Typ Max Unit
Power Supplies Digital
Analog
Digital
| VA - VD |
Ambient Operating Temperature T
Notes: 8. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR
latch-up .
9. The maximum over or under voltage is limited by the input current.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
VD
VA VL
4.75
4.75
2.7
-
A
-10 25 70 °C
5.0
5.0
5.0
-
5.25
5.25
5.25
0.4
V
6 DS284PP3
CS4220 CS4221

SWITCHING CHARACTERISTICS (T

= 25° C; VA, VD = 4.75 V - 5.25 V; outputs loaded with
A
30 pF)
Parameter Symbol Min Typ Max Unit
Audio ADC’s and DAC’s Sample Rate Fs 4 - 50 kHz XTI Frequency XTI = 256, 384, or 512 Fs 1.024 - 26 MHz XTI Pulse Width High XTI = 512 Fs
XTI = 384 Fs XTI = 256 Fs
XTI Pulse Width Low XTI = 512 Fs
XTI = 384 Fs XTI = 256 Fs
13 21 31
13 21 31
-
-
-
-
-
-
-
ns
-
-
-
ns
-
-
XTI Jitter Tolerance - 500 - psRMS
Low Time (Note 10) 10 - - ms
RST
1
SCLK falling edge to SDOUT output valid DSCK = 0 t LRCK edge to MSB valid t SDIN setup time before SCLK rising edge DSCK = 0 t SDIN hold time after SCLK rising edge DSCK = 0 t SCLK Period t SCLK High Time t SCLK Low Time t SCLK rising to LRCK edge DSCK = 0 t LRCK edge to SCLK rising DSCK = 0 t
dpd lrpd
ds
dh sckw sckh
sckl lrckd lrcks
-- ns
- - 45 ns 25 - - ns 25 - - ns
1
------------------- --­(128) Fs
40 - - ns 40 - - ns 35 - - ns 40 - - ns
------------------- ---20+ (384) Fs
--ns
Notes: 10. After powering up the CS4220/1, PDN should be held low for 10 ms to allow the power supply to settle.
LRCK
t
lrckd
SCLK*
SDIN
SDOUT
*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.
t
lrpd
t
lrcks
t
sckh
t
ds
t
dh
MSB MSB-1
t
sckw
t
sckl
t
dpd

Figure 1. Serial Audio Port Data I/O Timing

DS284PP3 7
CS4220 CS4221

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221)

(TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF)
Parameter Symbol Min Max Unit
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequency f
rising edge to CS falling (Note 11) t
RST CCLK edge to CS
High Time between transmissions t
CS
falling to CCLK edge t
CS
falling (Note 12) t
CCLK Low Time t CCLK High Time t CDIN to CCLK rising setup time t CCLK rising to DATA hold time (Note 13) t Rise time of CCLK and CDIN (Note 14) t Fall time of CCLK and CDIN (Note 14) t
Notes: 11. Not tested but guaranteed by design .
12. t
only needed before first falling edge of CS after RST rising edge. t
spi
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F
< 1 MHz.
SCK
sck srs
spi csh css
scl
sch dsu
dh
r2 f2
-6MHz
41 - µs
500 - ns
1.0 - µs 20 - ns 66 - ns 66 - ns 40 - ns 15 - ns
-100ns
-100ns
= 0 at all other times.
spi
RST
CS
CCLK
CDIN
t
srs
t
t
css
spi
tr2t
t
t
scl
t
f2
dsu
sch
t
dh
t
csh

Figure 2. SPI Control Port Timing

8 DS284PP3
CS4220 CS4221

SWITCHING CHARACTERISTICS - CONTROL PORT - I2C MODE (CS4221)

(TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF)
Parameter Symbol Min Max Unit
I2C® Mode (SPI/I2C = 1)
SCL Clock Frequency f
rising edge to Start (Note 15)
RST
Bus Free Time between transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low Time t Clock High Time t Setup time for repeated Start Condition t SDA hold time for SCL falling (Note 16) t SDA setup time to SCL rising t Rise time of SCL t Fall time of SCL t Rise time of SDA t Fall time of SDA t Setup time for Stop Condition t
scl
t
irs
buf
hdst
low high sust
hdd sud
rc fc rd fd
susp
-100kHz
50 - µs
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs 0-µs
250 - ns
-25ns
-25ns
-1µs
-300ns
4.7 - µs
Notes: 15. Not tested but guaranteed by design .
16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t
irs
Stop Start
SDA
SCL
t
buf
t
t
hdst
low
t
hdd
t
high
t
sud
Repeated
Start
t
sust
t
t
hdst
Stop
rd
t
rc
t
fd
t
fc
t
susp

Figure 3. I2C Control Port Timing

DS284PP3 9

2. TYPICAL CONNECTION DIAGRAM — CS4220

CS4220 CS4221
+5V
Supply
Ferrite Bead
150
150
150
150
Mode Selection
R=500
s
* Required for
Master Mode only
+ 0.1 µF
1 µF
20
2.2 nF
AINL+
19
AINL-
17
16
10 11 27
1
14 15
28
AINR+
AINR-
DIF1
DIF0
RST
NC NC
NC NC
2.2 nF
2
21 6
VA VD
AOUTL+
AOUTL-
AOUTR+
AOUTR-
DEM1
DEM0
CS4220
SCLK LRCK
SDOUT
AGND DGND
22 7
VL
XTI
XTO
SDIN
0.1 µF + 1µF
13
25
Digital Audio
40 pF
R
R R
R
*
47 k
Analog Filter
Analog Filter
s
s s
s
26 24
23 18
12
3
2
5 4 9 8
0.1 µF + 1µF
Source
40 pF
Eliminate the crystal and capacitors when using an external clock input
Audio
DSP
+2.7 - 5V
External Clock Input

Figure 4. CS4220 Recommended Connection Diagram

(Also see
Recommended Layout Diagram
)
10 DS284PP3

3. TYPICAL CONNECTION DIAGRAM — CS4221

CS4220 CS4221
+5V
Supply
Ferrite Bead
+ 0.1 µF
1 µF
150
150
150
150
Microcontroller AD0/CS
R = 500
s
* Required fo r
Master Mode only
20
2.2 nF 19
17
2.2 nF 16
10 11 12 27 18
1
14 15
28
2
21 6
VA VD
AINL+
AINL-
AINR+
CS4221
AINR-
SCL/CCLK SDA/CDIN
RST I2C/SPI
NC NC
NC NC
AGND DGND
22 7
VL
AOUTL+
AOUTL-
AOUTR+
AOUTR-
XTI
XTO
SCLK LRCK
SDIN
SDOUT
0.1 µF + 1µF
13
25
40 pF
* 47 k
R R R R
Analog Filter
Analog Filter
s s s s
26 24
23
3
2
5 4 9 8
0.1 µF + 1µF
External
40 pF
Eliminate the crystal and capacitorswhen using an external clock input
Audio
DSP
Clock Input
+2.7 - 5V

Figure 5. CS4221 Recommended Connection Diagram

(Also see
Recommended Layout Diagram
)
DS284PP3 11
CS4220 CS4221

4. REGISTER QUICK REFERENCE - CS4221

Addr Function 7 6 5 4 3 2 1 0
0h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 0 0 0 0 0 0 0 0
1h ADC Control PDN HPDR HPDL ADMR ADML CAL CALP CLKE
default 0 0 0 0 0 0 0 0
2h DAC Control Reserved MUTC MUTR MUTL SOFT Reserved RMP1 RMP0
default 0 0 0 0 0 0 0 0
3h-4h Output Attenuator
Level
default 0 0 0 0 0 0 0 0
5h DSP Port Mode Reserved DEM1 DEM0 DSCK DOF1 DOF0 DIF1 DIF0
default 0 0 0 0 0 0 0 0
6h Converter Status
Report
default 0 0 0 0 0 0 0 0
7h Master Clock Con-
trol
default 0 0 0 0 0 0 0 0
ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
ACCR ACCL LVR2 LVR1 LVR0 LVL2 LVL1 LVL0
Reserved Reserved Reserved Reserved Reserved Reserved MCK1 MCK0
12 DS284PP3
CS4220 CS4221

5. REGISTER DESCRIPTIONS - CS4221

Note: All registers are read/write in I2C mode and write-only in SPI mode, unless otherwise noted.
5.1 ADC Control (address 01h)
76543210
PDN HPDR HPDL ADMR ADML CAL CALP CLKE
00000000

5.1.1 POWER DOWN ADC (PDN)

Default = 0 0 - Disabled 1 - Enabled
Function:
The ADC will enter a low-power state when this function is enabled.

5.1.2 LEFT AND RIGHT CHANNEL HIGH PASS FILTER DEFEAT (HPDR-HPDL)

Default = 0 0 - Disabled 1 - Enabled
Function:
The internal high-pass filter is defeated when this function is enabled. Control of the internal high­pass filter is independent for the left and right channel.

5.1.3 LEFT AND RIGHT CHANNEL ADC MUTING (ADMR-ADML)

Default = 0 0 - Disabled 1 - Enabled
Function:
The output for the selected ADC channel will be muted when this function is enabled.

5.1.4 CALIBRATION CONTROL (CAL)

Default = 0 0 - Disabled 1 - Enabled
Function:
The device will automatically perform an offset calibration when brought out of reset, which last ap­proximately 50 ms. When this function is enabled, a rising edge on the reset line will initiate an offset calibration.

5.1.5 CALIBRATION STATUS (CALP) (READ ONLY)

Default = 0 0 - Calibration done 1 - Calibration in progress
DS284PP3 13
CS4220 CS4221

5.1.6 CLOCKING ERROR (CLKE) (READ ONLY)

Default = 0 0 - No error 1 - Error
5.2 DAC Control (address 02h)
76543210
Reserved
00000000
MUTC MUTR MUTL SOFT
Reserved

5.2.1 MUTE ON CONSECUTIVE ZEROS (MUTC)

Default = 0 0 - Disabled 1 - Enabled
Function:
The DAC output will mute following the reception of 512 consecutive audio samples of static 0 or -1 when this function is enabled. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The muting function is affected, similar to volume control changes, by the SOFT bit in the DAC Control register.
RMP1 RMP0

5.2.2 MUTE CONTROL (MUTR-MUTL)

Default = 0 0 - Disabled 1 - Enabled
Function:
The output for the selected DAC channel will be muted when this function is enabled. The muting function is affected, similar to volume control changes, by the SOFT bit in the DAC Control register.

5.2.3 SOFT RAMP CONTROL (SOFT)

Default = 0 0 - Soft Ramp level changes 1 - Zero Cross level changes
Function:
Soft Ramp level changes will be implemented by incrementally ramping, in 0.5 dB steps, from the cur­rent level to the new level. The rate of change defaults to 0.5 dB per 8 left/right clock periods and is adjustable through the RMP bits in the DAC Control register.
Zero Cross level changes will be implemented in a single step from the current level to the new level. The level change takes effect on a zero crossing to minimize audible artifacts. If the signal does not encounter a zero crossing, the level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate). Zero crossing is independently monitored and implemented for each channel. The ACCR and ACCL bits in the Converter Status Report register indicate when a level change has occurred for the right and left channel.
14 DS284PP3
CS4220 CS4221

5.2.4 SOFT RAMP STEP RATE (RMP)

Default = 00 00 - 1 step per 8 LRCK’s 01 - 1 step per 4 LRCK’s 10 - 1 step per 16 LRCK’s 11 - 1 step per 32 LRCK’s
Function:
The rate of change for the Soft Ramp function is adjustable through the RMP bits.
5.3 Left Channel Output Attenuator Level (address 03h)
5.4 Right Channel Output Attenuator Level (address 04h)
76543210
ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
00000000

5.4.1 ATTENUATION LEVEL (ATT7-ATT0)

Default = 00h
Function:
The Output Attenuator Level registers allow for attenuation of the DAC outputs in 0.5 dB increments from 0 to 113.5 dB. Level changes are implemented with an analog volume control until the residual output noise is equal to the noise floor in the mute state. At this point, volume changes are performed digitally. This technique is superior to purely digital volume control because the noise is attenuated by the same amount as the signal, thus preserving dynamic range, see Figure 16. Volume changes are performed as dictated by the SOFT bit in the DAC Control register. ATT0 represents 0.5 dB of attenuation and settings greater than 227 (decimal value) will mute the selected DAC output.
Binary Code Decimal Value Volume Setting
00000000 0 0 dB
11100011 227 -113.5 dB 11100100 228 Muted
Table 1. Example Volume Settings
DS284PP3 15
CS4220 CS4221
5.5 DSP Port Mode (address 05h)
76543210
Reserved
00000000

5.5.1 DE-EMPHASIS CONTROL (DEM)

Function:

5.5.2 SERIAL INPUT/OUTPUT DATA SCLK POLARITY SELECT (DSCK)

DEM1 DEM0 DSCK DOF1 DOF0 DIF1 DIF0
Default = 00 00 - 44.1 kHz de-emphasis setting 01 - 48 kHz de-emphasis setting 10 - 32 kHz de-emphasis setting 11 - De-emphasis disabled
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re­sponse at 32, 44.1 or 48 kHz sample rates, see Figure 15.
Default = 0 0 - Data valid on rising edge of SCLK 1 - Data valid on falling edge of SCLK
Function:
This function selects the polarity of the SCLK edge used to clock data in and out of the serial audio port.

5.5.3 SERIAL DATA OUTPUT FORMAT (DOF)

Default = 00
2
S compatible
00 - I 01 - Left justified 10 - Right justified, 24-bit 11 - Right justified, 20-bit
Function:
The required relationship between the left/right clock, serial clock and output serial data is defined by the Serial Data Output Format, and the options are detailed in Figures 8-11.
Note: If the format selected is Right-Justified, SCLK must be 64 Fs when operating in slave mode.

5.5.4 SERIAL DATA INPUT FORMAT (DIF)

Default = 00
2
S compatible
00 - I 01 - Left justified 10 - Right justified, 24-bit 11- Right justified, 20-bit
Function:
The required relationship between the left/right clock, serial clock and input serial data is defined by the Serial Data Input Format, and the options are detailed in Figures 8-11.
16 DS284PP3
CS4220 CS4221
5.6 Converter Status Report (Read Only) (address 06h)
76543210
ACCR ACCL LVR2 LVR1 LVR0 LVL2 LVL2 LVL0
00000000

5.6.1 LEFT AND RIGHT CHANNEL ACCEPTANCE BIT (ACCR-ACCL)

Default = 0 0 - Requested setting valid 1 - New setting loaded
Function:
The ACCR and ACCL bits indicate when a change in the Output Attenuator Level has occurred for the left and right channels, respectively. The value will be high when a new setting is loaded into the Output Attenuator Level registers. The value will return low when the requested attenuation setting has taken effect.

5.6.2 LEFT AND RIGHT CHANNEL ADC OUTPUT LEVEL (LVR AND LVL)

Default = 000 000 - Normal output levels 001 - -6 dB level 010 - -5 dB level 011 - -4 dB level 100 - -3 dB level 101 - -2 dB level 110 - -1 dB level 111 - Clipping
Function:
The analog-to-digital converter is continually monitoring the peak digital signal output for both the left and right channel, prior to the digital limiter. The maximum output value is stored in the LVL and LVR
bits. The LVL and LVR bits are ‘sticky’, so they are reset after each read is performed.
5.7 Master Clock Control (address 07h)
76543210
Reserved Reserved Reserved Reserved Reserved Reserved MCK1 MCK0
00000000

5.7.1 MASTER CLOCK CONTROL (MCK)

Default = 00 00 - XTI = 256 Fs for Master Mode 01 - XTI = 384 Fs for Master Mode 10 - XTI = 512 Fs for Master Mode
Function:
The MCK bits allow for control of the Master Clock, XTI, input frequency. Note: These bits are not valid when operating in slave mode.
DS284PP3 17

6. PIN DESCRIPTIONS — CS4220

XTO
XTO
LRCK
LRCK
SCLK
SCLK
DGND
DGND
SDIN
SDIN
DIF1
DIF1 DIF0
DIF0
CS4220
CS4220
1
1
NC
NC
2
2
XTI
XTI
3
3 4
4 5
5
VD
VD
6
6 7
7 821
821 9
9
10
10
11
11 12 17
12 17
13
VL
13
VL
14 15
14 15
28
28 27
27 26
26 25
25 24
24 23
23 22
22
20
20
19
19
18
18
16
16
NC
NC
RST
RST AOUTL-
AOUTL-
AOUTL+
AOUTL+
AOUTR+
AOUTR+ AOUTR-
AOUTR-
AGND
AGND
VASDOUT
VASDOUT AINL+
AINL+ AINL-
AINL­DEM1
DEM1 AINR+DEM0
AINR+DEM0 AINR-
AINR­NCNC
NCNC
CS4220 CS4221
NC 1,14,15, 28 No Connect - These pins are not connected internally and should be tied to DGND to mini-
mize noise coupling.
XTI, XTO 2,3 Crystal Connections (
Input/Output
) - Input and output connections for the crystal used to
clock the CS4220. Alternatively, a clock may be input into XTI. This is the clock source for the delta-sigma mod ulator and d igital filters. The frequency of this clo ck must be ei ther 256x, 38 4x, or 512x Fs in Slave Mode and 256x in Master Mode.
Fs (kHz) XTI (MHz)
256x 384x 512x
32 8.1920 12.2880 16.3840
44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760
Table 2. Common Clock Frequencies
Input
LRCK 4 Left/Right Clock (
serial audio data pi ns SDIN/SDOUT. The frequency of the Left/Right c lock must be equal to the input sample rate. Although the outputs for each ADC channel are transmitted at different times, Left/Right pai r s re pres en t sim ul taneously sample d ana lo g inputs. The required relation­ship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The options ar e detailed in Figures 8 - 11.
SCLK 5 Serial Data Clock (
out of the SDOUT pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 8 - 11.
VD 6 Digital Power (
Input
DGND 7 Digital Ground ( SDOUT 8 Serial Data Output (
The required relationship betwee n the le ft/ri ght cl oc k, serial clock and serial dat a is defi ne d by the DIF1-0 pins. The options are detailed in Figures 8 - 11.
SDIN 9 Serial Data Input (
required relationship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 8 - 11.
) - Determines which channel is currently being input/output of the
Input
) - Clocks the individual bits of the serial data into the SDIN pin and
) - Positive power supply for the digital section. Typically 5.0 VDC.
Input
) - Digital ground for t he dig it a l sec tion .
Output
) - Two’s complement MSB-first serial data is output on this pin.
Input
) - Two’s complement MSB-first serial data is input on this pin. The
18 DS284PP3
CS4220 CS4221
DIF0, DIF1 10,11 Digital Interface Format (
clock and serial data is defined by the Digital Interface Format. The options are detailed in Fig­ures 8 - 11.
DIF1 DIF0 DESCRIPTION FORMAT FIGURE
00 0 1 Left Justified, up to 24-bit data 1 9
1 0 Right Justified, 24-bit Data 2 10 1 1 Right Justified, 20-bit Data 3 11
2
I
S, up to 24-bit data
Input
) - The required relationship be tween the left/ right clock , serial
Table 3. Digital Interface Format - DIF1 and DIF0
Input
DEM0, DEM1 12,18 De-Emphasis Select (
filter. 32, 44.1, or 48 kHz sample rate selection defined in Table 4.
DEM0 DEM1 De-Emphasis
0 0 32 kHz 0 1 44.1 kHz 1 0 48 kHz 1 1 Disabled
) - Controls the activation of the standard 50/15 µs de-emphasis
Table 4. De-emphasis Control
VL 13 Digital Logic Power (
3.0 to 5.0 VDC.
AINR-, AINR+ 16,17 Differential Right Channel Analog Input (
tial) is specified in the Ana log Charac teristic s specifi cation t able and m ay be AC couple d or DC coupled into the device, see Figure 12 for optional line input buffer.
AINL-, AINL+ 19,20 Differential Left Channel Analog Input (
is specified in the Analog Characteristics specification table and may be AC coupled or DC coupled into the device, see Figure 12 for optional line input buffer.
VA 21 Analog Power ( AGND 22 Analog Ground ( AOUTR-,
AOUTR+ AOUTL-, AOUTL+ 25, 26 Differential Left Channel Analog Output (
RST 27 Reset (
23, 24 Differential Right Channel Analog Output (
ferential) is specified in the Analog Characteristics specification table.
ential) is specified in the Analog Characteristics specification table.
Input
) - When low, the device enters a low power mode and all internal registers are
reset, including the control port. When high, the control port becomes operational and normal operation will occur.
Input
) - Positive power supply for the digital interface section. Typically
Input
Input
) - Positive power supply for the analog section. Nominally +5 Volts.
Input
) - Analog ground reference.
08
Input
) - The full scale analog input level (differen-
) - The full scale analog input level (differentia l)
Output
) - The full scale analog output level (dif-
Output
) - The full scale analog output level (differ-
DS284PP3 19

7. PIN DESCRIPTIONS — CS4221

LRCK
SCLK
DGND
SCL/CCLK
SDA/CD IN
NC
XTO
XTI
VD
SDIN
VL
CS4221
1 2 3 4 5 6 7 821 9
10
11 12 17
13
14 15
28 27 26 25 24 23 22
20
19
18
16
NC
RST AOUTL-
AOU TL+
AOUTR+ AOUTR-
AGND
VASDOUT AINL+ AINL­I2C/SPI AINR+AD0/CS AINR­NCNC
CS4220 CS4221
NC 1,14,15, 28 No Connect - These pins are not connected internally and should be tied to DGND to mini-
mize noise coupling.
XTI, XTO 2,3 Crystal Connections (
Input/Output
) - Input and output connections for the crystal used to
clock the CS4221. Alte rnatively a clock ma y b e in put into XTI. This is the clo ck so urc e for the delta-sigma modulator and digita l filter s. The frequ ency of th is clock must be e ither 256x, 38 4x, or 512x Fs. The default XTI setting in Master Mode is 256x, but this may be changed to 384x or 512x through the Control Port.
Fs (kHz) XTI (MHz)
256x 384x 512x
32 8.1920 12.2880 16.3840
44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760
Table 5. Common Clock Frequencies
LRCK 4 Left/Right Clock (
serial audio data pi ns SDIN/SDOUT. The frequency of the Left/Right c lock must be equal to the input sample rate. Although the outputs for each ADC channel are transmitted at different times, Left/Right pai r s re pres en t sim ul taneously sample d ana lo g inputs. The required relation­ship between the left/right clock, serial clock and serial data is def ined by the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11.
SCLK 5 Serial Data Clock (
out of the SDOUT pin. The required relationship between the left/right clock, serial clock and serial data is def ined by the DSP Port Mod e (05h) re giste r. The options a re det ailed in Figu res 8 - 11.
VD 6 Digital Power ( DGND 7 Digital Ground ( SDOUT 8 Serial Data Output (
The required relationship betwee n the le ft/ri ght cl oc k, serial clock and serial dat a is defi ne d by the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11.
Input
) - Determines which channel is currently being input/output of the
Input
) - Clocks the individual bits of the serial data into the SDIN pin and
Input
) - Positive power supply for the digital section. Typically 5.0 VDC.
Input
) - Digital ground for the digital section.
Output
) - Two’s complement MSB-first serial data is output on this pin.
20 DS284PP3
CS4220 CS4221
SDIN 9 Serial Data Input (
required relationship between the left/right clock, serial clock and serial data is defined by the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11.
SCL/CCLK 10 Serial Control Port Clock (
SDA/CDIN 11
AD0/CS 12
VL 13 Logic Power (
AINR-, AINR+ 16,17 Differential Right Channel Analog Input (
I2C/SPI
AINL-, AINL+ 19,20 Differential Left Channel Analog Input (
VA 21 Analog Power ( AGND 22 Analog Ground ( AOUTR-,
AOUTR+ AOUTL-,
AOUTL+ RST 27 Reset (
18 Control Port Format (
23, 24 Differential Right Channel Analog Outputs (
25, 26 Differential Left Channel Analog Outputs (
2
In I
C mode, SCL requires an external pull-up resistor according to the I2C specification.
Serial Control Port Data (
external pull-up resistor according to the I serial control port in SPI mode.
Address Bit/Control Chip Select (
mode, CS interface is defined by the SPI
5.0 VDC.
tial) is specified in the Ana log Charac teristic s specifi cation t able and m ay be AC couple d or DC coupled into the device, see Figure 12 for optional line input buffer.
selected.
is specified in the Analog Characteristics specification table and may be AC coupled or DC coupled into the device, see Figure 12 for optional line input buffer.
ferential) is specified in the Analog Characteristics specification table.
ferential) is specified in the Analog Characteristics specification table.
is used to enable the c ontrol port interfac e on the CS422 1. The CS4 221 co ntrol po rt
Input
reset, including the control port. When high, the control port becomes operational and normal operation will occur.
Input
) - Two’s complement MSB-first serial data is input on this pin. The
Input
) - Clocks the serial control bits into and out of the CS4221.
Input/Output
/I2C pin.
Input
) - Positive power supply for the digital interface section. Typically 3.0 to
Input
) - When this pin is high, I2C mode is selected, when low, SPI is
)- SDA is a data I/O line in I2C mode and requires an
2
Input
) - In I2C mode, AD0 is a chip address bit. In SPI
Input
Input
) - Positive power supply for the analog section. Typically 5.0 VDC.
Input
) - Analog ground reference.
) - When low, the device enters a low power mode and all internal registers are
C specification. CDIN in the input data line for the
Input
) - The full scale analog input level (differen-
) - The full scale a nalog input l evel (dif ferenti al)
Output
) - The full scale ana log outp ut le ve l (dif-
Output
) - The full scale analog output level (dif-
DS284PP3 21
CS4220 CS4221

8. APPLICATIONS

8.1 Overview

The CS4220 is a stand-alone device controlled through dedicated pins. The CS4221 is controlled with an external microcontroller using the serial control port.

8.2 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS4220/1 requires careful attention to power sup­ply and grounding arrangements to optimize per­formance. Figures 4 and 5 shows the recommended power arrangement with VA, VD and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin.

8.3 High Pass Filter

The operational amplifiers in the input circuitry driving the CS4220/1 may generate a small DC off­set into the A/D converter. The CS4220/1 includes a high pass filter after the decima tor to remov e any DC offset which could result in recording a DC lev­el, possibly yielding "clicks" when switching be­tween devices in a multichannel system.

8.4 Analog Outputs

The recommended off-chip analog filter is e ither a 2nd order Butterworth or a 3rd order Butterworth, if greater out-of-band noise filtering is desired. The CS4220/1 DAC interpolation filter has been pre­compensated for an external 2nd order Butterworth filter with a 3 dB corner at Fs, or a 3rd order But­terworth filter with a 3 dB corner at 0.75 Fs to pro­vide a flat frequency response and linear phase over the passband (see Figure 14 for Fs = 48 kHz). If the recommended filter is not used, small frequency re­sponse magnitude and phase errors will occur. In addition to providing out-of-band noise attenua-
tion, the output filters shown in Figure 14 provide differential to single-ended conversion.

8.5 Master vs. Slave Mode

The CS4220/1 may be operated in either master mode or slave mode. In master mode, SCLK and LRCK are outputs which are internally derived from MCLK. The device will operate in master mode when a 47 k pulldown resistor is present on SDOUT at startup or after reset, see Figure 5. LRCK and SCLK are inputs to the CS4220/1 when operating in slave mode. See Figures 8-11 for the available clocking modes.

8.6 De-emphasis

The CS4220/1 includes digital de-emphasis for 32,
44.1, or 48 kHz sample rates. The frequency re­sponse of the de-emphasis curve, as shown in Fig­ure 15, will scale proportionally with changes in samples rate, Fs. The de-emphasis feature is in­cluded to accommodate older audio recordings that utilize pre-emphasis as a means of noise reduction.
De-emphasis control is achieved with the DEM1/0 pins on the CS4220 or through the DEM1-0 bits in the DSP Port Mode Byte (#5) on the CS4221.

8.7 Power-up / Reset / Power Down Calibration

Upon power up, the user should hold RST = 0 for approximately 10 ms. In this state, the control port is reset to its default settings and the part remains in the power down mode. At the end of RST, the de­vice performs an offset calibration which lasts ap­proximately 50 ms after which the device enters normal operation. In the CS4221, a calibration may also be initiated via the CAL bit in the ADC Con­trol Byte (#1). The CALP bit in the ADC Control Byte is a read only bit indicating the status of the calibration.
Reset/Power Down is achieved by lowering the RST pin causing the part to enter power down.
22 DS284PP3
CS4220 CS4221
Once RST goes high, the control port is functional and the desired settings should be loaded.
The CS4220/1 will also enter power down mode if the master clock source stops for approximately
10 µ s or if the LRCK is not synchronous to the master clock. The control port will re tain its current settings.
The CS4220/1 will mute the analog output s and en­ter the power down mode if the supply drops below approximately 4 volts.

8.8 Control Port Interface (CS4221 only)

The control port is used to load all the internal set­tings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference prob­lems, the control port pins should remain static if no operation is required.
The control port has 2 modes: SPI and I2C, with the CS4221 operating as a slave device. The con­trol port interface format is selected by the SPI/I2C pin.

8.8.1 SPI Mode

In SPI mode, CS is the CS4221 chip select signal, CCLK is the control port bit cl ock, C DIN i s the in­put data line from the microcontroller and the chip address is 0010000. All signals are inputs and data is clocked in on the rising edge of CCLK.
The CS4221 has a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, then the MAP will stay constant for successive writes. If INCR is set to a 1, then MAP will auto increment after each byte is written, al­lowing block writes of successive registers. Regis­ter reading from the CS4221 is not supported in the SPI mode.

8.8.2 I2C Mode

In I2C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 7. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VD or DGND as desired. The upper 6 bits of the 7 bit ad­dress field must be 001000. In order to communi­cate with the CS4221, the LSB of the chip address field (first byte sent to the CS4221) should match the setting of the AD0 pin. The eighth bit of the ad­dress byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer which selects the reg­ister to be read or written. If the operation is a read, the contents of the register pointed to by the Mem­ory Address Pointer will be output. Setting the auto increment bit in MAP, allows successive reads or writes of consecutive registers. Each byte is sepa­rated by an acknowledge bit.
Figure 6 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write in­dicator (R/W), which must be low to write. Regis­ter reading from the CS4221 is not supported in the SPI mode. The next 8 bits form the Memory Ad­dress Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into a register desig­nated by the MAP.
DS284PP3 23
CS4220 CS4221
8.9 Memory Address Pointer (MAP)
76543210
INCR
00000000
Reserved Reserved Reserved Reserved
8.9.1 AUTO-INCREMENT CONTROL (INCR)
Default = 0 0 - Disabled 1 - Enabled
8.9.2 REGISTER POINTER (MAP)
Default = 000
CS
CCLK
CHIP
CDIN
ADDRESS
0010000 R/W
MAP DATA
MAP2 MAP1 MAP0
MSB LSB
byte 1 byte n
MAP = Memory Address Pointer
Figure 6. Control Port Timing, SPI mode
SDA
SCL
001000
Start Stop
ADDR AD0
R/W
ACK DATA 1-8 ACK DATA 1-8 ACK
Figure 7. Control Port Timing, I2C mode
24 DS284PP3
CS4220 CS4221
LRCK
SCLK
SDATA +3 +2 +1
MSB
-1 -2 -3 -4 -5
Left Channel
+5 +4
LSB
Master Slave
I2S, up to 24-bit data XTI = 256, 384, 512 Fs (CS4223 - 256 Fs only) LRCK = 4 to 50 kHz SCLK = 64 Fs
Figure 8. Serial Audio Format 0 (I2S)
LRCK
SCLK
SDATA +3 +2 +1
MSB
-1 -2 -3 -4 -5
Left Channel
+5 +4
LSB
Right Channel
+3 +2 +1
MSB
-1 -2 -3 -4
2
S, up to 24-bit data
I
+5 +4
LSB
XTI = 256, 384, 512 Fs LRCK = 4 to 50 kHz SCLK = 48,64, 128 Fs
Right Channel
+3 +2 +1
MSB
-1 -2 -3 -4
+5 +4
LSB
Master Slave
Left-justified, up to 24-bit data XTI = 256, 384, 512 Fs (CS4223 - 256 Fs only) LRCK = 4 to 50 kHz SCLK = 64 Fs
Figure 9. Serial Audio Format 1
LRCK
SCLK
SDATA
0
Left Channel
23 22 21 20 19 18
32 clocks
65432107
Master Slave
Right-justified, 24-bit data XTI = 256, 384, 512 Fs (CS4223 - 256 Fs only) LRCK = 4 to 50 kHz SCLK = 64 Fs
Figure 10. Serial Audio Format 2
Left-justified, up to 24-bit data XTI = 256, 384, 512 Fs LRCK = 4 to 50 kHz SCLK = 48, 64, 128 Fs
Right Channel
23 22 21 20 19 18
65432107
Right-justified, 24-bit data XTI = 256, 384, 512 Fs LRCK = 4 to 50 kHz SCLK = 64 Fs
DS284PP3 25
CS4220 CS4221
LRCK
SCLK
SDATA
10
17 16 17 16
19 18 19 18
Left Channe l
15 14 13 12 11 10
32 clocks
6543210987
Master Slave
Right-justified, 20-bit data XTI = 256, 384, 512 Fs (CS4223 - 256 Fs only) LRCK = 4 to 50 kHz SCLK = 64 Fs
Figure 11. Serial Audio Format 3
Right Channel
15 14 13 12 11 10
6543210987
Right-justified, 20-bit data XTI = 256, 384, 512 Fs LRCK = 4 to 50 kHz SCLK = 64 Fs
Figure 12. Optional Input Buffer
150
10 µF
+
AINR+
2.2 nF
Input
CS4223/4
AINR-
4.7 µF
+
0.1 µF
Figure 13. Single-ended Input Application
26 DS284PP3
CS4220 CS4221
Figure 15. De-emphasis Curve
Figure 14. 2- and 3-Pole Butterworth Filters
Gain dB
Analog Digital
0
Signal
Noise
Amplitude (dB)
0 -113.5
Attenuation (d B)
0 dB
-10 dB
T1 = 50 µs
F1 F2
T2 = 15 µs
Frequency
Figure 16. Hybrid Analog/Digital Attenuation
DS284PP3 27

9. ADC/DAC FILTER RESPONSE

Figure 17. ADC Filter Response Figure 18. ADC Passband Ripple

CS4220 CS4221

Figure 19. ADC Transition Band Figure 20. DAC Filter Response

Figure 21. DAC Passband Ripple Figure 22. DAC Transition Band

28 DS284PP3

10.PARAMETER DEFINITIONS

Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering So­ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1 dBFS as suggested in AES17-1991 Annex A and DACs are measured at 0 dBFS.
Idle Channel Noise / Signal-to-Noise-Ratio
The ratio of the rms analog output level with 1 kHz full scale digital input to the rms analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in deci­bels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and re­ferred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio.
CS4220 CS4221
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. Units in decibels.
Interchannel Isolation
A measure of crosstalk between channels. Measured for each channel at the converter’s output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Frequency Response
A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in deci­bels.
Gain Error
The deviation from the nominal full scale output for a full scale input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
For the ADCs, the deviation in LSB's of the output from mid-scale with the selected inputs tied to a com­mon potential. For the DAC's, the differential output voltage with mid-scale input code. Units are in volts.
DS284PP3 29

11.PACKAGE DIMENSIONS

28L SSOP PACKAGE DRAWING
N
CS4220 CS4221
D
E
A2
A
E1
1
2
b
SIDE VIEW
1
23
e
TOP VIEW
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM M AX
A -- -- 0.084 -- -- 2.13 A1 0.002 0.006 0.010 0.05 0.15 0.25 A2 0.064 0.069 0.074 1.62 1.75 1.88
b 0.009 -- 0.015 0.22 -- 0.38 2,3
D 0.390 0.4015 0.413 9.90 10.20 10.50 1
E 0.291 0.307 0.323 7.40 7.80 8.20 E1 0.197 0.209 0.220 5.00 5.30 5.60 1
e 0.022 0.026 0.030 0.55 0.65 0.75
L 0.025 0.0354 0.041 0.63 0.90 1.03
A1
SEATING
PLANE
L
END VIEW
JEDEC #: MO-150
Controlling Dimension is Millimeters
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
30 DS284PP3
• Notes •
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