Cirrus Logic CS4202 User Manual

Audio Codec ’97 with Headphone Amplifier

CS4202

Features

! AC ’97 2.2 Compliant
! Exceeds the Microsoft

Performance Requirements

! Integrated High-Performance Headphone

Amplifier

! On-chip PLL for use with External Clock

Sources

! Integrated High-Performance Microphone

Pre-Amplifier

! Automatic Jack Sense through GPIO
! BIOS-Driver Interface for Audio Feature

Configuration through Software

! S/PDIF Digital Audio Output

2

! I

S Serial Digital Outputs Enable Cost

Effective Six Channel Applications

! Independent Simultaneous S/PDIF and Six

Channel Audio Playback

®

PC 2001 Audio

! Sample Rate Converters
! Three Analog Line-level Stereo Inputs
! High Quality Pseudo-Differential CD Input
! Two Analog Line-level Mono Inputs
! Dual Microphone Inputs
! Stereo and Mono Line-level Outputs
! Extensive Power Management Support

Description

The CS4202 is an AC ’97 2.2 compliant stereo audio co­dec designed for PC multimedia systems. It uses
industry leading delta-sigma and mixed signal technolo­gy. This advanced technology and these features are
designed to help enable the design of PC 99 and
PC 2001 compliant high-quality audio systems for desk­top, portable, and entertainment PCs.

Coupling the CS4202 with a PCI audio accelerator or
core logic supporting the AC ’97 interface implements a
cost effective, superior quality audio solution. The
CS4202 surpasses PC 99, PC 2001, and AC ’97 2.2 au­dio quality standards.

! 20-bit Stereo Digital-to-Analog Converters
! 18-bit Stereo Analog-to-Digital Converters

AC-LINK AND AC '97

REGISTERS

PWR

TEST

MGT

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

ID0#
ID1#

EAPD

SPDIF_OUT

GPIO[4:0]

SDOUT,LRCLK,SCLK

AC-

LINK

AC '97

REGISTERS

GPIO, S/PDIF

SERIAL DATA PORT

Preliminary Product Information

http://www.cirrus.com

SRC

GAIN / MUTE CONTROLS

MIXER / MUX SELECTS

SRC

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright © Cirrus Logic, Inc. 2005

(All Rights Reserved)

ORDERING INFO

CS4202-JQZ, Lead Free 48-pin TQFP 9x9x1.4 mm

ANALOG INPUT MUX
AND OUTPUT MIXER

LINE

PCM_DATA

PCM_DATA

18 bit

ADC

20 bit
DAC

INPUT

MUX

INPUT
MIXER

Σ

OUTPUT

MIXER

Σ

CD
AUX
VIDEO

MIC1
MIC2

PHONE
PC_BEEP

LINE_OUT
HP_OUT
MONO_OUT

JULY '05

DS549PP2

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 7

ANALOG CHARACTERISTICS................................................................................................7

ABSOLUTE MAXIMUM RATINGS ...........................................................................................8

RECOMMENDED OPERATING CONDITIONS .......................................................................8

AC ’97 SERIAL PORT TIMING............................................................................................... 10

2. GENERAL DESCRIPTION .....................................................................................................13

2.1 AC-Link ............................... ... .... ...................................... .... ... ... ... ... .... ............................13

2.2 Control Registers .......................... ... ....................................... ... ... ... .... ... ... ......................14

2.3 Sample Rate Converters ........................ .... ... ... ... .... ... ... ....................................... ... ... ... ... 14

2.4 Mixers ........................................................ ... ....................................... ... ... ... ...................14

2.5 Input Mux ................................... ... ... ....................................... ... ... ... .... ... ... ......................14

2.6 Volume Control ............................. ... ... ....................................... ... ... .... ... ... ... ...................14

3. AC-LINK FRAME DEFINITION ..............................................................................................16

3.1 AC-Link Serial Data Output Frame .................................................................................. 17

3.1.1 Serial Data Output Slot Tags (Slot 0)............................................................................. 17

3.1.2 Command Address Port (Slot 1)....................................................................................17

3.1.3 Command Data Port (Slot 2).......................................................................................... 18

3.1.4 PCM Playback Data (Slots 3-4,6-11)............................................................................. 18

3.1.5 GPIO Pin Control (Slot12)........................... ... ... .... ... ... ....................................... ... ... ... ... 18

3.2 AC-Link Serial Data Input Frame ..................... ............................................................. ... 19

3.2.1 Serial Data Input Slot Tag Bits (Slot 0) ........................................................................ 19

3.2.2 Status Address Port (Slot 1) ..........................................................................................19

3.2.3 Status Data Port (Slot 2)................................................................................................20

3.2.4 PCM Capture Data (Slot 3-4,6-8,11)..............................................................................20

3.2.5 GPIO Pin Status (Slot 12) .......... ... ... ... .... ... ... ... .... ... ....................................... ... ... ... ... ... 20

3.3 AC-Link Protocol Violation - Loss of SYNC ............................................................ ... ... ... 21

4. REGISTER INTERFACE ..................................................................................................... 22

4.1 Reset Register (Index 00h) ........... ... ... ... .... ... ... ... .... ... ... .......................................... ... ......23

4.2 Analog Mixer Output Volume Registers (Index 02h - 04h) ..............................................23

4.3 Mono Volume Register (Index 06h)............................... ... .... ......................................... ... 24

CS4202

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its

subsidiaries ("Cirr us") belie ve that the i nformation contained i n this document i s accurate a nd reliabl e. However, the information is subject to change without
notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to
verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowle dgme nt, inclu ding those p ertain ing to w arranty, ind emni ficatio n, and lim itatio n of liab ility. No responsibility is assumed by Cirrus for
the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of
third parties. Thi s document is the prop erty of Cirrus and by furnish ing thi s inform ation, Cir rus gran ts no lic ense, expr ess or implied under any patents, mask
work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained here­in and gives consent for copies to be m ad e of th e information only for use within your orga ni zatio n with respect to Cirrus integrated circuits or other pr oducts of
Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for
resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED
FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SE­CURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS
IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IM­PLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS
PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CU ST OMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRU S P ROD­UCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES,
DISTRIBUTORS AND OTHER AGENTS FR OM ANY AND ALL LI ABILI TY, INCL UDING AT TORNEYS ’ FEES AND COSTS, THA T MAY RE SULT F ROM OR
ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade­marks or service marks of their respective owners.

2 DS549PP2

CS4202

4.4 PC_BEEP Volume Register (Index 0Ah).......................................................................... 24

4.5 Phone Volume Register (Index 0Ch)....................... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ............ 24

4.6 Microphone Volume Register (Index 0Eh)........................................................................ 25

4.7 Analog Mixer Input Gain Registers (Index 10h - 18h) ...................................................... 26

4.8 Input Mux Select Register (Index 1Ah)............................................................................. 27

4.9 Record Gain Register (Index 1Ch) ...... ... .......................................................................... 28

4.10 General Purpose Register (Index 20h) ......... ... .... ... ... ... ....................................... ... ... ... 29

4.11 Powerdown Control/Status Register (Index 26h) ........................................................... 30

4.12 Extended Audio ID Register (Index 28h)........................................................................ 31

4.13 Extended Audio Status/Control Register (Index 2Ah) .................................................... 32

4.14 Audio Sample Rate Control Registers (Index 2Ch - 32h)......... ... ................................... 33

4.15 S/PDIF Control Register (Index 3Ah) ............................................................................. 34

4.16 Extended Modem ID Register (Index 3Ch) .................................................................... 35

4.17 Extended Modem Status/Control Register (Index 3Eh) ................................................. 35

4.18 GPIO Pin Configuration Register (Index 4Ch)................................................................ 35

4.19 GPIO Pin Polarity/Type Configuration Register (Index 4Eh).......................................... 36

4.20 GPIO Pin Sticky Register (Index 50h) ............................................................................ 36

4.21 GPIO Pin Wakeup Mask Register (Index 52h)............................................................... 37

4.22 GPIO Pin Status Register (Index 54h)............................................................................ 37

4.23 AC Mode Control Register (Index 5Eh).......................................................................... 37

4.24 Misc. Crystal Control Register (Index 60h)..................................................................... 39

4.25 Serial Port Control Register (Index 6Ah) ........................................................................ 40

4.26 BIOS-Driver Interface Control Registers (Index 70h - 72h) ............................................ 41

4.27 BIOS-Driver Interface Status Register (Index 7Ah)........................................................ 41

4.28 Vendor ID1 Register (Index 7Ch) ................................................................................... 42

4.29 Vendor ID2 Register (Index 7Eh) ................................................................................... 42

5. SERIAL DATA PORTS ........................................................................................................... 43

5.1 Overview ............. ....................................... ... ... ... .... ... ... ....................................... ... ......... 43

5.2 Multi-Channel Expansion ........... ... ... ... ... .... ... ... ... .... ... ... ... .......................................... ... ... 43

5.3 Serial Data Formats ............... .... ...................................... .... ... ... ... ... .... ... ... ...................... 44

6. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 45

7. EXCLUSIVE FUNCTIONS ...................................................................................................... 45

8. POWER MANAGEMENT ....................................................................................................... 46

8.1 AC ’97 Reset Modes ........................................................................................................ 46

8.1.1 Cold Reset .................... ...................................... .... ... ... ... ................................... 46

8.1.2 Warm Reset ........ ... ... .... ... ... ....................................... ... ... ... .... ... ... ...................... 46

8.1.3 New Warm Reset ................................ ... .... ... ... ... .... ... ... ...................................... 46

8.1.4 Register Reset .................... ... ... .... ...................................................................... 46

8.2 Powerdown Controls .................................... ... ... .... ... ... ... .... ... ... ... ................................... 47

9. CLOCKING ............................................................................................................................. 49

9.1 PLL Operation (External Clock) ....................................................................................... 49

9.2 24.576 MHz Crystal Operation ........................................................................................ 49

9.3 Secondary Codec Operation ........................................................................................... 49

10. ANALOG HARDWARE DESCRIPTION ............................................................................... 51

10.1 Analog Inputs ................................................................................................................. 51

10.1.1 Line Inputs ........................................................................................................ 51

10.1.2 CD Input ............................................................................................................ 51

10.1.3 Microphone Inputs ............................................................................................ 51

10.1.4 PC Beep Input ................................................................................................... 52

10.1.5 Phone Input ....................................................................................................... 52

10.2 Analog Outputs .............................................................................................................. 52

10.2.1 Stereo Outputs .................................................................................................. 52

10.2.2 Mono Output ..................................................................................................... 53

10.3 Miscellaneous Analog Signals ....................................................................................... 53

DS549PP2 3

10.4 Power Supplies ..............................................................................................................53

10.5 Reference Design ..........................................................................................................53

11. GROUNDING AND LAYOUT .............................................................................................. 54

12. PIN DESCRIPTIONS ........................................................................................................ 56

13. PARAMETER AND TERM DEFINITIONS ............................................................................ 62

14. REFERENCE DESIGN ................................................................................................... 64

15. REFERENCES ................................ ... ... ... ....................................... ... ... .... ... ... ... .... ... ... ......... 65

16. PACKAGE DIMENSIONS ..................................................................................................... 66

LIST OF FIGURES

Figure 1. Power Up Timing............................................................................................................11

Figure 2. Codec Ready from Start-up or Fault Condition..............................................................11

Figure 3. Clocks ............................................................................................................................11

Figure 4. Data Setup and Hold......................................................................................................12

Figure 5. PR4 Powerdown and Warm Reset ................................................................................12

Figure 6. Test Mode......................................................................................................................12

Figure 7. AC-link Connections.......................................................................................................13

Figure 8. CS4202 Mixer Diagram..................................................................................................15

Figure 9. AC-link Input and Output Framing.................................................................................. 16

Figure 10. Serial Data Port: Six Channel Circuit ...........................................................................43

Figure 11. Serial Data Format 0 (I2S)...........................................................................................44

Figure 12. Serial Data Format 1 (Left Justified) ............................................................................44

Figure 13. Serial Data Format 2 (Right Justified, 20-bit data).......................................................44

Figure 14. Serial Data Format 3 (Right Justified, 16-bit data).......................................................44

Figure 15. S/PDIF Output..............................................................................................................45

Figure 16. PLL External Loop Filter............................................................................................... 49

Figure 17. External Crystal............................................................................................................50

Figure 18. Line Input (Replicate for Video and AUX) ....................................................................51

Figure 19. Differential 1 VRMS CD Input ......................................................................................51

Figure 20. Microphone Input .........................................................................................................52

Figure 21. PC_BEEP Input............................................................................................................ 52

Figure 22. Modem Connection......................................................................................................52

Figure 23. Line Out and Headphone Out Setup............................................................................53

Figure 24. Line Out/Headphone Out Setup................................................................................... 53

Figure 25. +5V Analog Voltage Regulator.....................................................................................54

Figure 26. Conceptual Layout for the CS4202 when in XTAL or OSC Clocking Modes...............55

Figure 27. Pin Locations for the CS4202 ......................................................................................56

Figure 28. CS4202 Reference Design ..........................................................................................64

CS4202

4 DS549PP2

LIST OF TABLES

Table 1. Register Overview for the CS4202.....................................................................22

Table 2. Analog Mixer Output Attenuation........................................................................23

Table 3. Microphone Input Gain Values ...........................................................................25

Table 4. Analog Mixer Input Gain Values.........................................................................26

Table 5. Analog Mixer Input Gain Register Index.............................................................26

Table 6. Input Mux Selection.................................. ... .... ... ... ... .... ... ... ................................27

Table 7. Record Gain Values ...........................................................................................28

Table 8. Slot Mapping for the CS4202 .............................................................................31

Table 9. Slot Assignment Defaults ...................................................................................31

Table 10. Directly Supported SRC Sample Rates for the CS4202...................................33

Table 11. GPIO Input/Output Configurations....................................................................36

Table 12. Serial Data Format Selection............................................................................40

Table 13. Device ID with Corresponding Part Number.....................................................42

Table 14. Serial Data Formats and Compatible DACs for the CS4202............ ... .... ... ... ...44

Table 15. Powerdown PR Bit Functions........................................ ... ... .............................47

Table 16. Powerdown PR Function Matrix for the CS4202..............................................48

Table 17. Power Consumption by Powerdown Mode for the CS4202 .............................48

Table 18. Clocking Configurations for the CS4202 ..........................................................50

CS4202

DS549PP2 5

1. CHARACTERISTICS AND SPECIFICATIONS

CS4202

ANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted: T

AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; Z
1000 pF load for Mono and Line Outputs; C

= 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz,

DL

ambient

=100 kΩ/

AL

= 25° C,

18-bit linear coding for ADC functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain.

Parameter

(Note 2)

Symbol Path

(Note 3)

CS4202-JQZ

Min Typ Max

Unit

Full Scale Input Voltage
Line Inputs
Mic Inputs (10dB = 0, 20dB = 0)
Mic Inputs (10dB = 1, 20dB = 0)
Mic Inputs (10dB = 0, 20dB = 1)
Mic Inputs (10dB = 1, 20dB = 1)

A-D
A-D
A-D
A-D
A-D

0.91

0.91

0.283

0.091

0.0283

1.00

1.00

0.315

0.10

0.0315

-

-

-

-

-

V
V
V
V
V

RMS
RMS
RMS
RMS
RMS

Full Scale Output Voltage
Line and Mono Outputs
Headphone Output

Frequency Response (Note 4)
Analog Ac = ± 0.25 dB
DAC Ac = ± 0.25 dB
ADC Ac = ± 0.25 dB

Dynamic Range
Stereo Analog Input s to LINE_OUT
Mono Analog Input to LINE_OUT
DAC Dynamic Range
ADC Dynamic Range

DAC SNR
(-20 dB FS input w/ CCIR-RMS filter on output)

Total Harmonic Distortion + Noise

FR

DR

SNR

THD+N

D-A
D-A

A-A
D-A
A-D

A-A
A-A
D-A
A-D

0.91

-

20
20
20

90
85
85
85

1.0

1.4

-

-

-

95
90
90
90

1.13

-

20,000
20,000
20,000

-

-

-

-

V

RMS

V

RMS

Hz
Hz
Hz

dB FS A
dB FS A
dB FS A
dB FS A

D-A - 70 - dB

(-3 dB FS input signal):
Line Output
Headphone Output
DAC
ADC (all inputs)

A-A
A-A
D-A
A-D

-

-

-

-

-90

-75

-87

-84

-80

-70

-80

-80

dB FS
dB FS
dB FS
dB FS

Power Supply Rejection Ratio
(1 kHz, 0.5 V

w/ 5V DC offs e t ) (Note 4) 40 60 - dB

RMS

Interchannel Isolation 70 87 - dB
Spurious Tone (Note 4) - -100 - dB FS
Input Impedance (Note 4) 10 - - kΩ

Notes: 1. Z

refers to the analog output pin loading and CDL refers to the digital output pin loading.

AL

2. Parameter definitions are given in Section 13, Parameter and Term Definitions.

3. Path refers to the signal path used to generate this data. These paths are defined in Section 13,
Parameter and Term Definitions.

4. This specification is guaranteed by silicon characterization; it is not production tested.

6 DS549PP2

ANALOG CHARACTERISTICS (Continued)

CS4202

Parameter

(Note 2)

External Load Impedance
Line Output, Mono Output
Headphone Output

Output Impedance
Line Output, Mono Output
Headphone Output (Note 4)

Input Capacitance (Note 4) - 5 - pF
Vrefout 2.3 2.4 2.5 V

Symbol Path

(Note 3)

CS4202-JQZ

Min Typ Max

10
32

-

-

-

-

730

0.8

-

-

-

-

Unit

kΩ

MIXER CHARACTERISTICS

Parameter Min Typ Max Unit

Mixer Gain Range Span
PC Beep
Line In, Aux, CD, Video, Mic1, Mic2, Phone
Mono Out, Line Out, Headphone Out
ADC Gain

Step Size
All volume controls except PC Beep
PC Beep

-

-

-

-

-

-

45.0

46.5

46.5

22.5

1.5

3.0

-

-

-

-

-

-

dB
dB
dB
dB

dB
dB

Ω

Ω
Ω

ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog
Total Power Dissipation (Supplies, Inputs, Outputs) - - 1.25 W
Input Current per Pin (Except Supply Pins) -10 - 10 mA
Output Current per Pin (Except Supply Pins) -15 - 15 mA
Analog Input voltage -0.3 - AVdd+

Digital Input voltage -0.3 - DVdd +

Ambient Temperature (Power Applied) 0 - 70 °C
Storage Temperature -65 - 150 °C

-0.3

-0.3

-0.3

-

-

-

5.5

5.5

5.5

0.3

0.3

RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Symbol Min Typ Max Unit

Power Supplies +3.3 V Digital

+5 V Digital

Analog

Operating Ambient Temperature 0 - 70 °C

DVdd1, DVdd2
DVdd1, DVdd2

AVdd1, AVdd2

3.135

4.75

4.75

3.3
5
5

3.465

5.25

5.25

V
V
V

V

V

V
V
V

DS549PP2 7

CS4202

DIGITAL CHARACTERISTICS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

Parameter Symbol Min Typ Max Unit

DVdd = 3.3V

Low level input voltage V
High level input voltage V
High level output voltage V
Low level output voltage V

il

ih

oh

ol

Input Leakage Current (AC-link inputs) -10 - 10 µA
Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA
Output buffer drive current

BIT_CLK, SDATA_IN
SPDIF_OUT
EAPD/SCLK, GPIO0/LRCLK, GPIO1/SDOUT,
GPIO2, GPIO3, GPIO4/SDO2 (Note 4)

DVdd = 5.0 V

Low level input voltage V
High level input voltage V
High level output voltage V
Low level output voltage V

il

ih

oh

ol

Input Leakage Current (AC-link inputs) -10 - 10 µA
Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA
Output buffer drive current

BIT_CLK, SDATA_IN
SPDIF_OUT
EAPD/SCLK, GPIO0/LRCLK, GPIO1/SDOUT,
GPIO2, GPIO3, GPIO4/SDO2 (Note 4)

- - 0.80 V

2.15 - - V

3.00 3.25 - V

-0.030.35V

-

-

-

72
24

4

-

-

-

mA
mA

mA

- - 0.80 V

3.25 - - V

4.50 4.95 - V

- 0.03 0.35 V

-

-

-

72
24

4

-

-

-

mA
mA

mA

8 DS549PP2

CS4202

AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: T

AVdd = 5.0 V, DVdd = 3.3 V; C

= 55 pF load.

L

ambient

= 25° C,

Parameter Symbol Min Typ Max Unit

RESET Timing

RESET# active low pulse width T
RESET# inactive to BIT_CLK start-up delay (XTL mode)

(OSC mode)

(PLL mode)
1st SYNC active to CODEC READY ‘set’ T
Vdd stable to RESET# inactive T

rst_low

T

rst2clk

sync2crd

vdd2rst#

1.0 - - µs

-

-

-

4.0

4.0

2.5

-

-

-

-62.5-µs

100 - - µs

Clocks

BIT_CLK frequency F
BIT_CLK period T

clk_period

clk

- 12.288 - MHz

- 81.4 - ns
BIT_CLK output jitter (depends on XTL_IN source) - - 750 ps
BIT_CLK high pulse width T
BIT_CLK low pulse width T
SYNC frequency F
SYNC period T
SYNC high pulse width T
SYNC low pulse width T

sync_period

sync_high

sync_low

clk_high

clk_low

sync

36 40.7 45 ns
36 40.7 45 ns

- 48 - kHz

-20.8-µs

-1.3-µs

-19.5-µs

Data Setup and Hold

Output propagation delay from rising edge of BIT_CLK T
Input setup time from falling edge of BIT_CLK T
Input hold time from falling edge of BIT_CLK T
Input signal rise time T
Input signal fall time T
Output signal rise time (Note 4) T
Output signal fall time (Note 4) T

co

isetup

ihold

irise

ifall

orise

ofall

81012ns

10 - - ns

0--ns
2-6ns
2-6ns
246ns
246ns

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) T
SYNC pulse width (PR4) Warm Reset T
SYNC inactive (PR4) to BIT_CLK start-up delay T
Setup to trailing edge of RESET# (ATE test mode) (Note 4) T

s2_pdown

sync_pr4
sync2clk

setup2rst

Rising edge of RESET# to Hi-Z delay (Note 4) T

off

- 0.285 1.0 µs

1.0 - - µs

162.8 285 - ns
15 - - ns

- - 25 ns

µs
µs

ms

DS549PP2 9

BIT_CLK

RESET#

Vdd

BIT_CLK

T

rst_low

T

vdd2rst#

Figure 1. Power Up Timing

T

rst2clk

CS4202

SYNC

CODEC_READY

Figure 2. Codec Ready from Start-up or Fault Condition

BIT_CLK

T

orise

SYNC

T

irise

T

clk_highTclk_low

T

sync_high

T

T

sync2crd

T

ifall

sync_period

T

clk_period

T

sync_low

T

ifall

Figure 3. Clocks

10 DS549PP2

BIT_CLK

BIT_CLK

SDATA_IN

SDATA_OUT,
SYNC

Slot 1 Slot 2

T

co

T

isetup

Figure 4. Data Setup and Hold

T

CS4202

ihold

SDATA_OUT

SDATA_IN

SYNC

Write to 0x20 Data PR4 Don't Care

T

s2_pdown

Figure 5. PR4 Powerdown and Warm Reset

RESET#

T

setup2rst

SDATA_OUT,
SYNC

T

off

T

sync_pr4

T

sync2clk

SDATA_IN,
BIT_CLK

Hi-Z

Figure 6. Test Mode

DS549PP2 11

CS4202

2. GENERAL DESCRIPTION

The CS4202 is a mixed-signal serial audio codec
with integrated headphone power amplifier com­pliant with the Intel® Audio Codec ’97 Specifica-
tion, revision 2.2 [6] (referred to as AC ’97). It is
designed to be paired with a digital controller, typ­ically located on the PCI bus or integrated within
the system core logic chip set. The controller is re­sponsible for all communications between the
CS4202 and the remainder of the system. The
CS4202 contains two distinct functional sections:
digital and analog. The digital section includes the
AC-link interface, S/PDIF interface, serial data
port, GPIO, power management support, and Sam­ple Rate Converters (SRCs). The analog section in­cludes the analog input multiplexer (mux), stereo
input mixer, stereo output mixer, mono output mix­er, headphone amplifier, stereo Analog-to-Digital
Converters (ADCs), stereo Digital-to-Analog Con­verters (DACs), and their associated volume con­trols.

2.1 AC-Link

All communication with the CS4202 is established
with a 5-wire digital interface to the controller
called the AC-link. This interface is shown in
Figure 7. All clocking for the serial communication
is synchronous to the BIT_CLK signal. BIT_CLK
is generated by the primary audio codec and is used
to clock the controller and any secondary audio co­decs. Both input and output AC-link audio frames
are organized as a sequence of 256 serial bits form­ing 13 groups referred to as ‘slots’. During each au­dio frame, data is passed bi-directionally between
the CS4202 and the controller. The input frame is
driven from the CS4202 on the SDATA_IN line.
The output frame is driven from the controller on
the SDATA_OUT line. The controller is also re­sponsible for issuing reset commands via the RE­SET# signal. Following a Cold Reset, the CS4202
is responsible for notifying the controller that it is
ready for operation after synchronizing its internal
functions. The CS4202 AC-link signals must use
the same digital supply voltage as the controller, ei­ther +5 V or +3.3 V. See Section 3, AC-Link Frame
Definition, for detailed AC-link information.

Digital AC'97

Controller

Figure 7. AC-link Connections

12 DS549PP2

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

AC'97

CODEC

CS4202

2.2 Control Registers

The CS4202 contains a set of AC ’97 compliant
control registers, and a set of Cirrus Logic defined
control registers. These registers control the basic
functions and features of the CS4202. Read access­es of the control registers by the AC ’97 controller
are accomplished with the requested register index
in Slot 1 of a SDATA_OUT frame. The following
SDATA_IN frame will contain the read data in Slot

2. Write operations are similar, with the register in­dex in Slot 1 and the write data in Slot 2 of a
SDATA_OUT frame. The function of each input
and output frame is detailed in Section 3, AC-Link
Frame Definition. Individual register descriptions
are found in Section 4, Register Interface.

2.3 Sample Rate Converters

The sample rate converters (SRC) provide high ac­curacy digital filters supporting sample frequencies
other than 48 kHz to be captured from the CS4202
or played from the controller. AC ’97 requires sup­port for two audio rates (44.1 and 48 kHz). In addi­tion, the Intel® I/O Controller Hub (ICHx)
specification [9] requires support for five more au­dio rates (8, 11.025, 16, 22.05, and 32 kHz). The
CS4202 supports all these rates, as shown in
Table 10 on page 32.

2.4 Mixers

The CS4202 input and output mixers are illustrated
in Figure 8. The stereo input mixer sums together

the analog inputs to the CS4202 according to the
settings in the volume control registers. The stereo
output mixer sums the output of the stereo input
mixer with the PC_BEEP and PHONE signals. The
stereo output mix is then sent to the LINE_OUT
and HP_OUT pins of the CS4202. The mono out­put mixer generates a monophonic sum of the left
and right audio channels from the stereo input mix­er. The mono output mix is then sent to the
MONO_OUT pin on the CS4202.

2.5 Input Mux

The input multiplexer controls which analog input
is sent to the ADCs. The output of the input mux is
converted to stereo 18-bit digital PCM data and
transmitted to the controller by means of the
AC-link SDATA_IN signal.

2.6 Volume Control

The CS4202 volume registers control analog input
levels to the input mixer and analog output levels,
including the master volume level. The PC_BEEP
volume control uses 3 dB steps with a range of 0 dB
to -45 dB attenuation. All other analog volume con­trols use 1.5 dB steps. The analog inputs have a
mixing range of +12 dB signal gain to -34.5 dB sig­nal attenuation. The analog output volume controls
have a range of 0 dB to -46.5 dB attenuation for
LINE_OUT, HP_OUT and MONO_OUT.

DS549PP2 13

CS4202

PC_BEEP

PHONE

PCM_OUT

MIC1

MIC2

LINE

CD

VIDEO

AUX

MIC

SELECT

MAIN D/A

CONVERTERS

DAC

BOOST

MUTE

MUTE

MUTE

MUTE

MUTE

MUTE

MUTE

MUTE

PC BEEP BYPASS

ANALOG STEREO

Σ

INPUT MIXER

MONO MIX

SELECT

STEREO TO

MONO MIXER

Σ

ANALOG STEREO

OUTPUT MIXER

STEREO TO

MONO MIXER

Σ

1/2

Σ

1/2

DAC DIRECT

MODE

MONO OUT

SELECT

ADC

INPUT

MUX

MASTER
VOLUME

VOL VOL

HEADPHONE

VOLUME

MONO

VOLUME

VOL

MAIN ADC

GAIN

VOL

MUTE

MUTE

MUTE

OUTPUT
BUFFER

HEADPHONE

AMPLIFIER

OUTPUT
BUFFER

MAIN A/D

CONVERTERS

ADCMUTE

LINE OUT

HEADPHONE OUT

MONO OUT

PCM_IN

VOL

VOL

VOL

VOL VOL

VOL VOL VOL

Figure 8. CS4202 Mixer Diagram

14 DS549PP2

CS4202

3. AC-LINK FRAME DEFINITION

The AC-link is a bi-directional serial port with data
organized into frames consisting of one 16-bit and
twelve 20-bit time-division multiplexed slots.
Slot 0 is a special reserved time slot containing
16-bits which are used for AC-link protocol infra­structure. Slots 1 through 12 contain audio or con­trol/status data. Both the serial data output and
input frames are defined from the controller per­spective, not from the CS4202 perspective.

The controller synchronizes the beginning of a
frame with the assertion of the SYNC signal.
Figure 9 shows the position of each bit location

Tag Phase Data Phase

within the frame. The first bit position in a new se­rial data frame is F0 and the last bit position in the
serial data frame is F255. When SYNC goes active
(high) and is sampled active by the CS4202 (on the
falling edge of BIT_CLK), both devices are syn­chronized to a new serial data frame. The data on
the SDATA_OUT pin at this clock edge is the final
bit of the previous frame’s serial data. On the next
rising edge of BIT_CLK, the first bit of Slot 0 is
driven by the controller on the SDATA_OUT pin.
On the next falling edge of BIT_CLK, the CS4202
latches this data in as the first bit of the frame.

20.8 µs

(48 kHz)

SYNC

BIT_CLK

Bit Frame Position:

SDATA_OUT

Bit Frame Position:

SDATA_IN

12.288 MHz

81.4 ns

F0 F1 F2 F16F15F14F13F12

F255

Valid

Frame

F0 F1 F2 F16F15F14F13F12 F35 F56 F76F255

Codec
Ready

Slot 1

Valid

Slot 1
Valid

GPIO

INT

0

Slot 2

Valid

Slot 2

Valid

Slot 12

Valid

Slot 12

Valid

Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slots 5-12

Codec

Codec

0

ID1

R/W 0 WD15

ID0

0000

Figure 9. AC-link Input and Output Framing

F36 F57

F35

F36

0

F56

D19 D18

F57

D19 D18 D19RD15

F76

D19

D19

D19

F96

F96

F255

F255

GPIO

0

INT

DS549PP2 15

CS4202

3.1 AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4202 from the AC ’97
controller. Figure 9 illustrates the serial port timing.

The PCM playback data being passed to the CS4202 is shifted out MSB first in the most significant bits
of each slot. Any PCM data from the AC ’97 controller that is not 20 bits wide should be left justified in
its corresponding slot and dithered or zero-padded in the unused bit positions.

Bits that are reserved should always be ‘cleared’ by the AC ’97 controller.

3.1.1 Serial Data Output Slot Tags (Slot 0)

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Valid

Slot 1

Frame

Valid

Valid Frame The Valid Frame bit determines if any of the following slots contain either valid playback data

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Not

Implem

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 1 1

Valid

Slot 12

Valid

Res

Codec

ID1

Codec

ID0

for the CS4202 or data for read/write operatio ns. When ‘set’, at least one of th e other AC-link

slots contains valid data. If this bit is ‘clear’, the remainde r of the fr am e is ignor ed .
Slot 1 Valid The Slot 1 Valid bit indicates a valid register read/write address for a primary codec.
Slot 2 Valid The Slot 2 Valid bit indicates valid register write data for a primary codec.
Slot [3:4,6:11] Valid The Slot [3:4,6:11] Valid bits indicate the validity of data in their corresponding serial d ata out-

put slots. If a bit is ‘set’, the corresponding output slot co ntains valid data. If a bit is ‘cleared’,

the corresponding slot will be ignored.
Slot 12 Valid The Slot 12 Valid bit indicates if output Slot 12 contains valid GPIO control data.
Codec ID[1:0] The Codec ID[1:0] bits determine which codec is being accessed during the current AC-link

frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec ID[1:0] = 01,

10, or 11 indicates one of three possible secondary codecs is being accessed. A Codec ID

value of 01, 10, or 11 also indicates a valid read/write add ress and/or valid register write data

for a secondary codec.

3.1.2 Command Address Port (Slot 1)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W

R/W Read/Write. When this bit is ‘set’, a read of the AC ’97 register specified by the register index

RI6 RI5 RI4 RI3 RI2 RI1 RI0 Reserved

bits will occur in the AC ’97 2.x audio codec. When the bit is ‘cleared’, a write will occur. For

any read or write access to occur, the Valid Frame bit (F0) must be ‘set’ and the Codec ID[1:0]

bits (F[14:15]) must match the Codec ID of the AC ’97 2.x audio codec being accessed. Ad-

ditionally, for a primary codec, the Slot 1 Valid bit (F1) must be ‘set’ for a read access and

both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘set’ for a write access. For

a secondary codec, both the Slot 1 Valid bit (F1) and th e Slot 2 Valid bit (F2) must be ‘cleared’

for read and write accesses. See Figure 9 for bit frame positions.
RI[6:0] Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the

CS4202. All registers are defined at word addressable boundaries. The RI0 b it must be ‘clear’

to access CS4202 registers.

16 DS549PP2

CS4202

3.1.3 Command Data Port (Slot 2)

Bit 191817161514131211109876543210

WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Reserved

WD[15:0] Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an ac-

cess is a read, this slot is ignored.

NOTE: For any write to an AC ’97 register, the write is defined to be an ‘atomic’ access. This means

that when the Slot 1 Valid bit in output Slot 0 is ‘set’, the Slot 2 Valid bit in output Slot 0 should
always be ‘set’ during the same audio frame. No write access may be split across 2 frames.

3.1.4 PCM Playback Data (Slots 3-4,6-11)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PD[19:0] Playback Data. The PD[19:0] bits contain the 20-bit PCM (2’s complement) pl ayback data for

the left and right DACs, serial data ports, and/or the S/PDIF transmitter. Table 8 on page 30
lists a cross reference for each function and its respective slot. The mapping of a given slot
to the DAC, serial data port, or S/PDIF transmitter is determined by the state of the DSA[1:0]
bits in the Extended Audio ID Register (Index 28h) and the SPSA[1:0] bits in the Extended

Audio Status/Control Register (Index 2Ah).

3.1.5 GPIO Pin Control (Slot12)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Not Implemented GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Reserved

GPIO[4:0] GPIO Pin Control. The GPIO[4:0] bits control the CS4202 GPIO pins configured as outputs.

Write accesses using GPIO pin control bits configured as outputs will be reflected on the
GPIO pin output on the next AC-link frame. Write accesses using GPIO pin control bits con­figured as inputs will have no effect and are ignored. If the GPOC bit in the Misc. Crystal Con-
trol Register (Index 60h) is ‘set’, the bits in output Slot 12 are ignored and GPIO pins
configured as outputs are controlled through the GPIO Pin Status Register (Index 54h).

DS549PP2 17

CS4202

3.2 AC-Link Serial Data Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4202 to the AC ’97 con­troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 15 illus­trates the serial port timing.

The PCM capture data from the CS4202 is shifted out MSB first in the most significant 18 bits of each slot.
The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the AC ’97
Controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun­cate) to the desired bit depth.

Bits that are reserved or not implemented in the CS4202 will always be returned ‘cleared’.

3.2.1 Serial Data Input Slot Tag Bits (Slot 0)

Bit 1514131211109876543210

Codec
Ready

Codec Ready Codec Ready. The Codec Ready bit indicates the readiness of the CS4202 AC-link. Immedi-

Slot 1

Valid

Slot 2

Valid

Slot 3

ately after a Cold Reset this bit will be ‘clear’. Once the CS4202 clocks and voltages are sta­ble, this bit will be ‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be
attempted by the controller. The Codec Ready bit does not indicate readiness of the DACs,
ADCs, Vref, or any other analog function. Those must be checked in the Powerdown Con-
trol/Status Register (Index 26h) by the controller before any access is ma de to the mixer reg­isters. Any accesses to the CS4202 while Codec Ready is ‘clear’ are ignored.

Valid

Slot 4

Valid

Slot 6

0

Valid

Slot 7

Valid

Slot 8

Valid

00

Slot 1 1

Valid

Slot 12

Valid

Reserved

Slot 1 Valid The Slot 1 Valid bit indicates Slot 1 contains a valid read back address.

Slot 2 Valid The Slot 2 Valid bit indicates Slot 2 contains valid register read data.

Slot [3:4,6:8,11] Valid The Slot [3:4,6:8,11] Valid bits indicate Slot [3:4,6:8,11] contains valid capture data from the

CS4202 ADCs. If a bit is ‘set’, the corresponding input slot contains valid data. If a bit is

‘cleared’, the corresponding slot will be ignored.

Slot 12 Valid The Slot 12 Valid bit indicates Slot 12 contains valid GPIO status data.

3.2.2 Status Address Port (Slot 1)

Bit 191817161514131211109876543210

Res RI6 RI5 RI4 RI3 RI2 RI1 RI0 SR3 SR4 0 SR6 SR7 SR8 SR9 SR10 SR11 0 Reserved

RI[6:0] Register Index. The RI[6:0] bits echo the AC ’97 register address when a register read has

been requested in the previous frame. The CS4202 will only echo the register index for a read
access. Write accesses will not return valid data in Slot 1.

SR[3:4,6:11] Slot Request. If SRx is ‘set’, this indicates the CS4202 SRC does not need a new sample on

the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample
is needed on the following frame. If the VRA bit in the Extended Audio Stat us/Control Register

(Index 2Ah)

abled and the SR[3:4,6:11] bits are used to request data.

is ‘clear’, the SR[3:4,6:11] bits are always 0. When VRA is ‘set’, the SRC is en-

18 DS549PP2

CS4202

3.2.3 Status Data Port (Slot 2)

Bit 1918 17 16 15 14 13121110 9 8 7 6 5 4 3210

RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Reserved

RD[15:0] Read Data. The RD[15:0] bits contain the register data requested by the controller from the

previous read request. All read requests will return the read address in the input Slot 1 and
the register data in the input Slot 2 on the following ser ial data frame.

3.2.4 PCM Capture Data (Slot 3-4,6-8,11)

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 0 0

CD[17:0] Capture Data. The CD [17:0] bits contain 18-bit PCM (2’s complement) capture data. The

data will only be valid when the respective slot valid bit is ‘set’ in input Slot 0. The mapping of
a given slot to an ADC is determined by the state of the ASA[1:0] bits in the AC Mode Control
Register (index 5Eh). The definition of each slot can be found in Table 8 on page 30.

3.2.5 GPIO Pin Status (Slot 12)

Bit 191817161514131211109876543210

0 0000000000GPIO4GPIO3GPIO2GPIO1GPIO0ResBDIRes

GPIO

_INT

GPIO[4:0] GPIO Pin Status. The GPIO [4:0] bits reflect the status of the CS4202 GPIO pins configured

as inputs. The pin status of GPIO pins configured as outputs will be reflected back on the
GPIO[4:0] bits of input Slot 12 in the next frame. The output GPIO pins are controlled by the
GPIO[4:0] pin control bits in output Slot 12.

BDI BIOS-Driver Interface. The BDI bit indicates that a BIOS event has occurred. This bit is a logic

OR of all bits in the BDI Status Register (Index 7Ah) ANDed with their corresponding bit in the
BDI Config Register (Index 70h).

GPIO_INT GPIO Interrupt. The GPIO_INT bit indicates that a GPIO or BDI interrupt event has occurred.

The occurrence of a GPIO interrupt is determined b y the GPIO interrupt requir ements as out­lined in the GPIO Pin Wakeup Mask Register (Index 52h) description. In this case, the
GPIO_INT bit is cleared by writing a ‘0’ to the bit in the GPIO Pin Status Register (Index 54h)
corresponding to the GPIO pin which generated the interrupt.

The occurrence of a BDI interrupt is determined by the BDI interrupt requirements as outlined
in the BDI Control Registers (Index 70h - 72h). In this case, the GPIO_INT bit is cleared by
writing a ‘0’ to the bit in the BDI Status Register (Index 7Ah) that generated the interrupt.

DS549PP2 19

CS4202

3.3 AC-Link Protocol Violation - Loss of

SYNC

The CS4202 is designed to handle SYNC protocol
violations. The following are situations where the
SYNC protocol has been violated:

• The SYNC signal is not sampled high for exact-

ly 16 BIT_CLK clock cycles at the start of an
audio frame.

• The SYNC signal is not sampled high on the

256th BIT_CLK clock period after the previous
SYNC assertion.

• The SYNC signal goes active high before the
256th BIT_CLK clock period after the previous
SYNC assertion.

Upon loss of synchronization with the controller,
the CS4202 will ‘clear’ the Codec Ready bit in the
serial data input frame until two valid frames are
detected. During this detection period, the CS4202
will ignore all register reads and writes and will
discontinue the transmission of PCM capture data.
In addition, if the LOSM bit in the Misc. Crystal
Control Register (Index 60h) is ‘set’ (default), the
CS4202 will mute all analog outputs. If the LOSM
bit is ‘clear’, the analog outputs will not be muted.

20 DS549PP2