Cirrus Logic CS35L03 User Manual
Gate Drivers
Class-H
Controller
Advanced ΔΣ
Modulator
Gate Drivers
Internal
Oscillator
Gain
Gain
Audio In +
Audio In -
Shutdown
Speaker Out +
Speaker Out -
GND
VBATT
2.5V - 5V
LDO Filter
Short C ircuit/ Thermal
Protect ion
MODE
Low Drop-Out
Voltage Regulator
CS35L01/03
3.0 W Mono Class-D Audio Amplifier with Low Idle Current
CS35L01 and CS35L03 Features
Filterless Hybrid Class-D Architecture
– <1 mA Quiescent Current
– 1 x 3.0 W into 4 (10% THD+N)
– 1 x 2.4 W into 4 (1% THD+N)
– 1 x 1.7 W into 8 (10% THD+N)
– 1 x 1.4 W into 8 (1% THD+N)
Advanced Closed-loop Modulation
– 98 dB Signal-to-Noise Ratio (A-Weighted)
– 0.02% THD+N @ 1 W (SD & HD Mode)
Integrated Protection and Automatic Recovery
for Output Short-circuit and Thermal Overload
Pin-compatible 9-ball WLCSP family for easy
upgrade path
– CS35L01: +6 dB default Gain
– CS35L03: +12 dB default Gain
Pop and Click Suppression
Common Applications
Mobile Phones
Laptops/Netbooks/Tablets
Portable Navigation Devices
Active Speakers
Portable Gaming
General Description
The CS35L01 and the CS35L03 are 3.0W high efficiency Hybrid Class-D audio amplifiers with low idle current
consumption.
The CS35L01/03 features an advanced closed-loop architecture to provide 0.02% THD+N at 1 W and -87 dB
PSRR at 217 Hz.
A flexible Hybrid Class-D output stage offers four
modes of operation: Standard Class-D (SD) mode offers full audio bandwidth and high audio performance;
Hybrid Class-D (HD) mode offers a substantial reduction in idle power consumption with an integrated ClassH controller; Reduced Frequency Class-D (FSD) mode
reduces the output switching frequency, producing lower electromagnetic interference (EMI); and Reduced
Frequency Hybrid Class-D (FHD) mode produces both
the lower idle power consumption of HD mode and the
reduced EMI benefits of FSD mode.
Requiring minimal external components and PCB
space, the CS35L01 and CS35L03 are available in a
1.2 mm x 1.2 mm, 9-ball WLCSP package in Commercial grade (-10°C to +70°C). Please see “Ordering
Information” on page 33 for package options and gain
configurations.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
JULY '11
DS909F1
TABLE OF CONTENTS
1. BALL DESCRIPTIONS FOR CS35L01 & CS35L03 .............................................................................. 5
2. DIGITAL BALL CONFIGURATIONS ..................................................................................................... 6
3. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 7
4. CHARACTERISTICS & SPECIFICATIONS ........................................................................................... 8
5. APPLICATIONS ................................................................................................................................... 15
5.1 MODE Descriptions ....................................................................................................................... 15
5.2 Reducing the Gain with External Series Resistors ........................................................................ 16
5.3 Output Filtering with the CS35L01/03 ............................................................................................ 17
5.4 Power-Up and Power-Down .......................................................................................................... 19
5.5 Over Temperature Protection ........................................................................................................ 20
6. TYPICAL PERFORMANCE PLOTS ..................................................................................................... 21
6.1 SD Mode Typical Performance Plots ............................................................................................. 21
6.2 FSD Mode Typical Performance Plots ........................................................................................... 23
6.3 HD Mode Typical Performance Plots ............................................................................................. 25
6.4 FHD Mode Typical Performance Plots ........................................................................................... 27
7. PARAMETER DEFINITIONS ................................................................................................................ 29
8. PACKAGING AND THERMAL INFORMATION .................................................................................. 30
8.1 Package Drawings and Dimensions (Note 20) .............................................................................. 30
8.2 Recommend PCB Footprint and Routing Configuration ................................................................ 31
8.3 Package Thermal Performance ..................................................................................................... 31
9. ORDERING INFORMATION ................................................................................................................ 33
10. REVISION HISTORY .......................................................................... ... .... ... ... ... .... ... ... ... ................... 33
CS35L01/03
2 DS909F1
CS35L01/03
LIST OF FIGURES
Figure 1. Top View of WLCSP Pinout (Looking down through die) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Typical Connection Diagram for SD & FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Typical Connection Diagram for HD & FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Adjusting Gain via External Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Optional Output Filter Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Power-Up Timing with Input Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Power Up Timing without Input Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. THD+N vs. Output Power - SD Mode R
Figure 9. THD+N vs. Output Power - SD Mode R
Figure 10. THD+N vs. Frequency - SD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. THD+N vs. Frequency - SD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. THD+N vs. Frequency - SD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Frequency Response - SD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Idle Current Draw vs. VBATT - SD Mode R
Figure 15. Output Power vs. VBATT - SD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Efficiency vs. Output Power - SD Mode R
Figure 17. Efficiency vs. Output Power - SD Mode R
Figure 18. Supply Current vs. Output Power - SD Mode R
Figure 19. Supply Current vs. Output Power - SD Mode R
Figure 20. THD+N vs. Output Power - FSD Mode R
Figure 21. THD+N vs. Output Power - FSD Mode R
Figure 22. THD+N vs. Frequency - FSD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 23. THD+N vs. Frequency - FSD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 24. THD+N vs. Frequency - FSD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 25. Frequency Response - FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. Idle Current Draw vs. VBATT - FSD Mode R
Figure 27. Output Power vs. VBATT - FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 28. Efficiency vs. Output Power - FSD Mode R
Figure 29. Efficiency vs. Output Power - FSD Mode R
Figure 30. Supply Current vs. Output Power - FSD Mode R
Figure 31. Supply Current vs. Output Power - FSD Mode R
Figure 32. THD+N vs. Output Power - HD Mode R
Figure 33. THD+N vs. Output Power - HD Mode R
Figure 34. THD+N vs. Frequency - HD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 35. THD+N vs. Frequency - HD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 36. THD+N vs. Frequency - HD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 37. Frequency Response- HD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 38. Idle Current Draw vs. VBATT - HD Mode R
Figure 39. Output Power vs. VBATT - HD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 40. Efficiency vs. Output Power - HD Mode R
Figure 41. Efficiency vs. Output Power - HD Mode R
Figure 42. Supply Current vs. Output Power - HD Mode R
Figure 43. Supply Current vs. Output Power - HD Mode R
Figure 44. THD+N vs. Output Power - FHD Mode R
Figure 45. THD+N vs. Output Power - FHD Mode R
Figure 46. THD+N vs. Frequency - FHD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 47. THD+N vs. Frequency - FHD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 48. THD+N vs. Frequency - FHD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 49. Frequency Response - FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 50. Idle Current Draw vs. VBATT - FHD Mode R
Figure 51. Output Power vs. VBATT - FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 52. Efficiency vs. Output Power - FHD Mode R
= 8 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L
= 4 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L
=8W+33mH (Note 16) . . . . . . . . . . . . . . . . . . . . . . . 22
L
= 8 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L
= 4 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L
L
L
= 8 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
L
= 4 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
L
L
L
L
L
= 8 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L
= 4 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L
= 8 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
= 4 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
=8W+33mH (Note 17) . . . . . . . . . . . . . . . . . . . . . . 24
L
= 8 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L
= 4 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L
L
= 8 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L
= 4 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L
=8W+33mH (Note 18) . . . . . . . . . . . . . . . . . . . . . . . 26
= 8 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
= 4 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
= 8 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L
= 4 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L
= 8 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
= 4 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
=8W+33mH (Note 19) . . . . . . . . . . . . . . . . . . . . . . 28
L
= 8 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L
DS909F1 3
CS35L01/03
Figure 53. Efficiency vs. Output Power - FHD Mode R
Figure 54. Supply Current vs. Output Power - FHD Mode R
Figure 55. Supply Current vs. Output Power - FHD Mode R
= 4 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L
= 8 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L
= 4 W + 33 mH . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L
LIST OF TABLES
Table 1. LFILT+ and MODE Operation Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2. JA Specification for Typical PCB Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 DS909F1
1. BALL DESCRIPTIONS FOR CS35L01 & CS35L03
A1
IN+
A2
MODE
A3
OUT-
B1
LFILT +
B2
VBATT
B3
GND
C1
IN-
C2
SD
C3
OUT+
Figure 1. Top View of WLCSP Pinout
(Looking down through die)
CS35L01/03
Ball Name
IN+ A1 Positive Analog Input (Input) - Differential positive audio signal input.
MODE A2 Switching Mode (Input) - Controls the output switching modes of the CS35L01/03.
OUT- A3 Negative PWM Output (Output) - Differential negative PWM output.
LFILT+ B1
VBATT B2 Positive Analog Power Supply (Input) - Positive power supply input.
GND B3 Ground (Input) - Power supply ground.
IN- C1 Negative Analog Input (Input) - Differential negative audio signal input.
SD
OUT+ C3 Positive PWM Output (Output) - Differential Positive PWM output.
#
Description
Low Drop Out Regulator Filter (Output) - Bypass capacitor connection point for internal LDO. Con-
necting this net to VBATT places the device into SD mode.
C2 Shutdown (Input) - Pulling this net low places the CS35L01/03 in shutdown.
DS909F1 5
CS35L01/03
2. DIGITAL BALL CONFIGURATIONS
See (Note 1) and (Note 2) below the table.
Power Supply I/O Name Ball Direction Internal Connections Configuration
C2 Input No Internal Pull Up Hysteresis on CMOS Input
VBATT
Note:
1. Refer to specification table “Digital Interface Specifications and Characteristics” on page 14 for details
on the digital I/O characteristics.
2. I/O voltage levels must not exceed the voltage listed in table “Absolute Maximum Ratings” on page 8.
SD
MODE A2 Input No Internal Pull Up Hysteresis on CMOS Input
6 DS909F1
3. TYPICAL CONNECTION DIAGRAMS
Audio In+
Audio In-
System
Controller
GND
AIN+
AIN+
MODE
OUT+
OUT-
2.5V - 5V
VBATTLFILT+
10uF0. 1uF
SD
1uF
0.1uF
2.5V - 5 V
10u F
Audio In+
Audio In-
System
Controller
GND
AIN+
AIN+
MODE
OUT+
OUT-
VBATTLFILT+
SD
(Note 3)
CS35L01/03
Note:
Figure 2. Typical Connection Diagram for SD & FSD Mode
3. The value of the capacitance connected to the LFILT+ net should not exceed 4.7 F. Presence of a
capacitance above 4.7 F will prevent proper HD and FHD operation.
Figure 3. Typical Connection Diagram for HD & FHD Mode
DS909F1 7
CS35L01/03
4. CHARACTERISTICS & SPECIFICATIONS
Test Conditions (unless otherwise specified): GND = 0 V; All voltages with respect to ground; Input signal = 997 Hz
differential sine wave; T
= 25°C; VBATT = 5.0 V; RL=8; 22 Hz to 20 kHz measurement bandwidth; Measure-
A
ments taken with AES17 measurement filter and Audio Precision AUX-0025 passive filter.
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; All voltages with respect to ground. Please see (Note 4).
Parameters Symbol Min Typ Max Units
DC Power Supply
Supply Voltage VBATT 2.5 5.0 5.5 V
Temperature
Ambient Temperature T
Junction Temperature T
A
J
-10 - +70 °C
-10 - +150 °C
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; All voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply
Supply Voltage VBATT -0.3 6.0 V
LFILT+ Current (Note 5) I
VDREG
Inputs
Input Current I
in
Temperature
Ambient Operating Temperature (power applied) T
Storage Temperature T
A
stg
WARNING:Operation at or beyond these limits may result in permanent damage to the device.
-10A
-±10mA
-20 +125 °C
-65 +150 °C
Notes:
4. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may
adversely affect device reliability.
5. No external loads should be connected to the LFILT+ net. Any connection of a load to this point may
result in errant operation or performance degradation in the device.
8 DS909F1
ELECTRICAL CHARACTERISTICS - ALL OPERATIONAL MODES
Parameters Symbol Test Conditions Min Typ Max Units
Max. Current from LFILT+ (Note 6)
LFILT+ Output Impedance Z
VBATT Limit for HD/FHD Mode (Note 7)
Input Level for Entering LDO Operation in
HD/FHD Modes (Note 8)
Input Level for Entering VBATT Operation in
HD/FHD Modes (Note 9)
I
LFILT+
LFILT+
VB
V
IN-LDO
V
IN-VBATT
LIM
CS35L03
CS35L01
CS35L03
CS35L01
-10 -A
-0.7 -
-3.0 -VDC
--0.015•VBATT
0.029•VBATT--
-
-
0.09
0.19
CS35L01/03
Vrms
Vrms
--Vrms
Vrms
LDO Entry Time Delay
LDO Level for HD/FHD Modes
Output Offset Voltage
t
LDO
V
V
OFFSET
Amplifier Gain
Shutdown Supply Current I
MOSFET On Resistance R
Thermal Error Threshold (Note 10)
Thermal Error Retry Time (Note 10)
Under Voltage Lockout Threshold (Note 11)
A(SD)
DS(ON)
T
R
UVLO - 2.0 - V
Operating Efficiency
LDO
Inputs AC coupled to GND
CS35L03
A
V
CS35L01
SD = Low
I
= 0.5 A
bias
TE
TE
Output Levels at 10% THD+N
VBATT = 5 VDC - 92 - %
Load
VBATT = 3.7 VDC - 91 - %
8 + 33H
VBATT = 5 VDC - 87 - %
Load
VBATT = 3.7 VDC - 86 - %
4 + 33H
- 1200 - ms
-1.0 -V
-+/-1.5 -mV
-
-
12
--dB
6
dB
-0.05 -A
-270 -m
-150 -C
-100 -ms
Note:
6. No external loads should be connected to the LFILT+ net. Any connection of a load to this point may
result in errant operation or performance degradation in the device.
7. When VBATT is below this threshold (VB
), operation is automatically restricted to SD mode.
LIM
8. When operating in HD or FHD mode and the differential input voltage remains below the input level
threshold (V
) for a period of time (t
IN-LDO
), the PWM outputs will be powered by the internally
LDO
generated LDO supply (VLDO).
9. When operating in HD or FHD mode and the differential input voltage is above this input level
threshold (V
IN-VBATT
), the PWM outputs will be powered directly from the VBATT supply.
10. Refer to Section 5.5 for more information on Thermal Error functionality.
11. Under Voltage Lockout is the threshold at which a decreasing VBATT supply will disable device
operation.
DS909F1 9
ELECTRICAL CHARACTERISTICS - SD MODE
Parameters Symbol Test Conditions Min Typ Max Units
THD+N = 1%
= 8 (VBATT = 5.0/4.2/3.7 VDC)
R
L
Output Power
(Continuous Average)
Total Harmonic Distortion + Noise THD+N
Power Supply Rejection Ratio PSRR
RL = 4 (VBATT = 5.0/4.2/3.7 VDC)
P
O
THD+N = 10%
= 8 (VBATT = 5.0/4.2/3.7 VDC)
R
L
= 4 (VBATT = 5.0/4.2/3.7 VDC)
R
L
PO = 1.0 W
V
= 200 mVPP, AINx AC coupled to GND
ripple
@ 217 Hz
@ 1 kHz
CS35L01/03
-
1.39/0.98/0.76
-
2.41/1.69/1.30
-
1.73/1.23/0.95
-
3.03/2.12/1.64
-0.02 -%
-
-
87
82
-
W
W
-
W
W
-
dB
-
dB
Common-Mode Rejection Ratio CMRR
V
ripple
=1VPP, f
ripple
= 217 Hz
-73 -dB
Inputs AC Coupled to Ground,
Signal to Noise Ratio
A-Weighted
SNR
Referenced to 1% THD+N (Note 13)
A
CS35L03
CS35L01
-
-
96
97
-
dB
-
dB
AIN+ connected to AIN-
Idle Channel Noise
A-Weighted
ICN
A
CS35L03
CS35L01
-
-
54
49
--Vrms
Vrms
AIN+ connected to AIN-
Idle Channel Noise ICN
CS35L03
CS35L01
-
-
110
100
--Vrms
Vrms
Frequency Response FR 20 Hz to 20 kHz -0.1 0 0.4 dB
Total Group Delay GD - 6 - s
Output Switching Frequency
f
sw1
-192 -kHz
AIN+ connected to AIN-, No Output Load
Idle Current Draw (Note 12) I
Input Impedance, Single Ended
VBATT = 5.0 VDC
IDLE
VBATT = 4.2 VDC
VBATT = 3.7 VDC
CS35L03
Z
IN
CS35L01
-
-
-
-
-
1.40
1.28
1.21
65
100
-
mA
-
mA
-
mA
-
k
-
k
RL = 8 (VBATT = 5.0/4.2/3.7 VDC)
Input Voltage @ 1 % THD+N V
ICLIP
CS35L03
CS35L01
--0.85/0.72/0.63
1.71/1.44/1.26--
Vrms
Vrms
10 DS909F1
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