How it Works
Cirrus Logic
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CS35L00
User Manual
34 pgs748.21 Kb0
Table of contents
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Cirrus Logic CS35L00 User Manual

Gate Drivers
Controller
Advanced ΔΣ
Modulator
Gate Drivers
Internal
Oscillator
Gain
Gain
Audio In +
Audio In -
Shutdow n
Speaker Out + Speaker Out -
GND
VBATT
2.5V - 5 V
LDO Filter
Short C ircuit/Thermal
Protec tion
MODE
Low Drop-Out
Volta ge Re gulator
Gain Select
CS35L00
2.8 W Mono Class-D Audio Amplifier with Low Idle Current
CS35L00 Features
Hybrid Class-D Architecture
– <1 mA Quiescent Current – 1 x 2.8 W into 4 Ω (10% THD+N) – 1 x 2.3 W into 4 Ω (1% THD+N) – 1 x 1.7 W into 8 Ω (10% THD+N) – 1 x 1.4 W into 8 Ω (1% THD+N)
Advanced ΔΣ Closed-loop Modulation
– 98 dB Signal-to-Noise Ratio (A-Weighted) – 0.02% THD+N @ 1 W (SD & HD Mode)
Integrated Protection and Automatic Recovery
for Output Short-circuit and Thermal Overload
Thermally Enhanced 10-pin DFN Package with
Pin-selectable Gain of +6 dB or +12 dB
Pop and Click Suppression
Common Applications
LaptopsNetbooksPortable Navigation DevicesActive SpeakersPortable Gaming
General Description
The CS35L00 is a 2.8 W high efficiency Hybrid Class-D audio amplifier with low idle current consumption and a selectable gain.
The CS35L00 features an advanced closed-loop archi­tecture to provide 0.02% THD+N at 1 W and -88 dB PSRR at 217 Hz.
A flexible Hybrid Class-D output stage offers four modes of operation: Standard Class-D (SD) mode of­fers full audio bandwidth and high audio performance; Hybrid Class-D (HD) mode offers a substantial reduc­tion in idle power consumption with an integrated Class­H controller; Reduced Frequency Class-D (FSD) mode reduces the output switching frequency, producing low­er electromagnetic interference (EMI); and Reduced Frequency Hybrid Class-D (FHD) mode produces both the lower idle power consumption of HD mode and the reduced EMI benefits of FSD mode.
Requiring minimal external components and PCB space, the CS35L00 is available in a 3.0 mm x 3.0 mm, 10-pin DFN package in Commercial grade (-10°C to +70°C). Please see “Ordering Information” on page 33 for package options and gain configurations.
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS906PP1
FEB '11
TABLE OF CONTENTS
1. PIN DESCRIPTIONS FOR CS35L00 ..................................................................................................... 5
2. DIGITAL PIN CONFIGURATIONS ................................................................. ... ... .... ... ... ... ... .... .............. 6
3. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 7
4. CHARACTERISTICS & SPECIFICATIONS ........................................................................................... 8
RECOMMENDED OPERATING CONDITIONS .................................................................................... 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8
ELECTRICAL CHARACTERISTICS - ALL OPERATIONAL MODES ................................................... 9
ELECTRICAL CHARACTERISTICS - SD MODE ................................................................................ 10
ELECTRICAL CHARACTERISTICS - FSD MODE .............................................................................. 11
ELECTRICAL CHARACTERISTICS - HD MODE ................................................................................ 12
ELECTRICAL CHARACTERISTICS - FHD MODE ............................................................................. 13
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS .................................................... 14
POWER-UP & POWER-DOWN CHARACTERISTICS ........................................................................ 14
5. APPLICATIONS ................................................................................................................................... 15
5.1 MODE Descriptions ....................................................................................................................... 15
5.1.1 Standard Class D Modes of Operation .................................................................................. 15
5.1.1.1 SD Mode .................................................................................................................... 15
5.1.1.2 FSD Mode .................................................................................................................. 15
5.1.2 Hybrid Class D Modes of Operation ...................................................................................... 15
5.1.2.1 HD Mode .................................................................................................................... 16
5.1.2.2 FHD Mode ................................................................................................................. 16
5.2 Reducing the Gain with External Series Resistors ........................................................................ 16
5.3 Output Filtering with the CS35L00 ................................................................................................. 17
5.3.1 Reduced Filter Order with the CS35L00 ............................................................................... 17
5.3.2 Filter Component Selection ................................................................................................... 17
5.3.3 Output Filter Power Dissipation Considerations .................................................................... 18
5.3.3.1 Conduction Losses for All Modes of Operation ......................................................... 18
5.3.3.2 Switching Losses in SD/FSD Mode ........................................................................... 18
5.3.3.3 Switching Losses in HD/FHD. .................................................................................... 18
5.4 Power-Up and Power-Down .......................................................................................................... 19
5.4.1 Recommended Power-Up Sequence .................................................................................... 19
5.4.1.1 Zero Crossing on Power-Up Functionality ................................................................. 19
5.4.2 Recommended Power-Down Sequence ............................................................................... 20
5.5 Over Temperature Protection ........................................................................................................ 20
6. TYPICAL PERFORMANCE PLOTS ..................................................................................................... 21
6.1 SD Mode Typical Performance Plots ............................................................................................. 21
6.2 FSD Mode Typical Performance Plots ........................................................................................... 23
6.3 HD Mode Typical Performance Plots ............................................................................................. 25
6.4 FHD Mode Typical Performance Plots ........................................................................................... 27
7. PARAMETER DEFINITIONS ................................................................................................................ 29
8. PACKAGING AND THERMAL INFORMATION .................................................................................. 30
8.1 Package Drawings and Dimensions .............................................................................................. 30
8.2 Recommend PCB Footprint and Routing Configuration ................................................................ 31
8.3 Package Thermal Performance ..................................................................................................... 31
8.4 DFN Thermal Pad .......................................................................................................................... 31
8.4.1 Determining Maximum Ambient Temperature ....................................................................... 32
9. ORDERING INFORMATION ................................................................................................................ 33
10. REVISION HISTORY ....................................... ... ... ... .... ................................................ ... ................... 33
CS35L00
2 DS906PP1
CS35L00
LIST OF FIGURES
Figure 1.Top View of DFN Pin Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2.Typical Connection Diagram for SD & FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3.Typical Connection Diagram for HD & FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4.Adjusting Gain via External Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5.Optional Output Filter Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6.Power-Up Timing with Input Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7.Power Up Timing without Input Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8.THD+N vs. Output Power - SD Mode R Figure 9.THD+N vs. Output Power - SD Mode R
Figure 10.THD+N vs. Frequency - SD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11.THD+N vs. Frequency - SD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12.THD+N vs. Frequency - SD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13.Frequency Response - SD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14.Idle Current Draw vs. VBATT - SD Mode R
Figure 15.Output Power vs. VBATT - SD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16.Efficiency vs. Output Power - SD Mode R Figure 17.Efficiency vs. Output Power - SD Mode R Figure 18.Supply Current vs. Output Power - SD Mode R Figure 19.Supply Current vs. Output Power - SD Mode R Figure 20.THD+N vs. Output Power - FSD Mode R Figure 21.THD+N vs. Output Power - FSD Mode R
Figure 22.THD+N vs. Frequency - FSD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 23.THD+N vs. Frequency - FSD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 24.THD+N vs. Frequency - FSD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 25.Frequency Response - FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26.Idle Current Draw vs. VBATT - FSD Mode R
Figure 27.Output Power vs. VBATT - FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 28.Efficiency vs. Output Power - FSD Mode R Figure 29.Efficiency vs. Output Power - FSD Mode R Figure 30.Supply Current vs. Output Power - FSD Mode R Figure 31.Supply Current vs. Output Power - FSD Mode R Figure 32.THD+N vs. Output Power - HD Mode R Figure 33.THD+N vs. Output Power - HD Mode R
Figure 34.THD+N vs. Frequency - HD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 35.THD+N vs. Frequency - HD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 36.THD+N vs. Frequency - HD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 37.Frequency Response- HD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 38.Idle Current Draw vs. VBATT - HD Mode R
Figure 39.Output Power vs. VBATT - HD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 40.Efficiency vs. Output Power - HD Mode R Figure 41.Efficiency vs. Output Power - HD Mode R Figure 42.Supply Current vs. Output Power - HD Mode R Figure 43.Supply Current vs. Output Power - HD Mode R Figure 44.THD+N vs. Output Power - FHD Mode R Figure 45.THD+N vs. Output Power - FHD Mode R
Figure 46.THD+N vs. Frequency - FHD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 47.THD+N vs. Frequency - FHD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 48.THD+N vs. Frequency - FHD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 49.Frequency Response - FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 50.Idle Current Draw vs. VBATT - FHD Mode R
Figure 51.Output Power vs. VBATT - FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 52.Efficiency vs. Output Power - FHD Mode R
=8Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L
=4Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L
=4Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L
L
L
=8Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
L
=4Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
L
L
L
L
L
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L
=4Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L
=8Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
=4Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L
=4Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L
L
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L
=4Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
=4Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L
=4Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L
=8Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
=4Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L
DS906PP1 3
CS35L00
Figure 53.Efficiency vs. Output Power - FHD Mode R Figure 54.Supply Current vs. Output Power - FHD Mode R Figure 55.Supply Current vs. Output Power - FHD Mode R
=4Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L
=8Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L
=4Ω +33μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L
LIST OF TABLES
Table 1. LFILT+ and MODE Operation Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2. θ
Specification for Typical PCB Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
JA
4 DS906PP1

1. PIN DESCRIPTIONS FOR CS35L00

1
2
3
4
5
10
9
8
7
6
Thermal Pad
SD
IN-
LFILT+
IN+
MODE
OUT+
GND
VBATT
GAIN_SEL
OUT-
Figure 1. Top View of DFN Pin Out
(Looking down through package)
CS35L00
Pin Name
SD 1 Shutdown (Input) - Pulling this pin low places the CS35L00 in shutdown. IN- 2 Negative Analog Input (Input) - Differential negative audio signal input
LFILT+ 3
IN+ 4 Positive Analog Input (Input) - Differential positive audio signal input. MODE 5 Switching Mode (Input) - Controls the output switching modes of the CS35L00. OUT- 6 Negative PWM Output (Output) - Differential negative PWM output.
GAIN_SEL 7
VBATT 8 Positive Analog Power Supply (Input) - Positive power supply input. GND 9 Ground (Input) - Power supply ground. OUT+ 10 Positive PWM Output (Output) - Differential Positive PWM output.
Thermal Pad -
#
Pin Description
Low Drop Out Regulator Filter (Output) - Bypass capacitor connection point for internal LDO. Con-
necting this net to VBATT places the device into SD mode.
Gain Select (Input) - Sets the gain of the amplifier. When pulled low, gain is +12 dB. When pulled high,
gain is +6 dB.
Thermal Pad (Input) - Thermal relief pad for optimized heat dissipation. Connect to GND. See “DFN
Thermal Pad” on page 31 for more information.
DS906PP1 5
CS35L00

2. DIGITAL PIN CONFIGURATIONS

See (Note 1) and (Note 2) below the table.
Power Supply I/O Name Pin # Direction Internal Connections Configuration
SD
1 Input No Internal Pull Up Hysteresis on CMOS Input
VBATT
Note:
1. Refer to specification table “Digital Interface Specifications & Characteristics” on page 14 for details on the digital I/O characteristics.
2. I/O voltage levels must not exceed the voltage listed in table “Absolute Maximum Ratings” on page 8.
MODE 5 Input No Internal Pull Up Hysteresis on CMOS Input
GAIN_SEL 7 Input No Internal Pull Up Hysteresis on CMOS Input
6 DS906PP1

3. TYPICAL CONNECTION DIAGRAMS

Audio In+
Audio In-
System
Controller
GND
AIN+
AIN+
MODE
OUT+
OUT-
2.5V - 5V
VBATTLFILT+
10u F0. 1uF
Connec t to
VBATT for + 6dB Gain
or
GND for +12dB Gain
SD
GAIN_SEL
1uF
0.1 uF
2.5V - 5V
10u F
Audio In+
Audio In-
System
Controller
GND
AIN+
AIN+
MODE
OUT+
OUT-
VBATTLFILT+
Connect to
VBATT for +6dB Gain
or
GND for +12dB Gain
SD
GAIN_ SEL
(Note 3)
CS35L00
Figure 2. Typical Connection Diagram for SD & FSD Mode
Figure 3. Typical Connection Diagram for HD & FHD Mode
Note:
3. The value of the capacitance connected to the LFILT+ net should not exceed 4.7 μF. Presence of a capacitance above 4.7 μF will prevent proper HD and FHD operation.
DS906PP1 7
CS35L00

4. CHARACTERISTICS & SPECIFICATIONS

Test Conditions (unless otherwise specified): GND = 0 V; All voltages with respect to ground; Input signal = 997 Hz differential sine wave; T
= 25°C; VBATT = 5.0 V; RL=8Ω; 22 Hz to 20 kHz measurement bandwidth; Measure-
A
ments taken with AES17 measurement filter and Audio Precision AUX-0025 passive filter.

RECOMMENDED OPERATING CONDITIONS

GND = 0 V; All voltages with respect to ground. Please see (Note 4).
Parameters Symbol Min Typ Max Units
DC Power Supply
Supply Voltage VBATT 2.5 5.0 5.5 V
Temperature
Ambient Temperature T
Junction Temperature T
A
J
-10 - +70 °C
-10 - +150 °C

ABSOLUTE MAXIMUM RATINGS

GND = 0 V; All voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply
Supply Voltage VBATT -0.3 6.0 V LFILT+ Current (Note 5) I
VDREG
Inputs
Input Current I
in
Temperature
Ambient Operating Temperature (power applied) T Storage Temperature T
A
stg
WARNING:Operation at or beyond these limits may result in permanent damage to the device.
-10μA
-±10mA
-20 +125 °C
-65 +150 °C
Notes:
4. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability.
5. No external loads should be connected to the LFILT+ net. Any connection of a load to this point may result in errant operation or performance degradation in the device.
8 DS906PP1

ELECTRICAL CHARACTERISTICS - ALL OPERATIONAL MODES

Parameters Symbol Test Conditions Min Typ Max Units
Max. Current from LFILT+ (Note 6)
LFILT+ Output Impedance Z
VBATT Limit for HD/FHD Mode (Note 7)
Input Level for Entering LDO Operation in HD/FHD Modes (Note 8)
Input Level for Entering VBATT Operation in HD/FHD Modes (Note 9)
I
LFILT+
LFILT+
VB
V
IN-LDO
V
IN-VBATT
LIM
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
-10 -μA
-0.7 -Ω
-3.0 -VDC
--0.015•VBATT
0.029•VBATT--
-
-
0.10
0.20
CS35L00
Vrms Vrms
--Vrms Vrms
LDO Entry Time Delay
t
LDO
- 1200 - ms
LDO Level for HD/FHD Modes VLDO - 1.0 - V
Output Offset Voltage
V
Amplifier Gain
Shutdown Supply Current I
MOSFET On Resistance R
Thermal Error Threshold (Note 10)
Thermal Error Retry Time (Note 10)
Under Voltage Lockout Threshold (Note 10)
OFFSET
A(SD)
DS(ON)
T
R
UVLO - 2.0 - V
Inputs AC coupled to GND
GAIN_SEL = Low
A
V
GAIN_SEL = High
SD = Low
I
= 0.5 A
bias
TE
TE
-+/-2 -mV
-
-
12
--dB
6
dB
-0.05 -μA
-350 -mΩ
-150 -°C
- 1200 - ms
Output Levels at 10% THD+N
VBATT = 5 VDC - 90 - %
Load
Operating Efficiency η
VBATT = 3.7 VDC - 89 - %
8 Ω + 33μH
VBATT = 5 VDC - 84 - %
Load
VBATT = 3.7 VDC - 83 - %
4 Ω + 33μH
Note:
6. No external loads should be connected to the LFILT+ net. Any connection of a load to this point may result in errant operation or performance degradation in the device.
7. When VBATT is below this threshold (VB
), operation is automatically restricted to SD mode.
LIM
8. When operating in HD or FHD mode and the differential input voltage remains below the input level threshold (V
) for a period of time (t
IN-LDO
), the PWM outputs will be powered by the internally
LDO
generated LDO supply (VLDO).
9. When operating in HD or FHD mode and the differential input voltage is above this input level threshold (V
IN-VBATT
), the PWM outputs will be powered directly from the VBATT supply.
10. Refer to Section 5.5 for more information on Thermal Error functionality.
11. Under Voltage Lockout is the threshold at which a decreasing VBATT supply will disable device operation.
DS906PP1 9

ELECTRICAL CHARACTERISTICS - SD MODE

Parameters Symbol Test Conditions Min Typ Max Units
THD+N = 1%
= 8 Ω (VBATT = 5.0/4.2/3.7 VDC)
R
L
Output Power (Continuous Average)
Total Harmonic Distortion + Noise THD+N
Power Supply Rejection Ratio PSRR
RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC)
P
O
THD+N = 10%
= 8 Ω (VBATT = 5.0/4.2/3.7 VDC)
R
L
= 4 Ω (VBATT = 5.0/4.2/3.7 VDC)
R
L
PO = 1.0 W
V
= 200 mVPP, AINx AC coupled to GND
ripple
@ 217 Hz @ 1 kHz
CS35L00
-
1.35/0.95/0.73
-
2.25/1.58/1.22
-
1.67/1.18/0.91
-
2.82/2.00/1.53
-0.02 -%
-
-
88 82
-
W
­W
-
W
­W
-
dB
-
dB
Common-Mode Rejection Ratio CMRR
V
ripple
=1VPP, f
ripple
= 217 Hz
-73 -dB
Inputs AC Coupled to Ground,
Signal to Noise Ratio A-Weighted
SNR
Referenced to 1% THD+N (Note 13)
A
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
-
-
96 97
-
dB
-
dB
AIN+ connected to AIN-
Idle Channel Noise A-Weighted
ICN
A
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
-
-
54 49
--μVrms
μVrms
AIN+ connected to AIN-
Idle Channel Noise ICN
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
-
-
110
100
--μVrms
μVrms
Frequency Response FR 20 Hz to 20 kHz -0.1 0 0.4 dB
Total Group Delay GD - 6 - μs
Output Switching Frequency
f
sw1
-192 -kHz
AIN+ connected AIN-, No Output Load
Idle Current Draw (Note 12) I
Input Impedance, Single Ended Z
VBATT = 5.0 VDC
IDLE
VBATT = 4.2 VDC VBATT = 3.7 VDC
GAIN_SEL = Low (12 dB)
IN
GAIN_SEL = High (6 dB)
-
-
-
-
-
1.42
1.31
1.24
65
100
-
mA
-
mA
-
mA
-
kΩ
-
kΩ
RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC)
Input Voltage @ 1 % THD+N V
GAIN_SEL = Low (12 dB)
ICLIP
GAIN_SEL = High (6 dB)
--0.85/0.72/0.63
1.70/1.43/1.25--
Vrms Vrms
10 DS906PP1

ELECTRICAL CHARACTERISTICS - FSD MODE

Parameters Symbol Test Conditions Min Typ Max Units
THD+N = 1%
= 8 Ω (VBATT = 5.0/4.2/3.7 VDC)
R
L
Output Power (Continuous Average)
Total Harmonic Distortion + Noise THD+N
Power Supply Rejection Ratio PSRR
RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC)
P
O
THD+N = 10%
= 8 Ω (VBATT = 5.0/4.2/3.7 VDC)
R
L
= 4 Ω (VBATT = 5.0/4.2/3.7 VDC)
R
L
PO = 1.0 W - 0.10 - %
V
= 200 mVPP, AINx AC coupled to GND
ripple
@ 217 Hz @ 1 kHz
-
1.28/0.90/0.69
-
2.16/1.51/1.15
-
1.65/1.17/0.90
-
2.76/1.95/1.51
-
-
88 80
CS35L00
-
W
­W
-
W
­W
-
dB
-
dB
Common-Mode Rejection Ratio CMRR
V
ripple
=1VPP, f
ripple
=217Hz
-71 -dB
Inputs AC Coupled to Ground,
Signal to Noise Ratio A-Weighted
SNR
Referenced to 1% THD+N (Note 13)
A
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
-
-
80 80
-
dB
-
dB
AIN+ connected to AIN-
Idle Channel Noise A-Weighted
ICN
A
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
-
-
300 290
--μVrms
μVrms
AIN+ connected to AIN-
Idle Channel Noise ICN
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
-
-
570 550
--μVrms
μVrms
Frequency Response FR 20 Hz to 20 kHz -4.0 0 0.5 dB
Total Group Delay GD - 14 - μs
Output Switching Frequency
f
sw2
- 76 - kHz
AIN+ connected AIN-, No Output Load
Idle Current Draw (Note 12) I
Input Impedance, Single Ended Z
VBATT = 5 VDC
IDLE
VBATT = 4.2 VDC VBATT = 3.7 VDC
GAIN_SEL = Low (12 dB)
IN
GAIN_SEL = High (6 dB)
-
-
-
-
-
1.07
1.01
0.97
160 250
-
mA
-
mA
-
mA
--kΩ
kΩ
RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC)
Input Voltage @ 1 % THD+N V
GAIN_SEL = Low (12 dB)
ICLIP
GAIN_SEL = High (6 dB)
--0.83/0.69/0.61
1.65/1.38/1.21--
Vrms Vrms
Note:
12. Idle Current Draw (I
) is specified without any output filtering. Refer to Section 5.3 on page 17 for
IDLE
information on output filtering.
DS906PP1 11
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