–8 Independently Controllable Channels
–3 Configurable Master Volume and Muting
Controls
Wide Adjustable Volume Range
–-96 dB to +22 dB in ¼ dB Steps
Low Distortion & Noise
–-112 dB THD+N
–127 dB Dynamic Range
Noise-Free Level Transitions
–Zero-Crossing Detection with
Programmable Time-Out
Low Channel-to-Channel Crosstalk
–120 dB Inter-Channel Isolation
Comprehensive Serial Control Port
–Supports I²C
–Independent Control of up to 128 Devices
on a Shared 2-Wire I²C or 3-Wire SPI
Control Bus
–Supports Individual and Grouped Control of
all CS3318 Devices on the I²C or SPI
Control Bus
Flexible Power Supply Voltages
–±8 V to ±9 V Analog Supply
–+3.3 V Digital Supply
®
and SPITM Communication
Description
The CS3318 is an 8-channel digitally controlled analog
volume control designed specifically for high-end audio
systems. It features a comprehensive I²C/SPI serial
control port for easy device and volume configuration.
The CS3318 includes arrays of well-matched resistors
and complementary low-noise active output stages. A
total adjustable range of 118 dB, in ¼ dB steps, is
spread evenly over 96 dB of attenuation and 22 dB of
gain.
The CS3318 implements configurable zero-crossing
detection to provide glitch-free volume-level changes.
The I²C/SPI control interface provides for easy system
integration of up to 128 CS3318 devices over a single 2wire I²C or 3-wire SPI bus, allowing many channels of
volume control with minimal system controller I/O requirements. Devices may be controlled on an ind ividual
and grouped basis, simplifying simultaneous configuration of a group of channels across multiple devices,
while allowing discrete control over all channels on an
individual basis.
The device operates from ±8 V to ±9 V analog supplies
and has an input/output voltage range of ±6.65 V to
±7.65 V. The digital control interface operates at +3.3 V.
The CS3318 is available in a 48-pin LQFP package in
Commercial grade (-10° to 70° C). The CS3318 Customer Demonstration board is also available for device
evaluation. Refer to “Ordering Information” on page 44
for complete details.
Analog Inputs (Input) - The full-scale level is specified in the Analog Characteristics specification
table.
29
22
19
12
13 14 15 16 17 18 19 20 21 22 23 24
OUT8
REFO8
OUT7
VA-
VA+
IN7
REF07
REFI7
REFI6
IN6
REFO6
OUT6
DS693F15
CS3318
Pin Name#Pin Description
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
REFI1
REFI2
REFI3
REFI4
REFI5
REFI6
REFI7
REFI8
REFO1
REFO2
REFO3
REFO4
REFO5
REFO6
REFO7
REFO8
VA+
VA-
RESET
MUTE
SCL/CCLK5Serial Control Port Clock (Input) - Serial clock for the serial control port.
SDA/MOSI6
AD0/CS
ENOut8Enable Output (Output) - Enable output signal for multi-device serial control chain configuration.
DGND9Digital Ground (Input) - Ground reference for the internal digital section.
VD10Digital Power (Input) - Positive power for the internal digital section.
47
44
37
34
Analog Outputs (Output) - The full-scale output level is specified in the Analog Characteristics specifi-
cation table.
27
24
17
14
2
41
40
31
Reference In (Input) - Analog reference pin.
30
21
20
11
48
43
38
33
Reference Out (Output) - Analog reference pin.
28
23
18
13
15,
25,
Positive Analog Power (Input) - Positive power for the internal analog section.
35,
45
16,
26,
Negative Analog Power (Input) - Negative power for the internal analog section.
36,
46
3Reset (Input) - The device enters a low-power mode when this pin is driven low.
Mute (Input) - This pin defaults to an active low mute input, and may be configured as an active high
4
mute input.
SerialControl Data (Input/Output) - SDA is a data I/O line for the control port interface in I²C Mode.
MOSI is the input data line for the control port interface in SPI Mode.
Default Address Bit 0 (I²C) / Control Port Chip Select (SPI)(Input) - AD0 sets the LSB of the default
7
chip address in I²C Mode. CS
is the chip-select signal for SPI format.
6DS693F1
CS3318
2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and T
= 25°C.
A
SPECIFIED OPERATING CONDITIONS
(DGND = 0 V; All voltages with respect to ground.)
ParametersSymbol Min NomMaxUnits
DC Power Supplies:Positive Analog
Negative Analog
Digital
Ambient Operating Temperature (Power Applied)T
VA+
VAVD
7.6
-9.45
3.1
A
-10-+70°C
9.0
-9.0
3.3
9.45
-7.6
3.5
V
V
V
ABSOLUTE MAXIMUM RATINGS
(DGND = 0 V; All voltages with respect to ground. (Note 1)
ParameterSymbolMinMaxUnits
DC Power Supplies:Positive Analog
Negative Analog
Digital
Input Current(Note 2)I
Analog Input VoltageV
Digital Input VoltageV
Ambient Operating Temperature (Power Applied)T
Storage TemperatureT
VA+
VAVD
in
INA
IND
stg
-0.3
-10.5
-0.3
-±10mA
(VA-) - 0.3(VA+) + 0.3V
VD - 0.3VD + 0.3V
A
-55+125°C
-65+150°C
10.5
0.3
3.63
V
V
V
Notes:
1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS693F17
CS3318
ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): RS=0; RL=20kΩ; CL= 20 pF; 10 Hz to 20 kHz Me asu r em e nt
Bandwidth)
ParameterSymbol Min TypMaxUnit
DC Characteristics
Step Size-0.25-dB
Gain Error(Vol = +22 dB)-±0.5-dB
Gain Matching Between Channels(Vol = +22 dB)-±0.1-dB
Input ResistanceR
Input Capacitanc eC
Offset Voltage(Note 4)V
Output ResistanceR
AC Load ResistanceR
Load Capacitance--100pF
Short Circuit Current-20-mA
Unity Gain Bandwidth, Small Signal-5-MHz
OS
OUT
LOAD
Power Supplies
Supply Current (No Load, Vin = 0 V)Normal Operation
Power-Down, All Supplies (Note 5)
Power ConsumptionNormal Operation
Power Down (Note 5)
Power Supply Rejection Ratio (250 Hz)PSRR-80-dB
I
I
I
I
VA+
VAVD
PD
810-kΩ
-10-pF
(VA-) + 1.35-(VA+) - 1.35V
-0.755mV
-100-Ω
2--kΩ
-
-
-
-
-
-
36
36
0.6
60
650
540
50
50
1.07
-
904
-
mA
mA
mA
μA
mW
μW
in
=[(V
FS Max-VFS Min
3. V
Note that for (VA+) = -(VA-) = 9 V, V
)-1.6V]V
, 1 kHz, Volume = 0 dB.
p-p
=13.7V
in
p-p
=4.8V
RMS
.
4. Measured with input grounded and volume = 0 dB. Will increase as a function of volume settings >0 dB.
5. Power-down is defined as RESET
= low, all clock and data lines held static, and no analog input signals
applied.
8DS693F1
CS3318
DIGITAL INTERFACE CHARACTERISTICS
ParametersSymbol Min TypMaxUnits
High-Level Input VoltageV
Low-Level Input VoltageV
High-Level Output Voltage at Io=2 mAV
Low-Level Output Voltage at I
Input Leakage CurrentI
Input Capacitance-8-pF
=2 mAV
o
IH
IL
OH
OL
in
0.7 x VD--V
--0.2 x VDV
VD - 1.0--V
--0.4V
--±10μA
MUTE
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = DGND, Logic 1 = VD)
ParametersSymbol Min TypMaxUnits
MUTE Active Pulse Width(Note 6)-2--ms
6. The MUTE
active state (low/high) is set by the MutePolarity bit in the Device Configuration 1 register
(see page 33).
DS693F19
CONTROL PORT SWITCHING CHARACTERISTICS - I²C FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VD, CL=20pF)
Parameter SymbolMinMaxUnit
SCL Clock Frequencyf
RESET
Rising Edge to Startt
Bus Free Time Between Transmissionst
Start Condition Hold Time (prior to first clock pulse)t
Clock Low timet
Clock High Timet
Setup Time for Repeated Start Conditiont
SDA Hold Time from SCL Falling(Note 7)t
SDA Setup time to SCL Risingt
Rise Time of SCL and SDAt
Fall Time SCL and SDAt
Setup Time for Stop Conditiont
Acknowledge Delay from SCL Fallingt
scl
irs
buf
hdst
low
high
sust
hdd
sud
, t
rc
, t
fc
susp
ack
rd
fd
-100kHz
100-ns
4.7-µs
4.0-µs
4.7-µs
4.0-µs
4.7-µs
0-µs
250-ns
-1µs
-300ns
4.7-µs
3001000ns
CS3318
RESET
SDA
SCL
7. Data must be held for sufficient time to bridge the transition time, t
t
irs
StopStart
t
buf
t
hdst
t
low
t
t
high
hdd
t
sud
t
ack
Figure 1. Control Port Timing - I²C Format
, of SCL.
fc
Repeated
Start
t
sust
t
t
hdst
Stop
rd
t
t
rc
t
fd
fc
t
susp
10DS693F1
CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT
(Inputs: Logic 0 = DGN D , Logic 1 = VD, CL=20pF)
ParameterSymbol Min MaxUnit
CCLK Clock Frequencyf
RESET
Rising Edge to CS Fallingt
High Time Between Transmissionst
CS
Falling to CCLK Edget
CS
CCLK Low Timet
CCLK High Timet
CDIN to CCLK Rising Setup Timet
CCLK Rising to DATA Hold Time(Note 8)t
Rise Time of CCLK and CDIN(Note 9)t
Fall Time of CCLK and CDIN(Note 9)t
8. Data must be held for sufficient time to bridge the transition time of CCLK.
9. For f
<1 MHz.
sck
sck
srs
csh
css
scl
sch
dsu
dh
r2
f2
06.0MHz
100-ns
1.0-μs
20-ns
66-ns
66-ns
40-ns
15-ns
-100ns
-100ns
CS3318
RESET
CS
CCLK
MOSI
t
srs
t
t
sch
t
dsu
scl
t
f2
t
dh
t
css
t
r2
Figure 2. Control Port Timing - SPI Format
t
csh
DS693F111
3. TYPICAL CONNECTION DIAGRAM
CS3318
+3.3 V
Audio
Source
Host
Controller
+8 V to +9V
-8 V to -9V
See Note
2 kΩ2 kΩ
1
IN1
42
IN2
39
IN3
32
IN4
29
IN5
22
IN6
19
IN7
12
IN8
5
SCL/CCLK
6
SDA/MOSI
7
AD0/CS
3
RESET
4
MUTE
-
A
V
VA+
CS3318
VA
47
44
37
34
27
24
17
14
8
10
9
+8 V to +9V
-8 V to -9V
Audio
Outputs
To Next CS3318
+3.3 V
0.1 µF
0.1 µF 10 µF0.1 µF10 µF
36354546
-
+
VA
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
ENOut
VD
DGND
+8 V to +9V
Note:
Resistors are required for
I²C control port operation.
-8 V to -9V
2
41
40
31
30
21
20
11
REFI1
REFI2
REFI3
REFI4
REFI5
REFI6
REFI7
REFI8
VA+
VA-
VA-
REFO1
REFO2
REFO3
REFO4
REFO5
REFO6
REFO7
REFO8
VA+
15162625
0.1 µF 10 µF0.1 µF10 µF
Figure 3. Typical Connection Diagram
48
43
38
33
28
13
18
13
+8 V to +9V
-8 V to -9V
12DS693F1
4. DETAILED BLOCK DIAGRAM
CS3318
IN1
VA+
VA-
REFI1
REFI2
IN3
VA+
VA-
REFI3
REFI4
RESET
SDA/MOSI
SCL/CLLK
AD0/CS
MUTE
IN2
IN4
1
45
46
2
42
R
41
39
35
36
40
32
R
31
3
6
5
7
4
Zero Crossing Detector
0 ~ -96 dB
R
IN
Zero Crossing Detector
0 ~ -96 dB
IN
+
_
0 ~ +22 dB
Control
Control Registers
Control
Zero Crossing Detector
0 ~ -96 dB
R
IN
Zero Crossing Detector
0 ~ -96 dB
IN
+
_
0 ~ +22 dB
+
_
0 ~ +22 dB
R
Ch. 4
Ch. 3
Control
Ch. 8
Ch. 7
Control
OUT
Ch. 2
Control
Ch. 6
Control
+
_
0 ~ +22 dB
R
OUT
Ch. 1
Control
Ch. 5
Control
R
OUT
47
OUT1
48
REFO1
R
OUT
44
43
37
38
34
33
8
10
9
OUT2
REFO2
OUT3
REFO3
OUT4
REFO4
ENOut
VD
DGND
REFI5
REFI6
REFI7
REFI8
Refer to the Analog Characteristics
table on page 8 for the specified
values of R
and R
IN
OUT
.
IN5
VA+
VA-
IN6
IN7
VA+
VA-
IN8
29
25
26
30
22
R
21
19
15
16
20
12
R
11
Zero Crossing Detector
0 ~ -96 dB
R
IN
Zero Crossing Detector
0 ~ -96 dB
IN
+
_
0 ~ +22 dB
Zero Crossing Detector
0 ~ -96 dB
R
IN
Zero Crossing Detector
0 ~ -96 dB
IN
+
_
0 ~ +22 dB
+
_
0 ~ +22 dB
R
OUT
+
_
0 ~ +22 dB
R
OUT
R
OUT
27
OUT5
28
REFO5
R
OUT
24
23
17
18
14
13
OUT6
REFO6
OUT7
REFO7
OUT8
REFO8
Figure 4. Detailed Block Diagram
DS693F113
5. APPLICATIONS
5.1General Description
The CS3318 is an 8-channel digitally controlled analog volume control designed for audio systems. It incorporates a total adjustable range of 118 dB in ¼ dB steps, spread evenly over 96 dB of attenuation and
22 dB of gain.
The internal analog architecture includes one op-amp per channel, each with an input resistor network for
attenuation and a feedback resistor network for gain. Analog switch arrays are used to select taps in the
input and feedback resistor networks, thereby setting the gain or attenuation of each chan nel. These switch
arrays are controlled via the digital control port, bridging the gap between the analog and digital domains.
Figure 4 on page 13 provides a detailed diagram of the CS3318’s internal architecture.
The CS3318 incorporates highly configurable zero-crossing dete ction fo r glitch- free vol ume leve l changes.
Volume changes may be configured to occur immediately or on a signal zero-crossing. In the event tha t the
signal does not cross zero, the CS3318 provides 8 selectable time-out periods in the range of 5 ms to 50 ms
after which the volume level will be changed immediately. When the CS3318 receives more than one volume change command before a zero-crossing or a time-out, the CS3318 is able to implement the previous
volume change command immediately or discard it and act only on the most recent command. The “Zero-
Crossing Detection” section on page 22 provides a detailed description of the CS3318’s zero-crossing de-
tection functionality and controls.
CS3318
The CS3318 includes a comprehensive I²C/SPI serial control port interfac e for volume change s and device
configuration. This interface provides for easy system integration of up to 128 CS3318 devices over a single
2-wire I²C or 3-wire SPI bus, allow ing many channe ls of v olume control with minimal system controller I/O
requirements. Devices may be addressed on an individual and grouped basis, simplifying simultaneous
configuration of a group of channels across multiple devices, while allowing discrete control over all channels on an individual basis. The “System Serial Control Configuration” section on page 23 provides a detailed description of the serial control port features and functionality.
5.2System Design
Very few external components are required to su pport the CS3318. Typical powe r supply deco uplin g components are the only external requirements, as shown in Figure 3 on page 12.
5.2.1Analog Inputs
No external circuitry is required to interface between the audio source and the CS3318’s inputs. However,
as with any adjustable gain stage, the affects of a DC offset at the input must be considered. Capacitively
coupling the analog inputs may be required to prevent “clicks and pops” which occur with gain chan ges if
an appreciable offset is present.
The addition of an input coupling capacitor will form a high-pass filter with the CS3318’s input impedance.
Given nominal values of input impedance and coupling capacitor, a 10 µF coupling capacitor will result in
less than 0.03 dB of attenuation at 20 Hz. If additional low-frequency attenuation can be tolerated, a smaller coupling capacitor may be used.
The CS3318 requires a low source impedance to achieve maximum performance, and a source-impedance of 600 Ω or less is recommended.
The maximum input level is limited by the input signal swing capability of the internal op-amp. Signals approaching the analog supply voltages may be applied to the analog input pins if the internal attenuator
limits the output signal to within 1.35 V of the analog supply rails.
14DS693F1
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