Cirrus Logic CS3308 User Manual
8-Channel Analog Volume Control
CS3308
Features
Complete Analog Volume Control
– 8 Independently Controllable Channels
– 3 Configurable Master Volume and Muting
Controls
Wide Adjustable Volume Range
– -96 dB to +22 dB in ¼ dB Steps
Low Distortion & Noise
– -112 dB THD+N
– 123 dB Dynamic Range
Noise-Free Level Transitions
– Zero-Crossing Detection with
Programmable Time-Out
Low Channel-to-Channel Crosstalk
– 120 dB Inter-Channel Isolation
Comprehensive Serial Control Port
– Supports I²C
– Independent Control of up to 128 Devices
on a Shared 2-Wire I²C or 3-Wire SPI
Control Bus
– Supports Individual and Grouped Control of
all CS3308 Devices on the I²C or SPI
Control Bus
Standard Power Supply Voltages
– ±5 V Analog Supply
– +3.3 V Digital Supply
®
and SPITM Communication
Description
The CS3308 is an 8-channel digitally controlled analog
volume control designed specifically for high-end audio
systems. It features a comprehensive I²C/SPI serial
control port for easy device and volume configuration.
The CS3308 includes arrays of well-matched resistors
and complementary low-noise active output stages. A
total adjustable range of 118 dB, in ¼ dB steps, is
spread evenly over 96 dB of attenuation and 22 dB of
gain.
The CS3308 implements configurable zero-crossing
detection to provide glitch-free volume-level changes.
The I²C/SPI control interface provides for easy system
integration of up to 128 CS3308 devices over a single 2wire I²C or 3-wire SPI bus, allowing many channels of
volume control with minimal system controller I/O requirements. Devices may be controlled on an ind ividual
and grouped basis, simplifying simultaneous configuration of a group of channels across multiple devices,
while allowing discrete control over all channels on an
individual basis.
The device operates from ±5 V analog supplies and has
an input/output voltage range of ±3.65 V. The digital
control interface operates at +3.3 V.
The CS3308 is available in a 48-pin LQFP package in
Commercial grade (-10° to 70° C). The CS3308 Customer Demonstration board is also available for device
evaluation. Refer to “Ordering Information” on page 44
for complete details.
8-Channel
Analog
Inputs
I²C/SPI
Serial
Control
http://www.cirrus.com
±5 V
+3.3 V
8
I²C / SPI
Control
Port
+
_
Zero Crossing
Detector
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
8
8-Channel
Analog
Outputs
DECEMBER '06
DS702F1
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................ 5
2. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 7
SPECIFIED OPERATING CONDITIONS .................................................................................................... 7
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 7
ANALOG CHARACTERISTICS................................................................................................................... 8
DIGITAL INTERFACE CHARACTERISTICS....................................................... ... ... .... ... ... ... ... .... ... ... ... .....9
MUTE SWITCHING CHARACTERISTICS ..................................................................................................9
CONTROL PORT SWITCHING CHARACTERISTICS - I²C FORMAT...................................................... 10
CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT ................................................. 11
3. TYPICAL CONNECTION DIAGRAM ................................................................................................. 12
4. DETAILED BLOCK DIAGRAM .......................................................................................................... 13
5. APPLICATIONS ................................................................................................................................. 14
5.1 General Description ..................................................................................................................... 14
5.2 System Design ............................................................................................................................ 14
5.2.1 Analog Inputs .................................................................................................................... 14
5.2.2 Analog Outputs .................................................................................................................. 15
5.2.3 Recommended Layout, Grounding, and Power Supply Decoupling ................................. 15
5.3 Power-Up and Power-Down ........................................................................................................ 15
5.3.1 Recommended Power-Up Sequence ................................... .... ... ... ... .... ... ... ... ... .... ............ 16
5.3.2 Recommended Power-Down Sequence ..................................................... ... ... ................ 16
5.4 Volume & Muting Control Architecture ........................................................................................17
5.4.1 Control Mapping Matrix ..................................................................................................... 17
5.4.2 Volume & Muting Control Implementation ......................................................................... 18
5.5 Volume Controls .......................................................................................................................... 19
5.5.1 Individual Channel Volume Controls ........... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ......................... 19
5.5.2 Master Volume Controls ....................................................................................................19
5.5.3 Volume Limits .................................................................................................................... 20
5.6 Muting Controls ........................................................................................................................... 21
5.6.1 Individual Channel Mute Controls ..................................................................................... 21
5.6.2 Master Mute Controls ........................................................................................................ 21
5.6.3 Hardware Mute Control ..................................................................................................... 21
5.7 Zero-Crossing Detection .............................................................................................................. 22
5.7.1 Zero-Crossing Modes ........................................................................................................ 22
5.7.2 Zero-Crossing Time-Out .................................................................................................... 22
5.8 System Serial Control Configuration ...........................................................................................23
5.8.1 Serial Control within a Single-CS3308 System ................................................................. 23
5.8.2 Serial Control within a Multiple-CS3308 System ............ .......................................... ......... 24
5.8.2.1 SPI Mode Serial Control Configuration................ .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 24
5.8.2.2 I²C Mode Control Configuration ..................................................................................................... 26
5.9 I²C/SPI Serial Control Formats .................................................................................................... 27
5.9.1 I²C Mode ............................................................................................................................ 27
5.9.2 SPI Mode .............................. ............................................................................................. 28
6. CS3308 REGISTER QUICK REFERENCE ........................................................................................ 29
7. CS3308 REGISTER DESCRIPTIONS ................................................................................................ 31
7.1 Ch 1-8 Volume - Addresses 01h - 08h ..... ...................................................................................31
7.1.1 Volume Control (Bits 7:0) .................................................................................................. 31
7.2 ¼ dB Control - Address 09h ........................................................................................................ 32
7.2.1 ¼ dB Control (Bit 0 - 7) ...................................................................................................... 32
7.3 Mute Control - Address 0Ah ........................................................................................................ 33
7.3.1 Mute Channel X (Bit 0 - 7) . ... ... ... .... .......................................... ... ... ... .... ... ......................... 33
7.4 Device Configuration 1 - Address 0Bh (Bit 5) ........................................................ ... ... .... ... ... ... ...33
7.4.1 Enable MUTE Input (Bit 5) ..............................................................................................
CS3308
.. 33
2 DS702F1
CS3308
7.4.2 MUTE Input Polarity (Bit 4) ................................................................................................ 33
7.4.3 Channel B = Channel A (Bit 0 - 3) ..................................................................................... 34
7.5 Device Configuration 2 - Address 0Ch ........................................................................................ 34
7.5.1 Zero-Crossing Time-Out Period (Bits 4:2) ......................................................................... 34
7.5.2 Zero-Crossing Mode (Bits 1:0) .......................................................................................... 35
7.6 Channel Power - Address 0Dh ....................... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ...................... 35
7.6.1 Power Down Channel X (Bit 0 - 7) .................................................................................... 35
7.7 Master Power - Address 0Eh ....................................................................................................... 35
7.7.1 Power Down All (Bit 0) ...................................................................................................... 35
7.8 Freeze Control - Address 0Fh ............................................... ... ... ... .... ... ... ... .... ... ......................... 36
7.8.1 Freeze (Bit 7) ..................................................................................................................... 36
7.9 Master 1 Mask - Address 10h ...................................................................................................... 36
7.10 Master 1 Volume - Address 11h ................................................................................................ 36
7.10.1 Master 1 Volume Control (Bits 7:0) ................................................................................. 36
7.11 Master 1 Control - Address 12h ................................................................................................. 37
7.11.1 Master 1 Mute (Bit 1) ....................................................................................................... 37
7.11.2 Master 1 ¼ dB Control (Bit 0) .......................................................................................... 37
7.12 Master 2 Mask - Address 13h .................................................................................................... 37
7.13 Master 2 Volume - Address 14h ................................................................................................ 37
7.13.1 Master 2 Volume Control (Bits 7:0) ................................................................................. 37
7.14 Master 2 Control - Address 15h ................................................................................................. 38
7.14.1 Master 2 Mute (Bit 1) ....................................................................................................... 38
7.14.2 Master 2 ¼ dB Control (Bit 0) .......................................................................................... 38
7.15 Master 3 Mask - Address 16h .................................................................................................... 38
7.16 Master 3 Volume - Address 17h ................................................................................................ 38
7.16.1 Master 3 Volume Control (Bits 7:0) ................................................................................. 38
7.17 Master 3 Control - Address 18h ................................................................................................. 39
7.17.1 Master 3 Mute (Bit 1) ....................................................................................................... 39
7.17.2 Master 3 ¼ dB Control (Bit 0) .......................................................................................... 39
7.18 Group 2 Chip Address 19h ........................................................................................................ 40
7.18.1 Group 2 Chip Address (Bits 7:1) ..................................................................................... 40
7.18.2 Enable Group 2 Address (Bit 0) ................................................................................ ...... 40
7.19 Group 1 Chip Address 1Ah ........................................................................................................ 40
7.19.1 Group 1 Chip Address (Bits 7:1) ..................................................................................... 40
7.19.2 Enable Group 1 Address (Bit 0) ................................................................................ ...... 40
7.20 Individual Chip Address 1Bh ..................................................................................................... 41
7.20.1 Individual Chip Address (Bits 7:1) ................................................................................... 41
7.20.2 Enable Next Device (Bit 0) .............................................................................................. 41
7.21 Chip ID - Address 1Ch ............................................................................................................... 41
7.21.1 Chip ID (Bits 7:4) ............................................................................................................. 41
7.21.2 Chip Revision (Bits 3:0) ................................................................................................... 41
8. PARAMETER DEFINITIONS .............................................................................................................. 42
9. PACKAGE DIMENSIONS .................................................................................................................. 43
10. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 43
11. ORDERING INFORMATION ................. ... ... .... ... ... ... .......................................... .... ... ... ... ... .... ... ......... 44
12. REVISION HISTORY ................................ ... .... ... .......................................... ... ... .... ... ......................... 44
DS702F1 3
LIST OF FIGURES
Figure 1.Control Port Timing - I²C Format........................ .... ... ... ... .... ......................................................... 10
Figure 2.Control Port Timing - SPI Format........................... ... ... ... .... ... ... ... ... .... ......................................... 11
Figure 3.Typical Connection Diagram........................................................................................................ 12
Figure 4.Detailed Block Diagram ............................................................................................................... 13
Figure 5.CS3308 Control Mapping Matrix.................................. ... .... ... ... ... ... .... ... ... ... .... ... ......................... 17
Figure 6.Volume & Muting Control Implementation ................................................................................... 18
Figure 7.Standard I²C Connections............................................................................................................ 23
Figure 8.Standard SPI Connections........................ ... ... ... .... ... ... ... .... ... ... ................................................... 23
Figure 9.SPI Serial Control Connections ................................................................................................... 24
Figure 10.Individual Device Address Configuration Process ..................................................................... 25
Figure 11.I²C Serial Control Connections .................................................................................................. 26
Figure 12.Control Port Timing, I²C Write.................................................................................................... 27
Figure 13.Control Port Timing, I²C Read.................................................................................................... 28
Figure 14.SPI Write Cycle.......................................................................................................................... 28
LIST OF TABLES
Table 1. Example Volume Settings............................................................................................................ 20
Table 2. Zero-Crossing Modes................................................................................................................... 22
Table 3. Zero-Crossing Time-Out Periods................................................................................................. 22
Table 4. I²C Mode Default Chip Address ................................................................................ ... .... ............ 27
Table 5. Example Volume Settings............................................................................................................ 31
Table 6. Example Volume Settings............................................................................................................ 32
Table 7. Channel B = Channel A Settings ................................................................................................. 34
Table 8. Zero-Crossing Time-Out Settings ................................................................................................ 34
Table 9. Zero-Crossing Mode Settings ...................................................................................................... 35
Table 10. Chip Revision Register Codes................................................................................................ ... 41
CS3308
4 DS702F1
1. PIN DESCRIPTIONS
REFI1
RESET
MUTE
SCL/CCLK
SDA/MOSI
AD0/CS
ENOut
DGND
VD
REFI8
IN8
OUT1
VA-
VA+
OUT2
REFO2
IN2
REFO1
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
CS3308
REFI2
CS3308
REFI3
IN3
REFO3
OUT3
VA-IN1
36
VA+
35
OUT4
34
REFO4
33
IN4
32
REFI4
31
REFI5
30
IN5
29
REFO5
28
OUT5
27
VA-
26
VA+
25
Pin Name # Pin Description
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
1
42
39
32
Analog Inputs (Input) - The full-scale level is specified in the Analog Characteristics specification
table.
29
22
19
12
13 14 15 16 17 18 19 20 21 22 23 24
OUT8
REFO8
OUT7
VA-
VA+
IN7
REF07
REFI7
REFI6
IN6
REFO6
OUT6
DS702F1 5
CS3308
Pin Name # Pin Description
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
REFI1
REFI2
REFI3
REFI4
REFI5
REFI6
REFI7
REFI8
REFO1
REFO2
REFO3
REFO4
REFO5
REFO6
REFO7
REFO8
VA+
VA-
RESET
MUTE
SCL/CCLK 5 Serial Control Port Clock (Input) - Serial clock for the serial control port.
SDA/MOSI 6
AD0/CS
ENOut 8 Enable Output (Output) - Enable output signal for multi-device serial control chain configuration.
DGND 9 Digital Ground (Input) - Ground reference for the internal digital section.
VD 10 Digital Power (Input) - Positive power for the internal digital section.
47
44
37
34
Analog Outputs (Output) - The full-scale output level is specified in the Analog Characteristics specifi-
cation table.
27
24
17
14
2
41
40
31
Reference In (Input) - Analog reference pin.
30
21
20
11
48
43
38
33
Reference Out (Output) - Analog reference pin.
28
23
18
13
15,
25,
Positive Analog Power (Input) - Positive power for the internal analog section.
35,
45
16,
26,
Negative Analog Power (Input) - Negative power for the internal analog section.
36,
46
3 Reset (Input) - The device enters a low-power mode when this pin is driven low.
Mute (Input) - This pin defaults to an active low mute input, and may be configured as an active high
4
mute input.
Serial Control Data (Input/Output) - SDA is a data I/O line for the control port interface in I²C Mode.
MOSI is the input data line for the control port interface in SPI Mode.
Default Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 sets the LSB of the default
7
chip address in I²C Mode. CS
is the chip-select signal for SPI format.
6 DS702F1
CS3308
2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and T
= 25°C.
A
SPECIFIED OPERATING CONDITIONS
(DGND = 0 V; All voltages with respect to ground.)
Parameters Symbol Min Nom Max Units
DC Power Supplies: Positive Analog
Negative Analog
Digital
Ambient Operating Te mperature (Power Applied) T
VA+
VA-
VD
4.75
-5.25
3.1
A
-10 - +70 °C
5
-5
3.3
5.25
-4.75
3.5
V
V
V
ABSOLUTE MAXIMUM RATINGS
(DGND = 0 V; All voltages with respect to ground. (Note 1)
Parameter Symbol Min Max Units
DC Power Supplies: Positive Analog
Negative Analog
Digital
Input Current (Note 2) I
Analog Input Voltage V
Digital Input Voltage V
Ambient Operating Te mperature (Power Applied) T
Storage Temperature T
VA+
VA-
VD
in
INA
IND
stg
-0.3
-7.0
-0.3
- ±10 mA
(VA-) - 0.3 (VA+) + 0.3 V
VD - 0.3 VD + 0.3 V
A
-55 +125 °C
-65 +150 °C
7.0
0.3
3.63
V
V
V
Notes:
1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS702F1 7
CS3308
ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): RS=0; RL=2kΩ; CL= 20 pF; 10 Hz to 20 kHz Measurement Bandwidth)
Parameter Symbol Min Typ Max Unit
DC Characteristics
Step Size -0.25-dB
Gain Error (Vol = +22 dB) - ±0.5 - dB
Gain Matching Between Channels (Vol = +22 dB) - ±0.1 - dB
Input Resistance R
Input Capacitanc e C
IN
IN
AC Characteristics
Total Harmonic Distortion + Noise (Note 3) THD+N - 0.00025 0.00063 %
Dynamic Range 117 123 - dB
Input/Output Voltage Range (THD+N < 1 %) V
Output Noise (Note 4) -1.83.6μVrms
Interchannel Isolation (1 kHz) - -120 - dB
FS
Output Buffer
Offset Voltage (Note 4) V
Output Resistance R
AC Load Resistance R
Load Capacitance - - 100 pF
Short Circuit Current - 20 - mA
Unity Gain Bandwidth, Small Signal - 5 - MHz
OS
OUT
LOAD
Power Supplies
Supply Current (No Load, Vin = 0 V) Normal Operation
Power-Down, All Supplies (Note 5)
Power Consumption Normal Operation
Power Down (Note 5)
Power Supply Rejection Ratio (250 Hz) PSRR - 80 - dB
I
I
I
I
VA+
VAVD
PD
810-kΩ
-10-pF
(VA-) + 1.35 - (VA+) - 1.35 V
-0.755mV
-100-Ω
2--kΩ
-
-
-
-
-
-
36
36
0.6
60
362
300
50
50
1.07
-
500
-
mA
mA
mA
μA
mW
μW
in
=[(V
FS Max-VFS Min
3. V
Note that for (VA+) = -(VA-) = 5 V, V
)-1.6V]V
, 1 kHz, Volume = 0 dB.
p-p
=5.7V
in
p-p
=2V
RMS
.
4. Measured with input grounded and volume = 0 dB. Will increase as a function of volume settings >0 dB.
5. Power-down is defined as RESET
= low, all clock and data lines held static, and no analog input signals
applied.
8 DS702F1
CS3308
DIGITAL INTERFACE CHARACTERISTICS
Parameters Symbol Min Typ Max Units
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage at Io=2 mA V
Low-Level Output Voltage at I
Input Leakage Current I
Input Capacitance - 8 - pF
=2 mA V
o
IH
IL
OH
OL
in
0.7 x VD - - V
- - 0.2 x VD V
VD - 1.0 - - V
--0.4V
--±10μA
MUTE
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = DGND, Logic 1 = VD)
Parameters Symbol Min Typ Max Units
MUTE Active Pulse Width (Note 6) -2--ms
6. The MUTE
active state (low/high) is set by the MutePolarity bit in the Device Configuration 1 register
(see page 33).
DS702F1 9
CONTROL PORT SWITCHING CHARACTERISTICS - I²C FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VD, CL=20pF)
Parameter Symbol Min Max Unit
SCL Clock Frequency f
RESET
Rising Edge to Start t
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 7) t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling t
buf
hdst
low
high
sust
hdd
sud
rc
fc
susp
ack
scl
irs
, t
, t
rd
fd
- 100 kHz
100 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
300 1000 ns
CS3308
RESET
SDA
SCL
7. Data must be held for sufficient time to bridge the transition time, t
t
irs
Stop Start
t
buf
t
hdst
t
low
t
t
high
hdd
t
sud
t
ack
Figure 1. Control Port Timing - I²C Format
, of SCL.
fc
Repeated
Start
t
sust
t
t
hdst
Stop
rd
t
t
rc
t
fd
fc
t
susp
10 DS702F1
CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VD, CL=20pF)
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
RESET
Rising Edge to CS Falling t
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CS
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 8) t
Rise Time of CCLK and CDIN (Note 9) t
Fall Time of CCLK and CDIN (Note 9) t
8. Data must be held for sufficient time to bridge the transition time of CCLK.
9. For f
<1 MHz.
sck
sck
srs
csh
css
scl
sch
dsu
dh
r2
f2
06.0MHz
100 - ns
1.0 - μs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
- 100 ns
- 100 ns
CS3308
RESET
CS
CCLK
MOSI
t
srs
t
t
sch
t
dsu
scl
t
f2
t
dh
t
css
t
r2
Figure 2. Control Port Timing - SPI Format
t
csh
DS702F1 11
3. TYPICAL CONNECTION DIAGRAM
CS3308
+3.3 V
Audio
Source
Host
Controller
+5 V
-5 V
See Note
2 kΩ2 kΩ
1
IN1
42
IN2
39
IN3
32
IN4
29
IN5
22
IN6
19
IN7
12
IN8
5
SCL/CCLK
6
SDA/MOSI
7
AD0/CS
3
RESET
4
MUTE
-
VA
VA+
CS3308
VA+
36354546
VA
-
0.1 µF 10 µF0.1 µF10 µF
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
ENOut
DGND
VD
+5 V
-5 V
47
44
37
34
27
24
17
14
8
+3.3 V
10
9
Audio
Outputs
To Next CS3308
0.1 µF
Note:
Resistors are required for
I²C control port operation.
+5 V
-5 V
2
41
40
31
30
21
20
11
REFI1
REFI2
REFI3
REFI4
REFI5
REFI6
REFI7
REFI8
A+
VA-
V
VA-
REFO1
REFO2
REFO3
REFO4
REFO5
REFO6
REFO7
REFO8
VA+
15162625
0.1 µF 10 µF0.1 µF10 µF
Figure 3. Typical Connection Diagram
48
43
38
33
28
13
18
13
+5 V
-5 V
12 DS702F1
4. DETAILED BLOCK DIAGRAM
CS3308
IN1
VA+
VA-
REFI1
REFI2
IN3
VA+
VA-
REFI3
REFI4
RESET
SDA/MOSI
SCL/CLLK
AD0/CS
MUTE
IN2
IN4
1
45
46
2
42
41
39
35
36
40
32
R
31
3
6
5
7
4
Zero Crossing Detector
0 ~ -96 dB
R
IN
Zero Crossing Detector
0 ~ -96 dB
IN
+
_
0 ~ +22 dB
Control
Control Registers
Control
Zero Crossing Detector
0 ~ -96 dB
R
IN
Zero Crossing Detector
0 ~ -96 dB
R
IN
0 ~ +22 dB
+
_
0 ~ +22 dB
Ch. 4
Ch. 3
Control
Ch. 8
Ch. 7
Control
+
_
R
OUT
Ch. 2
Control
Ch. 6
Control
+
_
0 ~ +22 dB
R
OUT
Ch. 1
Control
Ch. 5
Control
R
OUT
47
OUT1
48
REFO1
R
OUT
44
43
37
38
34
33
8
10
9
OUT2
REFO2
OUT3
REFO3
OUT4
REFO4
ENOut
VD
DGND
REFI5
REFI6
REFI7
REFI8
Refer to the Analog Characteristics
table on page 8 for the specified
values of R
and R
IN
OUT
.
IN5
VA+
VA-
IN6
IN7
VA+
VA-
IN8
29
25
26
30
22
R
21
19
15
16
20
12
R
11
Zero Crossing Detector
0 ~ -96 dB
R
IN
Zero Crossing Detector
0 ~ -96 dB
IN
+
_
0 ~ +22 dB
Zero Crossing Detector
0 ~ -96 dB
R
IN
Zero Crossing Detector
0 ~ -96 dB
IN
+
_
0 ~ +22 dB
+
_
0 ~ +22 dB
R
OUT
+
_
0 ~ +22 dB
R
OUT
R
OUT
27
OUT5
28
REFO5
R
OUT
24
23
17
18
14
13
OUT6
REFO6
OUT7
REFO7
OUT8
REFO8
Figure 4. Detailed Block Diagram
DS702F1 13
5. APPLICATIONS
5.1 General Description
The CS3308 is an 8-channel digitally controlled analog volume control designed for audio systems. It incorporates a total adjustable range of 118 dB in ¼ dB steps, spread evenly over 96 dB of attenuation and
22 dB of gain.
The internal analog architecture includes one op-amp per channel, each with an input resistor network for
attenuation and a feedback resistor network for gain. Analog switch arrays are used to select taps in the
input and feedback resistor networks, thereby setting the gain or attenuation of each chan nel. These switch
arrays are controlled via the digital control port, bridging the gap between the analog and digital domains.
Figure 4 on page 13 provides a detailed diagram of the CS3308’s internal architecture.
The CS3308 incorporates highly configurable zero-crossing dete ction fo r glitch- free vol ume leve l changes.
Volume changes may be configured to occur immediately or on a signal zero-crossing. In the event tha t the
signal does not cross zero, the CS3308 provides 8 selectable time-out periods in the range of 5 ms to 50 ms
after which the volume level will be changed immediately. When the CS3308 receives more than one volume change command before a zero-crossing or a time-out, the CS3308 is able to implement the previous
volume change command immediately or discard it and act only on the most recent command. The “Zero-
Crossing Detection” section on page 22 provides a detailed description of the CS3308’s zero-crossing de-
tection functionality and controls.
CS3308
The CS3308 includes a comprehensive I²C/SPI serial control port interfac e for volume change s and device
configuration. This interface provides for easy system integration of up to 128 CS3308 devices over a single
2-wire I²C or 3-wire SPI bus, allow ing many channe ls of v olume control with minimal system controller I/O
requirements. Devices may be addressed on an individual and grouped basis, simplifying simultaneous
configuration of a group of channels across multiple devices, while allowing discrete control over all channels on an individual basis. The “System Serial Control Configuration” section on page 23 provides a detailed description of the serial control port features and functionality.
5.2 System Design
Very few external components are required to su pport the CS3308. Typical powe r supply deco uplin g components are the only external requirements, as shown in Figure 3 on page 12.
5.2.1 Analog Inputs
No external circuitry is required to interface between the audio source and the CS3308’s inputs. However,
as with any adjustable gain stage, the affects of a DC offset at the input must be considered. Capacitively
coupling the analog inputs may be required to prevent “clicks and pops” which occur with gain chan ges if
an appreciable offset is present.
The addition of an input coupling capacitor will form a high-pass filter with the CS3308’s input impedance.
Given nominal values of input impedance and coupling capacitor, a 10 µF coupling capacitor will result in
less than 0.03 dB of attenuation at 20 Hz. If additional low-frequency attenuation can be tolerated, a smaller coupling capacitor may be used.
The CS3308 requires a low source impedance to achieve maximum performance, and a source-impedance of 600 Ω or less is recommended.
The maximum input level is limited by the input signal swing capability of the internal op-amp. Signals approaching the analog supply voltages may be applied to the analog input pins if the internal attenuator
limits the output signal to within 1.35 V of the analog supply rails.
14 DS702F1
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