CS3001
CS3002
Precision Low Voltage Amplifier; DC to 2 kHz
Features
Low Offset: 10 µVMax
Low Drift: 0.05 µV/°C Max
Low Noise
–6nV/√Hz @0.5Hz
– 0.1 to 10 Hz = 125 nVp-p
– 1/f corner @ 0.08 Hz
Open-Loop Voltage Gain
– 1000 Trillion Typ
– 10 Billion Min
Rail-to-Rail Output Swing
1.8 mA Supply Current
Slew rate: 5 V/µs
Applications
Thermocouple/Thermopile Amplifiers
Load Cell and Bridge Transducer Amplifiers
Precision Instrumentation
Battery-Powered Systems
Description
The CS3001 single amplifier and the CS3002 dual amplifier are designed for precision amplification of low
level signals and are ideally suited to applications that
require very high closed loop gains. These amplifiers
achieve excellent offset stability, super high open loop
gain, and low noise over time and temperature. The devices also exhibit excellent CMRR and PSRR. The
common mode input range includes the negative supply
rail. The amplifiers operate with any total supply voltage
from 2.7 V to 6.7 V (±1.35 V to ±3.35 V).
Pin Configurations
PWDN
-In
+In
V-
CS3001
1
-
2
+
3
4
8-lead SOIC
8
7
6
5
NC
V+
Output
NC
Out A
-In A
+In A
CS3002
1
2
3
V-
4
8-lead SOIC
8
V+
A
+
-
7
Out B
B
6
+
-In B
-
5
+In B
Noise vs. Frequency (Measured)
100
10
nV/√Hz
1
0.001 0.01 0.1 1 10
Frequency (Hz)
Preliminary Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
CS3001
Dexter Research
Thermopile 1M
R2
64.9k
R1
100
Thermopile Amplifier with a Gain of 650 V/V
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrus Logic, Inc. 2002
(All Rights Reserved)
0.015
C1
µµµµF
OCT ‘02
DS490PP1
1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ................................................... 3
1.1 Electrical Characteristics ...................................................................................... 3
1.2 Absolute Maximum Ratings ................................................................................. 4
2. PERFORMANCE PLOTS ......................................................................................... 4
3. CS3001/CS3002 OVERVIEW ................................................................................... 7
3.1 Open Loop Gain and Phase Response .................................................................. 7
3.2 Open Loop Gain and Stability Compensation ...................................................... 8
3.3 Powerdown (PDWN) ......................................................................................... 10
3.4 Applications ........................................................................................................ 11
4. PACKAGE DRAWING ........................................................................................... 13
5. ORDERING INFORMATION ............................................................................... 14
LIST OF FIGURES
Figure 1. Noise vs Frequency (Measured) .........................................................................4
Figure 2. 0.01 Hz to 10 Hz Noise .......................................................................................4
Figure 3. Noise vs Frequency ............................................................................................4
Figure 4. Offset Voltage Stability (DC to 3.2 Hz) ...............................................................4
Figure 5. Open Loop Gain and Phase vs Frequency .........................................................5
Figure 6. Open Loop Gain and Phase vs Frequency (Expanded) .....................................5
Figure 7. Input Bias Current vs Supply Voltage (CS3002) .................................................6
Figure 8. Input Bias Current vs Common Mode Voltage ...................................................6
Figure 9. CS3001/CS3002 Open Loop Gain and Phase Response ..................................7
Figure 10. Non-Inverting Gain Configuration .....................................................................8
Figure 11. Non-Inverting Gain Configuration with Compensation ......................................9
Figure 12. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation ......................10
Figure 13. Thermopile Amplifier with a Gain of 650 V/V ..................................................11
Figure 14. Load Cell Bridge Amplifier and A/D Converter ...............................................12
CS3001
CS3002
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to <http://www.cirrus.com/corporate/contacts/sales.cfm>
IMPORTANT NOTICE
"Preliminary" pr oduct in formation describes products that are in production, but for which full characterization data is not yet available. "Advance" product inf ormation describes products that are in development an d subject to development changes. Cirrus Logic, I nc. and its subsidiaries ("Cirr us") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provi ded "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale suppl ied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus f or the use of thi s information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property ri ghts. Cirrus owns the copyrights of the information contained herein and gi ves consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated ci rcuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertisi ng or promotional purposes, or for creating any work for resale.
An export permit needs to be obtai ned from the competent authorities of the Japanese Government if any of the products or technologies described in thismaterial and controlled under the "Foreign Exchange and Foreign Trade Law" i s to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this materi al is subject to the PRC Foreign
Trade Law and i s to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL I NJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Ci rrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and pr oduct names in this document may be trademarks or service marks of their respective owners.
2
CS3001
CS3002
1. CHARACTERISTICS AND SPECIFICATIONS
1.1 Electrical Characteristics
V+=+5V,V-=0V,VCM=2.5V
Input Offset Voltage (Note 2) • --±10 µV
Average Input Offset Drift (Note 2) • -±0.01±0.05 µV/ºC
Long Term Input Offset Voltage Stability (Note 3)
Input Bias Current T
Input Offset Current T
Input Noise Voltage Density R
Input Noise Voltage 0.1 to 10 Hz - 125 nV
Input Noise Current Density f0=1Hz - 2
(Note 1)
Parameter
= 100 Ω,f0=1Hz
S
R
= 100 Ω,f0=1kHz
S
=25ºC
A
=25ºC
A
CS3001/CS3002
UnitMin Typ Max
- ±100 ±200
•
±1000
- ±200 ±400
•
-
-
6
6
±2000
pA
pA
pA
pA
nV/ Hz
nV/ Hz
p-p
pA/ Hz
Input Noise Current 0.1 to 10 Hz - 40 pA
p-p
Input Common Mode Voltage Range • -0.1 - (V+)-1.25 V
Common Mode Rejection Ratio (dc) (Note 4) • 115 120 - dB
Power Supply Rejection Ratio • 120 136 - dB
Large Signal Voltage Gain R
Output Voltage Swing R
Slew Rate R
=2kΩ to V+/2 (Note 5) • 200 300 - dB
L
=2kΩ to V+/2
L
R
= 100 kΩ to V+/2
L
= 2 k, 100 pF 5 - V/µs
L
• +4.7 +4.99
-V
V
Overload Recovery Time - 100 - µs
Supply Current per Amplifier
PWDN
PWDN
Threshold (Note 6)
active (CS3001 Only) (Note 6)••
• (V+) -1.0 - - V
-1.82.415mA
µA
Start-up Time (Note 7) • -912 ms
Notes: 1. Symbol “•” denotes specification applies over -40 to +85
° C.
2. This parameter is guaranteed by design and laboratory characterization. Thermocouple effects prohibit
accurate measurement of these parameters in automatic test systems.
3. 1000-hour life test data @ 125 °C indicates randomly distributed variation approximately equal to
measurement repeatability of 1 µV.
4. Measured within the specified common mode range limits.
5. Guaranteed within the output limits of (V+ -0.3 V) to (V- +0.3 V). Tested with proprietary production test
method.
6. PWDN
current consumption when PWDN
input has an internal pullup resistor to V+ of approximately 800 kΩ and is the major source of
is active low.
7. The device has a controlled start-up behavior due to its complex open loop gain characteristics. Startup time applies when supply voltage is applied or when PDWN
is released.
3
CS3001
0
0
5
0
0
5
0
0
0
CS3002
1.2 Absolute Maximum Ratings
Parameter Min Typ Max Unit
Supply Voltage [(V+) - (V-)] 6.8 V
Input Voltage V- -0.3 V+ +0.3 V
Storage Temperature Range -65 +150 ºC
2. PERFORMANCE PLOTS
Noise vs. Frequency (Measured)
100
10
nV/√Hz
1
0.001 0.01 0.1 1 10
Frequency (Hz)
Figure 1. Noise vs Frequency (Measured)
0
1
34 5
2
TIM E (Se c)
6
78
9
10
1000
100
10
1
10 100 1K 10K 100K 1M 10M
Frequency (Hz)
Figure 3. Noise vs Frequency
100
75
50
25
0
nV
-25
-50
-75
-100
Time (1 Hour)
= 13 nVσ
Figure 2. 0.01 Hz to 10 Hz Noise
Figure 4. Offset Voltage Stability (DC to 3.2 Hz)
4
Performance Plots (Cont.)
M
500
400
300
200
100
0
-100
Gain (dB)
-200
Phase (Degrees)
-300
-400
-500
1 10 100 1K 10K 100K 1M 10M
CS3001
CS3002
Gain
Phase
Frequency (Hz)
Figure 5. Open Loop Gain and Phase vs Frequency
100
80
60
40
Gain (dB)
20
0
-45
-90
-135
-180
-225
-270
Phase (Degrees)
-315
-360
10K
100K
1M
10
Figure 6. Open Loop Gain and Phase vs Frequency (Expanded)
5
Performance Plots (Cont.)
-150
-100
-50
0
-50
A1A1+
B1-
A2+
B1+
A2-
CS3001
CS3002
-100
Input Bias Current (pA)
-150
-200
Figure 7. Input Bias Current vs Supply Voltage (CS3002)
±1.35
CM = 0 V
±2
Supply Voltage (±V)
±2.5 ±3.35
3
2
1
0
-1
-2
-3
012345
Bias Current
Normalized to CM = 2.5 V
Common Mode Voltage (Vs = 5V)
B2B2+
Figure 8. Input Bias Current vs Common Mode Voltage
6
CS3001
CS3002
3. CS3001/CS3002 OVERVIEW
The CS3001/CS3002 amplifiers are designed for
precision measurement of signals from DC to
2 kHz when operating from a supply voltage of
+2.7 V to +6.7 V (± 1.35 to ± 3.35 V). The ampli-
fiers are designed with a patented architecture that
utilizes multiple amplifier stages to yield very high
open loop gain at frequencies of 10 kHz and below.
The amplifiers yield low noise and low offset drift
while consuming relatively low supply current. An
increase in noise floor above 2 kHz is the result of
intermediate stages of the amplifier being operated
at very low currents. The amplifiers are intended
for amplifying small signals with large gains in applications where the output of the amplifier can be
band-limited to frequencies below 2 kHz.
3.1 Open Loop Gain and Phase Response
Figure 9 illustrates the open loop gain and phase re-
sponse of the CS3001/CS3002. The gain slope of
the amplifier is about –100 dB/decade between
500 Hz and 60 kHz and transitions to –20 dB/decade between 60 kHz and its unity gain crossover
frequency at about 4.8 MHz. Phase margin at unity
gain is about 70 degrees; gain margin is about
20 dB.
100
80
60
40
Gain (dB)
20
0
-45
-90
-135
-180
-225
-270
Phase (Degrees)
-315
-100 dB/ dec
-20 dB/ dec
-360
10K
Figure 9. CS3001/CS3002 Open Loop Gain and Phase Response
100K
1M
10M
7
CS3001
CS3002
3.2 Open Loop Gain and Stability Compensation
The CS3001 and CS3002 achieve ultra-high open
loop gain. Figure 10 illustrates the amplifier in a
non-inverting gain configuration. The open loop
gain and phase plots indicate that the amplifier is
stable for closed-loop gains less than 50 V/V. For a
gain of 50, the phase margin is between 40° and 60°
depending upon the loading conditions. As shown
in Figure 11 on page 9, the op amp has an input capacitance at the + and – signal inputs of typically
50 pF. This capacitance adds an additional pole in
the loop gain transfer function at a frequency of
f=1/(2πR*C
) where R is the parallel combina-
in
tionofR1andR2(R1 || R2). A higher value for R
produces a pole at a lower frequency, thus reducing
the phase margin. R1 is recommended to be less
than or equal to 100 ohms, which results in a pole
at 30 MHz or higher. If a higher value of R1 is desired, a compensation capacitor (C2) should be
added in parallel with R2. C2 should be chosen
such that R2*C2 ≥ R1*Cin.
R
Vin
S
R2
R1
Figure 10. Non-Inverting Gain Configuration
Vo
8
Vin
CS3001
CS3002
C
in
50 pF
Vo
50 pF
C
in
R2
R1
C2
Figure 11. Non-Inverting Gain Configuration with Compensation
The feedback capacitor C2 is required for closedloop gains greater than 50 V/V. The capacitor introduces a pole and a zero in the loop gain transfer
function,
s
-----+
–
1
z
1
---------- -------------
T
=
P
1
Z
1
A
ol
s
1
-----+
p
1
1
------------ ------------- ------------
||
2π R
()C
1R2
1
---------- ------------- ------------=whereA
2π AR
×()C
1
2
1
---------- ------------- --
≅=forR
2π R
()
2
1C2
»
2R1
R
2
------=
R
1
Choose C2 so that R2C 2
≥
R1C
in
This indicates that the separation of the pole and
the zero is governed by the closed loop gain. It is
required that the zero falls on the steep slope
(–100 dB/decade) of the loop gain plot so that there
is some gain higher than 0 dB (typically 20 dB) at
the hand-over frequency (the frequency at which
the slope changes from – 100 dB/decade to
–20 dB/decade).
9
CS3001
CS3002
TheloopgainplotshowninFigure 12 illustrates
the unity gain configuration, and indicates how this
is modified when using the amplifier in a higher
gain configuration with compensation. If it is configured for higher gain, for example, 60 dB, the
x–axis will move up by 60 dB (line B). Capacitor
C2 adds a zero and a pole. The modified plot indicates the effects of introducing the pole and zero
due to capacitor C2. The pole can be located at any
frequency higher than the hand-over frequency, the
zero has to be at a frequency lower than the handover frequency so as to provide adequate gain margin. The separation between the pole and the zero
is governed by the closed loop gain. The zero (z
1
occurs at the intersection of the –100 dB/decade
and –80 dB/decade slopes. The point X in the figure should be at closed loop gain plus 20 dB gain
margin. The value for C2 = 1/(2πR1p1). Using
p1 = 1 MHz works very well and is independent of
gain. As the closed loop gain is changed, the zero
location is also modified if R1 remains fixed.
Capacitor C2 can be increased in value to limit the
amplifier’s rising noise above 2 kHz.
3.3 Powerdown (PDWN)
The CS3001 single amplifier provides a powerdown function on pin 1. If this pin is left open the
amplifier will operate normally. If the powerdown
is asserted low, the amplifier will go into a low
power state. There is a pull-up resistor (approximately 800 k ohm) inside the amplifier from pin
1 to the V+ supply. The current through this pull-up
resistor is the main source of current drain in the
powerdown state.
)
3.4 Applications
The CS3001 and CS3002 amplifiers are optimum
for applications that require high gain and low drift.
Figure 13 illustrates a thermopile amplifier with a
gain of 650 V/V. The thermopile outputs only a few
millivolts when subjected to infrared radiation. The
amplifier is compensated and bandlimited by C1 in
combination with R2.
10
-100 dB/dec
z
1
p
|T| (Log gain)
-20 dB/dec
FREQUENCY
Figure 12. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation
-80 dB/dec
X
Margin
50kHz 1MHz 5MHz
1
B
Desired Closed
Loop Gain
CS3001
CS3002
Figure14onpage12illustrates a load cell bridge
amplifier with a gain of 768 V/V. The load cell is
excited with +5 V and has a 1 mV/V sensitivity. Its
full scale output signal is amplified to produce a
Dexter Research
Thermopile 1M
fully differential ± 3.8 V into the CS5510/12 A/D
converter. This circuit operates from +5 V.
A similar circuit operating from +3 V can be
constructed using the CS5540/CS5541 A/D converters.
CS3001
R2
64.9k
R1
100
Th erm opile Amplifie r w ith a Gain of 650 V /V
C1
0.015
µµµµ F
Figure 13. Thermopile Amplifier with a Gain of 650 V/V
11
CS3001
µ
F
µ
F
µ
CS3002
+5 V
VA
1mV/V
+5 V +5 V
F
0.1
VREF
AIN+
AIN1
140 k
365
140 k
x768
Ω
Ω
Ω
+
-
Ω
-
350
+
-
+
100
0.22
0.047µF
0.22
100
Ω
Ω
V+
CS
SDO
SCLK
CS5510/12
V-
SC LK = 10 kHz to 10 0
SCLK = 10 kHz to 100 kHz
(32.76 8
(32.768 nom inal
)
µµµµ
Counter/T imer
Figure 14. Load Cell Bridge Amplifier and A/D Converter
12
4. PACKAGE DRAWING
8L SOIC (150 MIL BODY) PACKAGE DRAWING
1
b
CS3001
CS3002
E
H
D
SEATING
PLANE
e
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.053 0.069 1.35 1.75
A1 0.004 0.010 0.10 0.25
B 0.013 0.020 0.33 0.51
C 0.007 0.010 0.19 0.25
D 0.189 0.197 4.80 5.00
E 0.150 0.157 3.80 4.00
e 0.040 0.060 1.02 1.52
H 0.228 0.244 5.80 6.20
L 0.016 0.050 0.40 1.27
∝
0° 8° 0° 8°
JEDEC # : MS-012
A
A1
c
L
∝
13
5. ORDERING INFORMATION
Part # Temperature Range Package Description
CS3001-IS -40 °Cto+85°C 8-lead SOIC
CS3002-IS -40 °Cto+85°C 8-lead SOIC
Note: Add the letter R to the Part # to order reels. There are 2000 pieces per reel.
CS3001
CS3002
14
• Notes •
Loading...