Auxiliary
Output
6 to 75 MHz
PLL Output
Frequency Reference
3.3 V
Fractional-N
Frequency Synthesizer
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
N
PLL Output
Lock Indicator
50 Hz to 30 MHz
Frequency Reference
LCO
Hardware Configuration
Hardware Control
CS2300-OTP
Fractional-N Clock Multiplier with Internal LCO
Features
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery 50 Hz to 30 MHz Clock
Source
Internal LCO Reference Clock
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in High-
Resolution Mode
One-Time Programmability
– Configurable Hardware Control Pins
– Configurable Auxiliary Output
Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2300-OTP is an extremely versatile system
clocking device that utilizes a programmable phase lock
loop. The CS2300-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an external
noisy synchronization clock with frequencies as low as
50 Hz. The CS2300-OTP has many configuration options which are set once prior to runtime. At runtime
there are three hardware configuration pins available for
mode and feature selection.
The CS2300-OTP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) and Automotive
(-40°C to +85°C) grades. Customer development kits
are also available for custom device prototyping, small
production programming, and device evaluation.
Please see “Ordering Information” on page 25 for com-
plete details.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY '10
DS844F2
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
PLL PERFORMANCE PLOTS ............................................................................................................... 8
4. ARCHITECTURE OVERVIEW ............................................................................................................... 9
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 9
4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 9
5. APPLICATIONS ................................................................................................................................... 11
5.1 One Time Programmability ............................................................................................................ 11
5.2 Timing Reference Clock ................................................................................................................. 11
5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 11
5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 11
5.4 Output to Input Frequency Ratio Configuration ............................................................................. 13
5.4.1 User Defined Ratio (RUD) ..................................................................................................... 13
5.4.2 Ratio Modifier (R-Mod) .......................................................................................................... 13
5.4.3 Effective Ratio (REFF) .......................................................................................................... 13
5.4.4 Ratio Configuration Summary ............................................................................................... 14
5.5 PLL Clock Output ........................................................................................................................... 15
5.6 Auxiliary Output .............................................................................................................................. 16
5.7 Mode Pin Functionality ................................................................................................................... 16
5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 16
5.7.2 M2 Mode Pin Functionality .................................................................................................... 17
5.7.2.1 M2 Configured as Output Disable .............................................................................. 17
5.7.2.2 M2 Configured as R-Mod Enable .............................................................................. 17
5.7.2.3 M2 Configured as AuxOutSrc Override ..................................................................... 17
5.8 Clock Output Stability Considerations ............................................................................................ 18
5.8.1 Output Switching ................................................................................................................... 18
5.8.2 PLL Unlock Conditions .......................................................................................................... 18
5.9 Required Power Up Sequencing for Programmed Devices ........................................................... 18
6. PARAMETER DESCRIPTIONS ........................................................................................................... 19
6.1 Modal Configuration Sets ............................................................................................................... 19
6.1.1 R-Mod Selection (RModSel[1:0]) ...........................................................................................19
6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 20
6.2 Ratio 0 - 3 ...................................................................................................................................... 20
6.3 Global Configuration Parameters ................................................................................................... 20
6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 20
6.3.2 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 20
6.3.3 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 20
6.3.4 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 21
6.3.5 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 21
7. CALCULATING THE USER DEFINED RATIO .................................................................................... 22
7.1 High Resolution 12.20 Format ....................................................................................................... 22
7.2 High Multiplication 20.12 Format ................................................................................................... 22
8. PROGRAMMING INFORMATION ........................................................................................................ 23
9. PACKAGE DIMENSIONS .................................................................................................................... 24
THERMAL CHARACTERISTICS ......................................................................................................... 24
10. ORDERING INFORMATION .............................................................................................................. 25
11. REVISION HISTORY .......................................................................................................................... 25
CS2300-OTP
DS844F2 2
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 8
Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 8
Figure 4. CLK_IN Random Jitter Rejection and Tolerance .........................................................................8
Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer .......................................................................9
Figure 6. Hybrid Analog-Digital PLL .......................................................................................................... 10
Figure 7. External Component Requirements for LCO ............................................................................. 11
Figure 8. Low bandwidth and new clock domain ...................................................................................... 12
Figure 9. High bandwidth with CLK_IN domain re-use .............................................................................12
Figure 10. Ratio Feature Summary ........................................................................................................... 14
Figure 11. PLL Clock Output Options ....................................................................................................... 15
Figure 12. Auxiliary Output Selection ........................................................................................................ 16
Figure 13. M2 Mapping Options ................................................................................................................ 17
Figure 14. Parameter Configuration Sets .................................................................................................. 19
LIST OF TABLES
Table 1. Modal and Global Configuration .................................................................................................. 11
Table 2. Ratio Modifier .............................................................................................................................. 13
Table 3. Example 12.20 R-Values ............................................................................................................ 22
Table 4. Example 20.12 R-Values ............................................................................................................ 22
CS2300-OTP
DS844F2 3
CS2300-OTP
1
2
3
4
5
6
7
8
9
10
FILTP
CLK_OUT
GND
VD
FILTN
M2
M1
M0
AUX_OUT
CLK_IN
1. PIN DESCRIPTION
Pin Name # Pin Description
VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.
GND 2 Ground (Input) - Ground reference.
CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.
AUX_OUT 4
CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference.
FILTP
FILTN
M2 8 Mode Select (Input) - M2 is a configurable mode selection pin.
M1 9 Mode Select (Input) - M1 is a configurable mode selection pin.
M0 10 Mode Select (Input) - M0 is a configurable mode selection pin.
Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on configuration.
67LCO Filter Connections (Input/Output) - These pins provide external supply filtering for the LCO.
4 DS844F2
2. TYPICAL CONNECTION DIAGRAM
GND
M2
M1
FILTP
Frequency Reference CLK_IN
FILTN
CLK_OUT
AUX_OUT
0.1 µF
VD
+3.3 V
M0
System Microcontroller
1 µF
0.1 µF
To circuitry which requires
a low-jitter clock
To other circuitry or
Microcontroller
Figure 1. Typical Connection Diagram
CS2300-OTP
CS2300-OTP
DS844F2 5
CS2300-OTP
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note 1)
Parameters Symbol Min Typ Max Units
DC Power Supply (Note 2) VD 3.1 3.3 3.5 V
Ambient Operating Temperature (Power Applied)
Commercial Grade
Automotive Grade
T
AC
T
AD
-10
-40
-
-
+70
+85
°C
°C
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits
may adversely affect device reliability.
2. CLK_IN must not be applied when these conditions are not met, including during power up. See section
5.9 on page 18 for required power up procedure.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply VD -0.3 6.0 V
Input Current I
Digital Input Voltage (Note 3)V
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
IN
IN
A
stg
-±10mA
-0.3 VD + 0.4 V
-55 125 °C
-65 150 °C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Notes: 3. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T
= -40°C to +85°C (Automotive Grade).
A
Parameters Symbol Min Typ Max Units
Power Supply Current - Unloaded (Note 4)I
Power Dissipation - Unloaded (Note 4)P
Input Leakage Current I
Input Capacitance I
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (IOH = -1.2 mA) V
Low-Level Output Voltage (I
= 1.2 mA) V
OH
D
D
IN
C
IH
IL
OH
OL
Notes: 4. To calculate the additional current consumption due to loading (per output pin), multiply clock output
frequency by load capacitance and power supply voltage.
For example,
f
CLK_OUT
(49.152 MHz) * CL(15 pF) * VD (3.3 V) = 2.4 mA of additional current due to
these loading conditions on CLK_OUT.
-1823mA
-5976mW
--±10µA
-8-pF
70% - - VD
--30%VD
80% - - VD
--20%VD
6 DS844F2
CS2300-OTP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T
= -40°C to +85°C (Automotive Grade); CL=15pF.
A
Parameters Symbol Conditions Min Typ Max Units
Clock Input Frequency f
Clock Input Pulse Width pw
PLL Clock Output Frequency f
PLL Clock Output Duty Cycle t
Clock Output Rise Time t
Clock Output Fall Time t
Period Jitter t
CLK_IN
CLK_IN
CLK_OUT
OD
OR
OF
JIT
f
< 175 kHz
CLK_IN
f
> 175 kHz
CLK_IN
Measured at VD/2 45 50 55 %
20% to 80% of VD - 1.7 3.0 ns
80% to 20% of VD - 1.7 3.0 ns
(Note 5) - 35 - ps rms
Base Band Jitter (100 Hz to 40 kHz) (Notes 5, 6) - 50 - ps rms
Wide Band JItter (100 Hz Corner) (Notes 5, 7) - 150 - ps rms
PLL Lock Time - CLK_IN (Note 8)t
LC
f
CLK_IN
f
CLK_IN
< 200 kHz
> 200 kHz
50 Hz - 30 MHz
140
10
-
-
-
-
ns
ns
6-75MHz
-
100
-
1
200
3
UI
ms
Notes: 5. f
6. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
7. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
8. 1 UI (unit interval) corresponds to t
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.
order 100 Hz to 40 kHz bandpass filter.
order 100 Hz Highpass filter.
CLK_IN
or 1/f
CLK_IN
.
DS844F2 7
PLL PERFORMANCE PLOTS
1 10 100 1, 000 10,000
0.1
1
10
100
1,000
10,000
Input Jitter Frequency (Hz)
Max Input Jitter L eve l (usec)
1 Hz Bandwidth
128 Hz Bandwidth
1 10 100 1000 10000
-60
-50
-40
-30
-20
-10
0
10
Input Jitter Frequency (Hz)
Jitter Transfer (dB)
1 Hz Bandwidt h
128 Hz Bandwi dth
Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
Figure 4. CLK_IN Random Jitter Rejection and Tolerance
0.01 0.1 1 10 100 1000
0.01
0.1
1
10
100
1000
Input Jitter Level (nsec)
Output Jitter Level (nsec)
1 Hz Bandwidt h
128 Hz Bandwidt h
Unlock
Unlock
Test Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; f
f
CLK_IN
= 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] =11.
CLK_OUT
CS2300-OTP
= 12.288 MHz;
8 DS844F2
4. ARCHITECTURE OVERVIEW
Fractional-N
Divider
PLL Output
Voltage Controlled
Oscillator
Internal
Loop Filter
Phase
Comparator
N
Delta-Sigma
Modulator
LC Oscillator
4.1 Delta-Sigma Fractional-N Frequency Synthesizer
The core of the CS2300 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to
quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies
the LC Oscillator (LCO) by the value of N to generate the PLL output clock. The desired output to input clock
ratio is the value of N that is applied to the delta-sigma modulator (see Figure 5).
The analog PLL based frequency synthesizer uses a low-jitter timing reference clock, the LCO, as a time
and phase reference for the internal voltage controlled oscillator (VCO). The phase comparator compares
the fractional-N divided clock with the original timing reference and generates a control signal. The control
signal is filtered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio
between the reference clock and the VCO output (thus the duty cycle of the modulator sets the fractional
value). This allows the design to be optimized for very fast lock times for a wide range of output frequencies
without the need for external filter components.
CS2300-OTP
Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer
4.2 Hybrid Analog-Digital Phase Locked Loop
The addition of the Digital PLL and Fractional-N Logic (shown in Figure 6) to the Fractional-N Frequency
Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical analog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges
without the need to change external loop filter components while maintaining impressive jitter reduction performance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the frequency reference and compares that to the desired ratio. The digital logic generates a value of N which is
then applied to the Fractional-N frequency synthesizer to generate the desired PLL output frequency. Notice
that the frequency and phase of the LCO does not affect the output of the PLL since the digital control loop
will correct for the PLL output. A major advantage of the Digital PLL is the ease with which the loop filter
bandwidth can be altered. The PLL bandwidth is set to a wide-bandwidth mode to quickly achieve lock and
then reduced for optimal jitter rejection.
DS844F2 9
CS2300-OTP
N
Digital Filter
Frequency
Comparator for
Frac-N Generation
Frequency Reference
Clock
Delta-Sigma Fractional-N Frequency Synthesizer
Digital PLL and Fractional-N Logic
Output to Input Ratio for Hybrid mode
Fractional-N
Divider
PLL Output
Voltage Controlled
Oscillator
Internal
Loop Filter
Phase
Comparator
Delta-Sigma
Modulator
LCO
Figure 6. Hybrid Analog-Digital PLL
10 DS844F2
5. APPLICATIONS
Figure 7. External Component Requirements for LCO
FILTN FILTP
0.1 µF
5.1 One Time Programmability
The one time programmable (OTP) circuitry in the CS2300-OTP allows for pre-configuration of the device
prior to use in a system. There are two types of parameters that are used for device pre-configuration:
and global. The modal parameters are features which, when grouped together, create a modal configuration
set (see Figure 14 on page 19). Up to four modal configuration sets can be permanently stored and then
dynamically selected using the M[1:0] mode select pins (see Table 1). The
maining configuration settings which do not change with the mode select pins. The modal and global parameters can be pre-set at the factory or user programmed using the customer development kit, CDK2000;
Please see “Programming Information” on page 23 for more details.
Parameter Type M[1:0] pins = 00 M[1:0] pins = 01 M[1:0] pins = 10 M[1:0] pins = 11
Modal Configuration Set 0
Ratio 0
Global Configuration settings set once for all modes.
Table 1. Modal and Global Configuration
5.2 Timing Reference Clock
Configuration Set 1
Ratio 1
global parameters are the re-
Configuration Set 2
Ratio 2
CS2300-OTP
modal
Configuration Set 3
Ratio 3
The internal LC oscillator is used to generate the timing reference clock. A single 0.1 µF cap must be connected between the FILTP and FILTN pins and FILTN must be connected to ground as shown in Figure 7.
5.3 Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to
dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid Analog-Digital PLL”
on page 10). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic
block then translates the desired ratio based off of CLK_IN to one based off of the internal LCO. This allows
the low-jitter internal LCO to be used as the clock which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency
range for CLK_IN is found in the “AC Electrical Characteristics” on page 7.
5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN
DS844F2 11
The CS2300 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and
128 Hz using the
ly affects the jitter transfer function; specifically, jitter frequencies below the loop bandwidth corner are
passed from the PLL input directly to the PLL output without attenuation. In some applications it is desirable to have a very low minimum loop bandwidth to reject very low jitter frequencies, commonly referred
ClkIn_BW[2:0] global parameter. The minimum loop bandwidth of the Digital PLL direct-
CS2300-OTP
Figure 8. Low bandwidth and new clock domain
LRCK
SCLK
SDATA
MCLK
MCLK
Wander > 1 Hz
Wander and Jitter > 1 Hz Rejected
D0 D1
LRCK
SCLK
SDATA
Subclocks generated
from new clock domain .
or
PLL
BW = 1 Hz
CLK_IN
PLL_OUT
D0 D1
Jitter
Figure 9. High bandwidth with CLK_IN domain re-use
D0 D1
LRCK
SCLK
SDATA
MCLK
MCLK
Wander < 128 Hz
Jitter > 128 Hz Rejected
Wander < 128 Hz Passed to Output
LRCK
SCLK
SDATA
or
PLL
BW = 128 Hz
CLK_IN PLL_OUT
Subclocks and data re-us ed
from previous clock domain .
Jitter
D0 D1
to as wander. In others it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the PLL without attenuation.
Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other system clocks and associated data are derived will benefit from the maximum jitter and wander rejection of
the lowest PLL bandwidth setting. See Figure 8.
Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data
are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the
system. See Figure 9. If there is substantial wander on the CLK_IN signal in these applications, it may be
necessary to increase the minimum loop bandwidth allowing this wander to pass through to the CLK_OUT
signal in order to maintain phase alignment. For these applications, it is advised to experiment with the
loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing
errors due to wandering between the clocks and data synchronous to the CLK_IN domain and those synchronous to the PLL_OUT domain.
While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is
achieved, the digital loop bandwidth will settle to the minimum value selected by the
ClkIn_BW[2:0] pa-
rameter.
Referenced Control Parameter Definition
ClkIn_BW[2:0] .......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 21
12 DS844F2
5.4 Output to Input Frequency Ratio Configuration
5.4.1 User Defined Ratio (RUD)
The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number which determines the basis for the
desired input to output clock ratio. Up to four different ratios,
time programmable memory. Selection between the four ratios is achieved by the M[1:0] mode select
pins. The 32-bit R
format selectable by the
can be expressed in either a high resolution (12.20) or high multiplication (20.12)
UD
LFRatioCfg global parameter.
Ratio
CS2300-OTP
, can be stored in the CS2300’s one
0-3
The R
for high resolution (12.20) format is encoded with 12 MSBs representing the integer binary por-
UD
tion with the remaining 20 LSBs representing the fractional binary portion. The maximum multiplication
factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Calculating the
User Defined Ratio” on page 22 for more information.
The R
for high multiplication (20.12) format is encoded with 20 MSBs representing the integer binary
UD
portion with the remaining 12 LSBs representing the fractional binary portion. In this configuration, the
maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less than 4096 since
the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference
clock and the resolution of the R
Referenced Control Parameter Definition
Ratio 0-3................................“Ratio 0 - 3” on page 20
LFRatioCfg ............................ “Low-Frequency Ratio Configuration (LFRatioCfg)” on page 20
M[1:0] ....................................“M1 and M0 Mode Pin Functionality” on page 16
5.4.2 Ratio Modifier (R-Mod)
The Ratio Modifier is used to internally multiply/divide the currently addressed RUD (Ratio
register space remain unchanged). The available options for R-Mod are summarized in Table 2 on
page 13. R-Mod is enabled via the M2 pin in conjunction with the appropriate setting of the
global parameter (see Section 5.7.2 on page 17).
RModSel[1:0] R Modifier
.
UD
00 0.5
01 0.25
10 0.125
11 0.0625
stored in the
0-3
M2Config[2:0]
Table 2. Ratio Modifier
Referenced Control Parameter Definition
Ratio 0-3................................“Ratio 0 - 3” on page 20
RModSel[1:0] ........................“R-Mod Selection (RModSel[1:0])” section on page 19
M2Config[2:0]........................ “M2 Pin Configuration (M2Config[2:0])” on page 21
5.4.3 Effective Ratio (R
The Effective Ratio (R
previously described. R
= RUD • R-Mod
R
EFF
)
EFF
) is an internal calculation comprised of RUD and the appropriate modifiers, as
EFF
is calculated as follows:
EFF
DS844F2 13
CS2300-OTP
Effective Ratio R
EFF
Ratio Format
Frequency Reference Clock
(CLK_IN)
PLL Output
Frequency
Synthesizer
Digital PLL &
Fractional N Logic
Ratio 0
Ratio 1
Ratio 2
Ratio 3
12.20
20.12
M[1:0] pins
LFRatioCfg
RModSel[1:0]
4
Ratio
Modifier
LCO
Dynamic Ratio, ‘N’
User Defined Rati o R
UD
M2 pin
Ratio modifiers which would produce an overflow or truncation of R
the maximum and minimum allowable values for R
input and output clocks as shown in the “AC Electrical Characteristics” on page 7.
Selection of the user defined ratio from the four stored ratios is made by using the M[1:0] pins.
Referenced Control Parameter Definition
M[1:0] pins.............................“M1 and M0 Mode Pin Functionality” on page 16
5.4.4 Ratio Configuration Summary
The RUD is the user defined ratio for which up to four different values (Ratio
time programmable memory. The M[1:0] pins then select the user defined ratio to be used as well as the
modal configuration set. The resolution/format for the R
The user defined ratio, ratio modifier, and automatic ratio modifier make up the effective ratio R
final calculation used to determine the output to input clock ratio. The conceptual diagram in Figure 10
summarizes the features involved in the calculation of the ratio values used to generate the fractional-N
value which controls the Frequency Synthesizer. The subscript ‘4’ indicates the modal parameters.
should not be used. In all cases,
are dictated by the frequency limits for both the
EFF
is selectable. R-Mod is applied accordingly.
UD
EFF
) can be stored in the one
0-3
EFF
, the
Figure 10. Ratio Feature Summary
Referenced Control Parameter Definition
Ratio 0-3................................“Ratio 0 - 3” on page 20
M[1:0] pins.............................“M1 and M0 Mode Pin Functionality” on page 16
LFRatioCfg ............................ “Low-Frequency Ratio Configuration (LFRatioCfg)” on page 20
RModSel[1:0] ........................“R-Mod Selection (RModSel[1:0])” section on page 19
14 DS844F2
5.5 PLL Clock Output
PLL Locked/Unlocked
PLL Output
2:1 Mux
M2 pin with
M2Config[1:0] = 000, 010
2:1 Mux
ClkOutUnl
0
PLL Clock Output Pin
(CLK_OUT)
0
1
0
1
PLL Clock Output
PLLClkOut
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the M2 pin when the
either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is unlocked (when the clock may be unreliable). This feature can be disabled by setting the
parameter, however the state CLK_OUT may then be unreliable during an unlock condition.
Referenced Control Parameter Definition
ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 20
ClkOutDis .............................. “M2 Configured as Output Disable” on page 17
M2Config[2:0]........................ “M2 Pin Configuration (M2Config[2:0])” on page 21
CS2300-OTP
M2Config[1:0] global parameter is set to
ClkOutUnl global
Figure 11. PLL Clock Output Options
DS844F2 15
5.6 Auxiliary Output
3:1 Mux
Auxiliary Output Pin
(AUX_OUT)
AuxOutSrc[1:0]
AuxLockCfg
PLL Clock Output
(PLLClkOut)
PLL Lock/Unlock Indication
(Lock)
M2 pin with
M2Config[1:0] = 001, 010
Frequency Reference Clock
(CLK_IN)
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 12, to one of three signals: input
clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is controlled via the
eter is then used to control the output driver type and polarity of the LOCK signal (see section 6.3.1 on
page 20). If AUX_OUT is set to CLK_OUT, the phase of the PLL Clock Output signal on AUX_OUT may
differ from the CLK_OUT pin. The driver for the pin can be set to high-impedance using the M2 pin when
the
M2Config[1:0] global parameter is set to either 001 or 010.
AuxOutSrc[1:0] modal parameter. If AUX_OUT is set to Lock, the AuxLockCfg global param-
CS2300-OTP
Figure 12. Auxiliary Output Selection
Referenced Control Parameter Definition
AuxOutSrc[1:0]...................... “Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 20
AuxOutDis ............................. “M2 Configured as Output Disable” on page 17
AuxLockCfg........................... “AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 20
M2Config[2:0]........................ “M2 Pin Configuration (M2Config[2:0])” on page 21
5.7 Mode Pin Functionality
5.7.1 M1 and M0 Mode Pin Functionality
M[1:0] determine the functional mode of the device and select both the default User Defined Ratio and
the set of modal parameters. The modal parameters are
one or more of the modal parameters between the 4 sets, different functional configurations can be
achieved. However, global parameters are fixed and the same value will be applied to each functional
configuration. Figure 14 on page 19 provides a summary of all parameters used by the device.
RModSel[1:0], and AuxOutSrc[1:0]. By modifying
16 DS844F2
5.7.2 M2 Mode Pin Functionality
M2 pin
Disable CLK_OUT and AUX_OUT pins
Disable AUX_OUT pin
Disable CLK_OUT pin
RModSel[1:0] Modal Parameter Enable
Force AuxOutSel[1:0] = 10 (PLL Clock Out)
Reserved
M2Config[2:0] global parameter
000
001
010
011
100
101
110
111
Reserved
Reserved
M2 usage is mapped to one of the optional special functions via the M2Config[2:0] global parameter. Depending on what M2 is mapped to, it will either act as an output enable/disable pin or override certain modal parameters. Figure 13 summarizes the available options and the following sections will describe each
option in more detail.
CS2300-OTP
Figure 13. M2 Mapping Options
5.7.2.1 M2 Configured as Output Disable
If M2Config[2:0] is set to either ‘000’, ‘001’, or ‘010’, M2 becomes an output disable pin for one or
both output pins. If M2 is driven ‘low’, the corresponding output(s) will be enabled, if M2 is driven
‘high’, the corresponding output(s) will be disabled.
5.7.2.2 M2 Configured as R-Mod Enable
If M2Config[2:0] is set to ‘011’, M2 becomes the R-Mod enable pin. It should be noted that M2 is
the only way to enable R-Mod. Even though the
trarily for each configuration set, it will not take effect unless enabled via M2. If M2 is driven ‘low’,
R-Mod will be disabled, if M2 is driven ‘high’ R-Mod will be enabled.
5.7.2.3 M2 Configured as AuxOutSrc Override
If M2Config[2:0] is set to ‘111’, M2 when driven ‘high’ will override the AuxOutSrc[1:0] modal parameter and force the AUX_OUT source to PLL Clock Output. When M2 is driven ‘low’, AUX_OUT
will function according to
AuxOutSrc[1:0].
RModSel[1:0] modal parameter can be set arbi-
DS844F2 17
5.8 Clock Output Stability Considerations
5.8.1 Output Switching
The CS2300-OTP is designed such that re-configuration of the clock routing functions do not result in a
partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or
disabling an output, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period.
The following exceptions/limitations exist:
CS2300-OTP
• Enabling/disabling AUX_OUT when
• Switching
(Transitions between
When any of these exceptions occur, a partial clock period on the output may result.
AuxOutSrc[1:0] to or from 01 (CLK_IN) and to or from 11 (unlock indicator)
AuxOutSrc[1:0] = [00,10] will not produce a glitch).
AuxOutSrc[1:0] = 11 (unlock indicator).
5.8.2 PLL Unlock Conditions
Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the
presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go unlocked:
• Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new
setting takes affect.
• Changes made to the state of the M2 when the
or 110 can cause the PLL to temporarily lose lock as the new setting takes affect.
• Discontinuities on the Frequency Reference Clock, CLK_IN.
• Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.
M2Config[2:0] global parameter is set to 011, 100, 101,
5.9 Required Power Up Sequencing for Programmed Devices
• Apply power. All input pins should be held in a static logic hi or lo state until the DC Power Supply specification in the “Recommended Operating Conditions” table on page 6 are met.
• Apply input clock.
• For CDK programmed devices, toggle the state of the M0, M1, or both pins at least 3 times to initialize
the device. This must be done after the power supply is stable and before normal operation is expected.
Note:This operation is not required for factory programmed devices.
• After the specified PLL lock time on page 7 has passed, the device will output the desired clock as configured by the M0-M2 pins.
18 DS844F2
CS2300-OTP
M[1:0] pins
Modal Configuration Set #0
RModSel[1:0] AuxOutSrc[1:0]
Modal Configuration Set #1
Ratio 1 RModSel[1:0] AuxOutSrc[1:0]
Modal Configuration Set #2
Ratio 2 RModSel[1:0] AuxOutSrc[1:0]
Modal Configuration Set #3
Ratio 3 RModSel[1:0] AuxOutSrc[1:0]
00
01
10
11
Global Configuration Set
ClkOutUnlAuxLockCfg LFRatioCfg M2Config[2:0]
Ratio 0
Digital/PLL Core
ClkIn_BW[2:0]
6. PARAMETER DESCRIPTIONS
As mentioned in Section 5.1 on page 11, there are two different kinds of parameter configuration sets, Modal and
Global. These configuration sets, shown in Figure 14, can be programmed in the field using the CDK2000 or preprogrammed at the factory. Please see “Programming Information” on page 23 for more details.
6.1 Modal Configuration Sets
6.1.1 R-Mod Selection (RModSel[1:0])
Figure 14. Parameter Configuration Sets
There are four instances of each of these configuration parameters. Selection between the four stored sets
is made using the M[1:0] pins.
Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N.
RModSel[1:0] R-Mod Selection
00 Right-shift R-value by 1 (÷ 2).
01 Right-shift R-value by 2 (÷ 4).
10 Right-shift R-value by 3 (÷ 8).
11 Right-shift R-value by 4 (÷ 16).
Application: “Ratio Modifier (R-Mod)” on page 13
Note: This parameter does not take affect unless M2 pin is high and the M2Config[2:0] global param-
eter is set to ‘011’.
DS844F2 19
6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0] Auxiliary Output Source
00 Reserved.
01 CLK_IN.
10 CLK_OUT.
11 PLL Lock Status Indicator.
Application: “Auxiliary Output” on page 16
Note: When set to 11, the AuxLockCfg global parameter sets the polarity and driver type (“AUX PLL
Lock Output Configuration (AuxLockCfg)” on page 20).
6.2 Ratio 0 - 3
The four 32-bit User Defined Ratios are stored in the CS2300’s one time programmable memory. See “Out-
put to Input Frequency Ratio Configuration” on page 13 and “Calculating the User Defined Ratio” on
page 22 for more details.
6.3 Global Configuration Parameters
6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg)
CS2300-OTP
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] modal parameter = ‘11’), this
global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the
polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this parameter is disregarded.
AuxLockCfg AUX_OUT Driver Configuration
0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
1 Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
Application: “Auxiliary Output” on page 16
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the
unlock condition.
6.3.2 Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl Clock Output Enable Status
0 Clock outputs are driven ‘low’ when PLL is unlocked.
1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
Application: “PLL Clock Output” on page 15
6.3.3 Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio.
LFRatioCfg Ratio Bit Encoding Interpretation
0 20.12 - High Multiplier.
1 12.20 - High Accuracy.
Application: “User Defined Ratio (RUD)” on page 13
20 DS844F2
6.3.4 M2 Pin Configuration (M2Config[2:0])
Controls which special function is mapped to the M2 pin.
M2Config[2:0] M2 pin function
000 Disable CLK_OUT pin.
001 Disable AUX_OUT pin.
010 Disable CLK_OUT and AUX_OUT.
011 RModSel[1:0] Modal Parameter Enable.
100 Reserved.
101 Reserved.
110 Reserved.
111 Fo rce AuxOutSrc[1:0] = 10 (PLL Clock Out).
Application: “M2 Mode Pin Functionality” on page 17
6.3.5 Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
ClkIn_BW[2:0] Minimum Loop Bandwidth
000 1 Hz
001 2 Hz
010 4 Hz
011 8 Hz
100 16 Hz
101 32 Hz
110 64 H z
111 12 8 Hz
Application: “Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 11
CS2300-OTP
DS844F2 21
CS2300-OTP
7. CALCULATING THE USER DEFINED RATIO
Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User
Defined Ratio. This section is for those who would like to know more about how the User Defined Ratio is
calculated and stored.
Most calculators do not interpret the fixed point binary representation which the CS2300-OTP uses to define the
output to input clock ratio (see Section 5.4.1 on page 13); However, with a simple conversion we can use these tools
to generate a binary or hex value for
ming Information” on page 23 for more details on programming.
7.1 High Resolution 12.20 Format
Ratio
to be stored in one time programmable memory. Please see “Program-
0-3
To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 2
scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and
write to the register. A few examples have been provided in Table 3.
Desired Output to Input Clock Ratio
(output clock/input clock)
12.288 MHz/10 MHz=1.2288
11.2896 MHz/44.1 kHz=256
Table 3. Example 12.20 R-Values
7.2 High Multiplication 20.12 Format
To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 2
scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and
write to the register. A few examples have been provided in Table 4.
Desired Output to Input Clock Ratio
(output clock/input clock)
12.288 MHz/60 Hz=204,800
11.2896 MHz/59.97 Hz =188254.127...
Scaled Decimal
Representation =
(output clock/input clock)
1288490 00 13 A9 2A
268435456 10 00 00 00
Scaled Decimal
Representation =
(output clock/input clock)
838860800 32 00 00 00
771088904 2D F5 E2 08
• 2
• 2
Hex Representation of
20
Binary R
Hex Representation of
12
Binary R
20
to get the
UD
12
to get the
UD
Table 4. Example 20.12 R-Values
22 DS844F2
CS2300-OTP
8. PROGRAMMING INFORMATION
Field programming of the CS2300-OTP is achieved using the hardware and software tools included with the
CDK2000. The software tools can be downloaded from www.cirrus.com for evaluation prior to ordering a CDK. The
CDK2000 is designed with built-in features to ease the process of programming small quantities of devices for prototype and small production builds. In addition to its field programming capabilities, the CDK2000 can also be used
for the complete evaluation of programmed CS2300-OTP devices.
The CS2300-OTP can also be factory programmed for large quantity orders. When ordering factory programmed
devices, the CDK should first be used to program and evaluate the desired configuration. When evaluation is complete, the CS2000 Configuration Wizard is used to generate a file containing all device configuration information;
this file is conveyed to Cirrus Logic as a complete specification for the factory programming configuration. Please
contact your local Cirrus Logic sales representative for more information regarding factory programmed parts.
See the CDK2000 datasheet, available at www.cirrus.com, for detailed information on the use of the CDK2000 programming and evaluation tools.
Below is a form which represents the information required for programming a device (noted in gray). The “Parameter
Descriptions” section beginning on page 19 describes the functions of each parameter. This form may be used ei-
ther for personal notation for device configuration or it can be filled out and given to a Cirrus representative in conjunction with the programming file from the CDK2000 as an additional check. The User Defined Ratio may be filled
out in decimal or it may be entered as hex as outlined in “Calculating the User Defined Ratio” on page 22. For all
other parameters mark a ‘0’ or ‘1’ below the parameter name.
OTP Modal and Global Configuration Parameters Form
Modal Configuration Set #0
Ratio 0 (dec)
Ratio 0 (hex) __ __ : __ __ : __ __ : __ __
RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0
Modal Configuration Set #1
Ratio 1 (dec)
Ratio 1 (hex) __ __ : __ __ : __ __ : __ __
RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0
Modal Configuration Set #2
Ratio 2 (dec)
Ratio 2 (hex) __ __ : __ __ : __ __ : __ __
RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0
Modal Configuration Set #3
Ratio 3 (dec)
Ratio 3 (hex) __ __ : __ __ : __ __ : __ __
RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0
Global Configuration Set
AuxLockCfg ClkOutUnl LFRatioCfg M2Cfg2 M2Cfg1 M2Cfg0
ClkIn_BW2 ClkIn_BW1 ClkIn_BW0
DS844F2 23
CS2300-OTP
10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1)
E
N
1
23
e
b
A1
A2
A
D
SEATING
PLANE
E1
1
L
SIDE VIEW
END VIEW
TOP VIEW
∝
L1
c
9. PACKAGE DIMENSIONS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.0433 -- -- 1.10
A1 0 -- 0.0059 0 -- 0.15
A2 0.0295 -- 0.0374 0.75 -- 0.95
b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5
c 0.0031 -- 0.0091 0.08 -- 0.23
D -- 0.1181 BSC -- -- 3.00 BSC -- 2
E -- 0.1929 BSC -- -- 4.90 BSC --
E1 -- 0.1181 BSC -- -- 3.00 BSC -- 3
e -- 0.0197 BSC -- -- 0.50 BSC -L 0.0157 0.0236 0.0315 0.40 0.60 0.80
L1 -- 0.0374 REF -- -- 0.95 REF --
Notes: 1. Reference document: JEDEC MO-187
2. D does not include mold flash or protrusions which is 0.15 mm max. per side.
3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side.
4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
5. Exceptions to JEDEC dimension.
THERMAL CHARACTERISTICS
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance JEDEC 2-Layer
24 DS844F2
JEDEC 4-Layer
θ
JA
θ
JA
-
-
170
100
-
-
°C/W
°C/W
CS2300-OTP
10.ORDERING INFORMATION
The CS2300-OTP is ordered as an un-programmed device. The CS2300-OTP can also be factory programmed for
large quantity orders. Please see “Programming Information” on page 23 for more details.
Product Description Package
CS2300-OTP Clocking Device 10L-MSOP Yes
CS2300-OTP Clocking Device 10L-MSOP Yes -10° to +70°C
CS2300-OTP Clocking Device 10L-MSOP Yes
CS2300-OTP Clocking Device 10L-MSOP Yes -40° to +85°C
CDK2000 Evaluation Platform - Yes - - - CDK2000-LCO
Pb-Free Grade
Commercial
Automotive
Temp Range Container
-10° to +70°C Rail CS2300P-CZZ
Tape and
Reel
-40° to +85°C Rail CS2300P-DZZ
Tape and
Reel
Order#
CS2300P-CZZR
CS2300P-DZZR
REVISION HISTORY
Release Changes
F1 Updated Period Jitter specification in “AC Electrical Characteristics” on page 7.
Added
“PLL Performance Plots” table on page 8.
Removed CLK_IN Skipping Mode.
Removed Auto R-Mod.
Added Mode pin toggle requirement to startup for CDK programmed devices to “Required Power Up
Sequencing for Programmed Devices” on page 18.
F2 Updated to add Automotive Grade temperature ranges and ordering options.
DS844F2 25
CS2300-OTP
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com
.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
26 DS844F2
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