Cirrus Logic CS2300-OTP User Manual
Auxiliary
Output
6 to 75 MHz
PLL Output
Frequency Reference
3.3 V
Fractional-N
Frequency Synthesizer
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
N
PLL Output
Lock Indicator
50 Hz to 30 MHz
Frequency Reference
LCO
Hardware Configuration
Hardware Control
CS2300-OTP
Fractional-N Clock Multiplier with Internal LCO
Features
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery 50 Hz to 30 MHz Clock
Source
Internal LCO Reference Clock
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in High-
Resolution Mode
One-Time Programmability
– Configurable Hardware Control Pins
– Configurable Auxiliary Output
Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2300-OTP is an extremely versatile system
clocking device that utilizes a programmable phase lock
loop. The CS2300-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an external
noisy synchronization clock with frequencies as low as
50 Hz. The CS2300-OTP has many configuration options which are set once prior to runtime. At runtime
there are three hardware configuration pins available for
mode and feature selection.
The CS2300-OTP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) and Automotive
(-40°C to +85°C) grades. Customer development kits
are also available for custom device prototyping, small
production programming, and device evaluation.
Please see “Ordering Information” on page 25 for com-
plete details.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY '10
DS844F2
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
PLL PERFORMANCE PLOTS ............................................................................................................... 8
4. ARCHITECTURE OVERVIEW ............................................................................................................... 9
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 9
4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 9
5. APPLICATIONS ................................................................................................................................... 11
5.1 One Time Programmability ............................................................................................................ 11
5.2 Timing Reference Clock ................................................................................................................. 11
5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 11
5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 11
5.4 Output to Input Frequency Ratio Configuration ............................................................................. 13
5.4.1 User Defined Ratio (RUD) ..................................................................................................... 13
5.4.2 Ratio Modifier (R-Mod) .......................................................................................................... 13
5.4.3 Effective Ratio (REFF) .......................................................................................................... 13
5.4.4 Ratio Configuration Summary ............................................................................................... 14
5.5 PLL Clock Output ........................................................................................................................... 15
5.6 Auxiliary Output .............................................................................................................................. 16
5.7 Mode Pin Functionality ................................................................................................................... 16
5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 16
5.7.2 M2 Mode Pin Functionality .................................................................................................... 17
5.7.2.1 M2 Configured as Output Disable .............................................................................. 17
5.7.2.2 M2 Configured as R-Mod Enable .............................................................................. 17
5.7.2.3 M2 Configured as AuxOutSrc Override ..................................................................... 17
5.8 Clock Output Stability Considerations ............................................................................................ 18
5.8.1 Output Switching ................................................................................................................... 18
5.8.2 PLL Unlock Conditions .......................................................................................................... 18
5.9 Required Power Up Sequencing for Programmed Devices ........................................................... 18
6. PARAMETER DESCRIPTIONS ........................................................................................................... 19
6.1 Modal Configuration Sets ............................................................................................................... 19
6.1.1 R-Mod Selection (RModSel[1:0]) ...........................................................................................19
6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 20
6.2 Ratio 0 - 3 ...................................................................................................................................... 20
6.3 Global Configuration Parameters ................................................................................................... 20
6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 20
6.3.2 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 20
6.3.3 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 20
6.3.4 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 21
6.3.5 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 21
7. CALCULATING THE USER DEFINED RATIO .................................................................................... 22
7.1 High Resolution 12.20 Format ....................................................................................................... 22
7.2 High Multiplication 20.12 Format ................................................................................................... 22
8. PROGRAMMING INFORMATION ........................................................................................................ 23
9. PACKAGE DIMENSIONS .................................................................................................................... 24
THERMAL CHARACTERISTICS ......................................................................................................... 24
10. ORDERING INFORMATION .............................................................................................................. 25
11. REVISION HISTORY .......................................................................................................................... 25
CS2300-OTP
DS844F2 2
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 8
Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 8
Figure 4. CLK_IN Random Jitter Rejection and Tolerance .........................................................................8
Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer .......................................................................9
Figure 6. Hybrid Analog-Digital PLL .......................................................................................................... 10
Figure 7. External Component Requirements for LCO ............................................................................. 11
Figure 8. Low bandwidth and new clock domain ...................................................................................... 12
Figure 9. High bandwidth with CLK_IN domain re-use .............................................................................12
Figure 10. Ratio Feature Summary ........................................................................................................... 14
Figure 11. PLL Clock Output Options ....................................................................................................... 15
Figure 12. Auxiliary Output Selection ........................................................................................................ 16
Figure 13. M2 Mapping Options ................................................................................................................ 17
Figure 14. Parameter Configuration Sets .................................................................................................. 19
LIST OF TABLES
Table 1. Modal and Global Configuration .................................................................................................. 11
Table 2. Ratio Modifier .............................................................................................................................. 13
Table 3. Example 12.20 R-Values ............................................................................................................ 22
Table 4. Example 20.12 R-Values ............................................................................................................ 22
CS2300-OTP
DS844F2 3
CS2300-OTP
1
2
3
4
5
6
7
8
9
10
FILTP
CLK_OUT
GND
VD
FILTN
M2
M1
M0
AUX_OUT
CLK_IN
1. PIN DESCRIPTION
Pin Name # Pin Description
VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.
GND 2 Ground (Input) - Ground reference.
CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.
AUX_OUT 4
CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference.
FILTP
FILTN
M2 8 Mode Select (Input) - M2 is a configurable mode selection pin.
M1 9 Mode Select (Input) - M1 is a configurable mode selection pin.
M0 10 Mode Select (Input) - M0 is a configurable mode selection pin.
Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on configuration.
67LCO Filter Connections (Input/Output) - These pins provide external supply filtering for the LCO.
4 DS844F2
2. TYPICAL CONNECTION DIAGRAM
GND
M2
M1
FILTP
Frequency Reference CLK_IN
FILTN
CLK_OUT
AUX_OUT
0.1 µF
VD
+3.3 V
M0
System Microcontroller
1 µF
0.1 µF
To circuitry which requires
a low-jitter clock
To other circuitry or
Microcontroller
Figure 1. Typical Connection Diagram
CS2300-OTP
CS2300-OTP
DS844F2 5
CS2300-OTP
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note 1)
Parameters Symbol Min Typ Max Units
DC Power Supply (Note 2) VD 3.1 3.3 3.5 V
Ambient Operating Temperature (Power Applied)
Commercial Grade
Automotive Grade
T
AC
T
AD
-10
-40
-
-
+70
+85
°C
°C
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits
may adversely affect device reliability.
2. CLK_IN must not be applied when these conditions are not met, including during power up. See section
5.9 on page 18 for required power up procedure.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply VD -0.3 6.0 V
Input Current I
Digital Input Voltage (Note 3)V
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
IN
IN
A
stg
-±10mA
-0.3 VD + 0.4 V
-55 125 °C
-65 150 °C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Notes: 3. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T
= -40°C to +85°C (Automotive Grade).
A
Parameters Symbol Min Typ Max Units
Power Supply Current - Unloaded (Note 4)I
Power Dissipation - Unloaded (Note 4)P
Input Leakage Current I
Input Capacitance I
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (IOH = -1.2 mA) V
Low-Level Output Voltage (I
= 1.2 mA) V
OH
D
D
IN
C
IH
IL
OH
OL
Notes: 4. To calculate the additional current consumption due to loading (per output pin), multiply clock output
frequency by load capacitance and power supply voltage.
For example,
f
CLK_OUT
(49.152 MHz) * CL(15 pF) * VD (3.3 V) = 2.4 mA of additional current due to
these loading conditions on CLK_OUT.
-1823mA
-5976mW
--±10µA
-8-pF
70% - - VD
--30%VD
80% - - VD
--20%VD
6 DS844F2
CS2300-OTP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T
= -40°C to +85°C (Automotive Grade); CL=15pF.
A
Parameters Symbol Conditions Min Typ Max Units
Clock Input Frequency f
Clock Input Pulse Width pw
PLL Clock Output Frequency f
PLL Clock Output Duty Cycle t
Clock Output Rise Time t
Clock Output Fall Time t
Period Jitter t
CLK_IN
CLK_IN
CLK_OUT
OD
OR
OF
JIT
f
< 175 kHz
CLK_IN
f
> 175 kHz
CLK_IN
Measured at VD/2 45 50 55 %
20% to 80% of VD - 1.7 3.0 ns
80% to 20% of VD - 1.7 3.0 ns
(Note 5) - 35 - ps rms
Base Band Jitter (100 Hz to 40 kHz) (Notes 5, 6) - 50 - ps rms
Wide Band JItter (100 Hz Corner) (Notes 5, 7) - 150 - ps rms
PLL Lock Time - CLK_IN (Note 8)t
LC
f
CLK_IN
f
CLK_IN
< 200 kHz
> 200 kHz
50 Hz - 30 MHz
140
10
-
-
-
-
ns
ns
6-75MHz
-
100
-
1
200
3
UI
ms
Notes: 5. f
6. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
7. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
8. 1 UI (unit interval) corresponds to t
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.
order 100 Hz to 40 kHz bandpass filter.
order 100 Hz Highpass filter.
CLK_IN
or 1/f
CLK_IN
.
DS844F2 7
PLL PERFORMANCE PLOTS
1 10 100 1, 000 10,000
0.1
1
10
100
1,000
10,000
Input Jitter Frequency (Hz)
Max Input Jitter L eve l (usec)
1 Hz Bandwidth
128 Hz Bandwidth
1 10 100 1000 10000
-60
-50
-40
-30
-20
-10
0
10
Input Jitter Frequency (Hz)
Jitter Transfer (dB)
1 Hz Bandwidt h
128 Hz Bandwi dth
Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
Figure 4. CLK_IN Random Jitter Rejection and Tolerance
0.01 0.1 1 10 100 1000
0.01
0.1
1
10
100
1000
Input Jitter Level (nsec)
Output Jitter Level (nsec)
1 Hz Bandwidt h
128 Hz Bandwidt h
Unlock
Unlock
Test Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; f
f
CLK_IN
= 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] =11.
CLK_OUT
CS2300-OTP
= 12.288 MHz;
8 DS844F2
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