Cirrus Logic CS2300-CP User Manual
I²C / SPI
Auxiliary
Output
6 to 75 MHz
PLL Output
Frequency Reference
3.3 V
I²C/SPI
Software Control
Fractional-N
Frequency Synthesizer
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
N
PLL Output
Lock Indicator
50 Hz to 30 MHz
Frequency
Reference
LCO
CS2300-CP
Fractional-N Clock Multiplier with Internal LCO
Features
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to 30
MHz Clock Source
Internal LC Oscillator for Timing Reference
Highly Accurate PLL Multiplication Factor
– Maximum Error less than 1 PPM in High-
Resolution Mode
I²C™ / SPI™ Control Port
Configurable Auxiliary Output
Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2300-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2300-CP is based on a hybrid analog-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an external noisy synchronization clock at frequencies as low
as 50 Hz. The CS2300-CP supports both I²C and SPI
for full software control.
The CS2300-CP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) and Automotive
(-40°C to +85°C) grades. Customer development kits
are also available for device evaluation. Please see
“Ordering Information” on page 31 for complete details.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY '10
DS843F2
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 5
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7
RECOMMENDED OPERATING CONDITIONS .................................................................................... 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7
DC ELECTRICAL CHARACTERISTICS . ... ... .... ... ... ... .... ... ... ....................................... ... ... ... .... ... ... ... .... . 7
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8
PLL PERFORMANCE PLOTS ............................................................................................................... 9
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ........................ ... ...................... 10
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 11
4. ARCHITECTURE OVERVIEW ............................................................................................................. 12
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 12
4.2 Hybrid Analog-Digital Phase Locked Loop ....................................................................................12
5. APPLICATIONS ................................................................................................................................... 14
5.1 Timing Reference Clock .............. ... ... ... ... .... ... ... ... ....................................... ... .... ... ... ... ... ................ 14
5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 14
5.2.1 CLK_IN Skipping Mode ............ ... ... .... ... ... ... .... ... .......................................... ......................... 14
5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 16
5.3 Output to Input Frequency Ratio Configuration ............................................................................. 17
5.3.1 User Defined Ratio (RUD) ..................................................................................................... 17
5.3.2 Ratio Modifier (R-Mod) .......................................................................................................... 18
5.3.3 Effective Ratio (REFF) .......................................................................................................... 18
5.3.4 Ratio Configuration Summary ............................................................................................... 19
5.4 PLL Clock Output ........................................................................................................................... 20
5.5 Auxiliary Output ................. ... ... .... ... ... ....................................... ... ... ... ............................................. 20
5.6 Clock Output Stability Considerations ......... ... ... ... .... ... ... ... .... ...................................... ... .... ... ......... 21
5.6.1 Output Switching ................................................................................................................... 21
5.6.2 PLL Unlock Conditions .......................................................................................................... 21
5.7 Required Power Up Sequencing ................................................................. ... .... ... ... ... ... ................ 21
6. SPI / I²C CONTROL PORT ...................... ... ... .... ... ... ... ....................................... ... .... ... ......................... 21
6.1 SPI Control ........................ ... ....................................... ... ... .... ......................................................... 22
6.2 I²C Control .................. .... ... ... ... .... ... ....................................... ... ...................................................... 22
6.3 Memory Address Pointer ........................ .... ...................................... .... ... ... ... .... ... ......................... 24
6.3.1 Map Auto Increment .............................................................................................................. 24
7. REGISTER QUICK REFERENCE ........................................................................................................ 24
8. REGISTER DESCRIPTIONS ................................................................................................................ 25
8.1 Device I.D. and Revision (Address 01h) . .... ... ... ... .... ... ... .......................................... ... ... .... ... ... ...... 25
8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 25
8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 25
8.2 Device Control (Address 02h) ................. .............................................. ......................................... 25
8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 25
8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 25
8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 26
8.3 Device Configuration 1 (Address 03h) ........................................................................................... 26
8.3.1 R-Mod Selection (RModSel[2:0]) ........................ ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ...26
8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) .................... ......................................... 26
8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ............................ ............................ 27
8.4 Global Configuration (Address 05h) ............................................................................................... 27
8.4.1 Device Configuration Freeze (Freeze) .................................................................................. 27
8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ............................ ............................ 27
8.5 Ratio (Address 06h - 09h) .............................. ... ... .... ... ....................................... ... ... ... ... ................ 27
8.6 Function Configuration 1 (Address 16h) ............................... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 28
CS2300-CP
2 DS843F2
8.6.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 28
8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 28
8.6.3 Enable Device Configuration Registers 3 (EnDevCfg3) ............................ ............................ 28
8.7 Function Configuration 2 (Address 17h) ............................... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 29
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 29
8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 29
8.8 Function Configuration 3 (Address 1Eh) ........................................ ... .... ... ...................................... 29
8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 29
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 30
9.1 High Resolution 12.20 Format ....................................................... ... .... ......................................... 30
9.2 High Multiplication 20.12 Format ................................................................................................... 30
10. PACKAGE DIMENSIONS .................. ... ... ... .... ... ....................................... ... ... ... .... ... ... ...................... 31
THERMAL CHARACTERISTICS ......................................................................................................... 31
11. ORDERING INFORMATION .............. ... ... ... .... ... ... ... .... ... ....................................... ... ... ... ... .... ... ......... 32
12. REFERENCES ....................... ... ... .... ... ... ... ... .... ... ... ....................................... ... ... .... ... ... ...................... 32
13. REVISION HISTORY ............................. ... ... .... ... ....................................... ... ... ... .... ... ... ...................... 32
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 6
Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 9
Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 9
Figure 4. CLK_IN Random Jitter Rejection and Tolerance .......... .... ... ...................................... .... ... ... ........9
Figure 5. Control Port Timing - I²C Format ................................................................................................ 10
Figure 6. Control Port Timing - SPI Format (Write Only) .......................................................................... 11
Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 12
Figure 8. Hybrid Analog-Digital PLL .......................................................................................................... 13
Figure 9. External Component Requirements for LCO ............................................................................. 14
Figure 10. CLK_IN removed for > 2
Figure 11. CLK_IN removed for < 2
Figure 12. CLK_IN removed for < t
Figure 13. Low bandwidth and new clock domain .................................................................................... 17
Figure 14. High bandwidth with CLK_IN domain re-use ........................................................................... 17
Figure 15. Ratio Feature Summary ........................................................................................................... 19
Figure 16. PLL Clock Output Options ....................................................................................................... 20
Figure 17. Auxiliary Output Selection ........................... .......................................... ................................... 20
Figure 18. Control Port Timing in SPI Mode ............................................................................................. 22
Figure 19. Control Port Timing, I²C Write .................................................................................................. 23
Figure 20. Control Port Timing, I²C Aborted Write + Read .......................................................................23
CS2300-CP
23
LCO cycles ................................................................................... 15
23
LCO cycles but > t
CS .................................................................................................................................. 16
CS ....................................................................................... 15
LIST OF TABLES
Table 1. Ratio Modifier .............................................................................................................................. 18
Table 2. Example 12.20 R-Values ............................................................................................................ 30
Table 3. Example 20.12 R-Values ............................................................................................................ 30
DS843F2 3
CS2300-CP
1
2
3
4
5
6
7
8
9
10
FILTP
CLK_OUT
GND
VD
FILTN
AD0/CS
SCL/CCLK
SDA/CDIN
AUX_OUT
CLK_IN
1. PIN DESCRIPTION
Pin Name # Pin Description
VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.
GND 2 Ground (Input) - Ground reference.
CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.
AUX_OUT
CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference.
FILTP
FILTN
4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on register configuration.
67LCO Filter Connections (Input/Output) - These pins provide external supply filtering for the inter-
nal LC Oscillator.
AD0/CS
SCL/CCLK
SDA/CDIN
4 DS843F2
8 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C
Mode. CS is the chip select signal in SPI Mode.
9 Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI
mode.
10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data
line for the control port interface in SPI Mode.
2. TYPICAL CONNECTION DIAGRAM
GND
SCL/CCLK
SDA/CDIN
2 kΩ
Frequency Reference CLK_IN
CLK_OUT
AUX_OUT
0.1 µF
VD
+3.3 V
Notes:
1. Resistors
required for I
2
C
operation.
2 kΩ
AD0/CS
System MicroController
1 µF
Note
1
To circuitry which requires
a low-jitter clock
To other circuitry or
Microcontroller
FILTP
FILTN
0.1 µF
Figure 1. Typical Connection Diagram
CS2300-CP
CS2300-CP
DS843F2 5
CS2300-CP
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note 1)
Parameters Symbol Min Typ Max Units
DC Power Supply VD 3.1 3.3 3.5 V
Ambient Operating Temperature (Power Applied)
Commercial Grade
Automotive Grade
T
AC
T
AD
-10
-40
-
-
+70
+85
°C
°C
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits
may adversely affect device reliability.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply VD -0.3 6.0 V
Input Current I
Digital Input Voltage (Note 2)V
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
IN
IN
A
stg
-±10mA
-0.3 VD + 0.4 V
-55 125 °C
-65 150 °C
WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T
= -40°C to +85°C (Automotive Grade).
A
Parameters Symbol Min Typ Max Units
Power Supply Current - Unloaded (Note 3)I
Power Dissipation - Unloaded (Note 3)P
Input Leakage Current I
Input Capacitance I
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (I
Low-Level Output Voltage (I
= -1.2 mA) V
OH
= 1.2 mA) V
OH
D
D
IN
C
IH
IL
OH
OL
Notes: 3. To calculate the additional current consumption due to loading (per output pin), multiply clock output
frequency by load capacitance and power supply voltage.
For example,
f
CLK_OUT
(49.152 MHz) * CL(15 pF) * VD (3.3 V) = 2.4 mA of additional current due to
these loading conditions on CLK_OUT.
-1823mA
-5976mW
--±10µA
-8-pF
70% - - VD
--30%VD
80% - - VD
--20%VD
6 DS843F2
CS2300-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
= -40°C to +85°C (Automotive Grade); CL=15pF.
T
A
Parameters Symbol Conditions Min Typ Max Units
Clock Input Frequency f
Clock Input Pulse Width pw
Clock Skipping Timeout t
Clock Skipping Input Frequency f
PLL Clock Output Frequency f
PLL Clock Output Duty Cycle t
Clock Output Rise Time t
Clock Output Fall Time t
Period Jitter t
CLK_IN
CLK_IN
CS
CLK_SKIP
CLK_OUT
OD
OR
OF
JIT
f
< 175 kHz
CLK_IN
f
> 175 kHz
CLK_IN
(Notes 4, 5)20--ms
(Note 5) 50 Hz - 80 kHz
Measured at VD/2 45 50 55 %
20% to 80% of VD - 1.7 3.0 ns
80% to 20% of VD - 1.7 3.0 ns
(Note 6) - 35 - ps rms
Base Band Jitter (100 Hz to 40 kHz) (Notes 6, 7) - 50 - ps rms
Wide Band JItter (100 Hz Corner) (Notes 6, 8) - 150 - ps rms
PLL Lock Time - CLK_IN (Note 9)t
LC
f
CLK_IN
f
CLK_IN
< 200 kHz
> 200 kHz
50 Hz - 30 MHz
140
10
-
-
-
-
ns
ns
6-75MHz
-
100
-
1
200
3
UI
ms
Notes: 4. t
5. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 13 for more information.
6.
7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Inte rval Error taken with 3rd
8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Inte rval Error taken with 3rd
9. 1 UI (unit interval) corresponds to t
represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
CS
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequency, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.
CS
.
order 100 Hz to 40 kHz bandpass filter.
order 100 Hz Highpass filter.
CLK_IN
or 1/f
CLK_IN
.
DS843F2 7
PLL PERFORMANCE PLOTS
1 10 100 1,000 10,000
0.1
1
10
100
1,000
10,000
Input Jitter Frequency (Hz)
Max Input Jitter Level (usec)
1 Hz Bandwidth
128 Hz Bandwidth
1 10 100 1000 10000
-60
-50
-40
-30
-20
-10
0
10
Input Jitter Frequency (Hz)
Jitter Transfer (dB)
1 Hz Bandwidth
128 Hz Bandwi dth
Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
Figure 4. CLK_IN Random Jitter Rejection and To lerance
0.01 0.1 1 10 100 1000
0.01
0.1
1
10
100
1000
Inpu t Jit ter Level ( nsec)
Output Jitt e r Level ( nsec)
1 Hz Bandwidt h
128 Hz Bandwidt h
Unlock
Unlock
Test Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; f
CLK_IN
= 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] =11.
f
CLK_OUT
CS2300-CP
= 12.288 MHz;
8 DS843F2
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT
t
buf
t
hdst
t
hdst
t
low
t
r
t
f
t
hdd
t
high
t
sud
t
sust
t
susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
VD
t
dpor
Figure 5. Control Port Timing - I²C Format
Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.
Parameter Symbol Min Max Unit
SCL Clock Frequency f
Bus Free-Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 10)t
SDA Setup Time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling t
Delay from Supply Voltage Stable to Control Port Ready t
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
ack
dpor
- 100 kHz
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
300 1000 ns
100 - µs
CS2300-CP
Notes: 10. Data must be held for sufficient time to bridge the transition time, t
, of SCL.
f
DS843F2 9
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
csh
t
spi
t
dpor
VD
Figure 6. Control Port Timing - SPI Format (Write Only)
Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
CCLK Edge to CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CS
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 12)t
Rise Time of CCLK and CDIN (Note 13)t
Fall Time of CCLK and CDIN (Note 13)t
Delay from Supply Voltage Stable to Control Port Ready t
Notes: 11.
Falling (Note 11)t
t
is only needed before first falling edge of CS after power is applied. t
spi
ccllk
spi
csh
css
scl
sch
dsu
dh
r2
f2
dpor
12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For f
< 1 MHz.
cclk
-6MHz
500 - ns
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
- 100 ns
- 100 ns
100 - µs
= 0 at all other times.
spi
CS2300-CP
10 DS843F2
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