Cirrus Logic CS2300-03 User Manual

CS2300-03
1x, 4x, 128x, and 256x Clock Multiplier with Internal LCO
Features
Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery 23 kHz to 30 MHz Clock Source
Internal LCO Reference Clock128 Hz Loop Filter BandwidthSelectable Multiplication Factors
1x, 4x, 128x, and 256x
Selectable Aux Output PinMinimal Board Space Required
No External Analog Loop-filter
Components
General Description
The CS2300-03 is an extremely versatile system clock­ing device that utilizes a programmable phase lock loop. The CS2300-03 is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchroniza­tion clock with frequencies as low as 23 kHz. The CS2300-03 is a CS2300-OTP device that has been pre­configured at the factory. There are three hardware con­figuration pins available for mode and feature selection.
Ordering Information
The CS2300-03 is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) grade. Customer de­velopment kits are also available for custom device prototyping and device evaluation. Please see “Order-
ing Information” on page 2 for complete details.
Pin-Out Diagram
VD
GND
PLL_OUT
AUX_OUT
CLK_IN
1 2 3 4 5
10
9 8 7 6
M0 M1
CLK FILTN FILTP
/PLL
Hardware Controls Settings
M1 M0 PLL_OUT
00 01 4x CLK_IN 10 128x CLK_IN 11 256x CLK_IN
CKL/PLL AUX_OUT Source
0 1 PLL_OUT
1x CLK_IN
CLK_IN
0.1 µF
Ratio Selection
23 kHz to 30 MHz
Frequency Reference
FILTP
FILTN
M1 M0
10=128x 11=256x
CLK_IN
Advance Product Information
http://www.cirrus.com
LCO
M[1:0] 00=1x 01=4x
Output to Input Clock Ratio
VD
0.1 µF 1 µF
GND
3.3 V
Fractional-N
Frequency Synthesizer
N
128 Hz BW Digital PLL
& Fractional N Logic
PLL_OUT
CLK_IN
PLL_OUT
CLK/PLL
AUX_OUT
6 MHz to 75 MHz PLL Output
AUX Output Source Select
23 kHz to 75 MHz AUX Output
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
February '08
PS856A1
CS2300-03

1. PIN DESCRIPTIONS

Pin Name # Pin Description
VD 1 Digital Power GND 2 Ground PLL_OUT 3 PLL Clock Output AUX_OUT 4 AUX Output CLK_IN 5 Clock Input FILTP
FILTN
/PLL 8 AUX Output Source Selection Input
CLK M1
M0
67LCO Filter Connections
910Mode Selection Inputs

2. SPECIFICATIONS

Please see the CS2300-OTP datasheet for package in­formation, device characteristics, and specifications ex­cept where noted due to specific programming options.

3. OPERATIONAL INFORMATION

Complete operational information can be found in the CS2300-OTP datasheet. Specific operational details dictated by the programming of the CS2300-03 are in­cluded below.
• The PLL clock output is forced to 0 when the PLL is unlocked, both upon loss of the CLK_IN signal or briefly when switching mode pin configurations.
See the CS2300-OTP datasheet for additional pin de­scription information.
• The minimum loop filter bandwidth once locked is 128 Hz.

4. CONFIGURATION INFORMATION

The CS2300-03 has been factory pre-programmed with a unique configuration . The following table outlines the spe­cific configuration profile which can be compared to the CS2300-OTP d atasheet for detailed functional descriptions.
OTP Modal and Global Configuration Parameters Form
Mode 0 Mode 1 Mode 2 Mode 3
Ratio 0 (dec) 1 4 128 256 Ratio 0 (hex) 00:10:00:00 00:40:00:00 08:00:00:00 10:00:00:00
RModSel1 0000
RModSel0 0000 AuxOutSrc1 0000 AuxOutSrc0 1111
AutoRMod 0000
Global Configuration Set
ClkSkipEn AuxLockCfg ClkOutUnl LFRatioCfg M2Cfg2 M2Cfg1 M2Cfg0
0 0 0 1 1 1 1
ClkIn_BW2 ClkIn_BW1 ClkIn_BW0
1 1 1

5. ORDERING INFORMATION

Product Description Package
CS2300-03 Clocking Device 10L-MSOP Yes Commercial -10° to +70°C
CDK-2000 Evaluation Platform - Yes - - - CDK-2000-LCO
Pb-Free Grade
Temp Range Container
Rail CS230003-CZZ
Tape and
Reel
Order#
CS230003-CZZR
PS856A1 2
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