CS2300-02
1x, 2x, 4x, and 8x Clock Multiplier with Internal LCO
Features
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery 750 kHz to 30 MHz Clock
Source
Internal LCO Reference Clock
128 Hz Loop Filter Bandwidth
Selectable Multiplication Factors
– 1x, 2x, 4x, and 8x
Output Enable Pin
Lock Indicator
Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2300-02 is an extremely versatile system clocking device that utilizes a programmable phase lock loop.
The CS2300-02 is based on a hybrid analog-digital PLL
architecture comprised of a unique combination of a
Delta-Sigma Fractional-N Frequency Synthesizer and a
Digital PLL. This architecture allows for generation of a
low-jitter clock relative to an external noisy synchronization clock with frequencies as low as 750 kHz. The
CS2300-02 is a CS2300-OTP device that has been preconfigured at the factory. There are three hardware configuration pins available for mode and feature selection.
Ordering Information
The CS2300-02 is available in a 10-pin MSOP package
in Commercial (-10°C to +70°C) grade. Customer development kits are also available for custom device
prototyping and device evaluation. Please see “Order-
ing Information” on page 2 for complete details.
Pin-Out Diagram
VD
GND
CLK_OUT
LOCK
CLK_IN
1
2
3
4
5
10
9
8
7
6
M0
M1
OUT_EN
FILTN
FILTP
Hardware Controls Settings
M1 M0 PLL_OUT
00
01 2x CLK_IN
10 4x CLK_IN
11 8x CLK_IN
OUT_EN CLK_OUT
0
1 High Impedance
1x CLK_IN
Enabled
0.1 µF
Ratio Selection
750 kHz to 30 MHz
Frequency Reference
FILTP
FILTN
M1
M0
CLK_IN
Advance Product Information
http://www.cirrus.com
LCO
LOCK
Fractional-N
M[1:0]
00=1x
01=2x
10=4x
11=8x
Output to Input
Clock Ratio
Frequency Synthesizer
N
128 Hz BW Digital PLL
& Fractional N Logic
CLK_OUT
OUT_EN
VD
0.1 µF 1 µF
GND
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
PLL Lock
Indicator
6 MHz to 75 MHz
PLL Output
Output
Enable/Disable
3.3 V
February '08
PS855A1
CS2300-02
1. PIN DESCRIPTIONS
Pin Name # Pin Description
VD 1 Digital Power
GND 2 Ground
CLK_OUT 3 PLL Clock Output
LOCK
CLK_IN 5 Clock Input
FILTP
FILTN
OUT_EN
M1
M0
4 Active Low PLL Lock Indicator
67LCO Filter Connections
8 Active Low CLK_OUT Enable Input
910Mode Selection Inputs
2. SPECIFICATIONS
Please see the CS2300-OTP datasheet for package information, device characteristics, and specifications except where noted due to specific programming options.
3. OPERATIONAL INFORMATION
Complete operational information can be found in the
CS2300-OTP datasheet. Specific operational details
dictated by the programming of the CS2300-02 are included below.
• The PLL clock output is forced to 0 when the PLL is
unlocked, both upon loss of the CLK_IN signal or
briefly when switching mode pin configurations.
See the CS2300-OTP datasheet for additional pin description information.
• The minimum loop filter bandwidth once locked is
128 Hz.
4. CONFIGURATION INFORMATION
The CS2300-02 has been factory pre-programmed with a unique configuration . The following table outlines the specific configuration profile which can be compared to the CS2300-OTP d atasheet for detailed functional descriptions.
OTP Modal and Global Configuration Parameters Form
Mode 0 Mode 1 Mode 2 Mode 3
Ratio 0 (dec) 1248
Ratio 0 (hex) 00:10:00:00 00:20:00:00 00:40:00:00 00:80:00:00
RModSel1 0000
RModSel0 0000
AuxOutSrc1 1111
AuxOutSrc0 1111
AutoRMod 0000
Global Configuration Set
ClkSkipEn AuxLockCfg ClkOutUnl LFRatioCfg M2Cfg2 M2Cfg1 M2Cfg0
0 0 0 1 0 0 0
ClkIn_BW2 ClkIn_BW1 ClkIn_BW0
1 1 1
5. ORDERING INFORMATION
Product D escription Package
CS2300-02 Clocking Device 10L-MSOP Yes Commercial -10° to +70°C
CDK-2000 Evaluation Platform - Yes - - - CDK-2000-LCO
Pb-Free Grade
Temp Range Container
Rail CS230002-CZZ
Tape and
Reel
Order#
CS230002-CZZR
PS855A1 2
6. REVISION HISTORY
Release Changes
A1 Initial Release
CS2300-02
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
“Advance” product information describ es prod ucts that a re in develop me nt and subje ct to develo pm ent ch ange s. Cirru s Logi c, Inc. a nd its su bsidiari es (“Cirr us”) b elieve that the infor mati on cont aine d in t his d ocument is ac cura te and reli abl e. However , th e info rmat ion i s subj ect t o chan ge wi th out noti ce an d is provi ded “ AS IS ”
without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment,
including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, incl udi ng us e
of this information as t he basi s for man ufact ure or sale of an y items , or f or inf ringement of pat ents or othe r right s of t hird parties. This document is the property of
Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrig hts, trad emarks, trade secrets or
other intellectu al pr op er ty r i gh ts . Ci rr us ow ns t h e c opyr i gh t s a ss oci at e d wi th t he i nformation contain ed he re i n a nd gi ves c o nsent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such
as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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INDEMNIFY CIRRUS, ITS OFFICERS, DI RECTORS, EMPL OYEES, DIST RIBUT ORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES .
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or service marks of their respective owners.
PS855A1 3
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