Cirrus Logic CS22250 Datasheet
CS22250 Data Sheet
Wireless 10BT Controller
1 Introduction
The Cirrus Logic CS22250 Wireless Network Controller enables high speed, 11 Mbps digital
wireless data connectivity for wireless Ethernet bridge, access points, and other broadband
applications.
The CS22250 is a highly integrated single-chip Ethernet bridge solution for wireless networks
supporting video, audio, voice, and data traffic. The programmable controller executes Cirrus
Logic’s Whitecap™2 networking protocol that provides Wi-Fi™ (802.11b) compliance, multimedia
and a foundation for quality of service (QoS) applications, and Ethernet to wireless bridging. The
device includes several high performance components including an ARM7TDMI RISC processor
core, a Forward Error Correction (FEC) codec, and a wireless radio MAC supporting up to 11
Mbps throughput. The CS22250 utilizes state of the art 0.18um CMOS process and is housed in
a 208 FPBGA compact package, offering low-lead inductance suitable for highly integrated radio
applications. The core is powered at 1.8 V with 3.3V I/O to reduce overall power consumption. In
addition, the CS22250 supports various power management modes for host, MAC, baseband,
and radio interfaces.
The CS22250 is designed to provide integrated low cost IEEE 802.3 standard compliant system
solutions. The controller also incorporates a high-speed parallel interface, which can be used to
interface with other ASICs (eg: HNPA 2.0 Network controller) to implement a variety of other
wireless LAN bridging products.
10 BaseT
Ethernet PHY
AUI Serial Interface
802.11b compatible
2.4 GHz
Digital Radio
PHY Transceiver
2.4 GHz Direct Sequence
Spread Spectrum
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11 Mbps Wireless
Baseband I/F
CS22250
Wireless 10BT
Controller
High Speed Parallel Interface
Figure 1. Example System Block Diagram
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Configuration Interface (USB)
System Memory
SDRAM (Up to 4MB)
SRAM (Up to 256KB)
Boot ROM/Flash
(Upto1MB)
2 Features
Embedded ARM Core and System Support Logic
• High Performance ARM7TDMI RISC processor core up to 77MHz
• 4KB integrated, one-way set associative, unified, write through cache
• Individual interrupt for each functional block
• Two 23-bit programmable (periodic or one-shot) general purpose timers
• 8 Dword (32-bits) memory write and read buffers for high system performance
• Abort cycle detection and reporting for debugging
• ARM performance monitoring function for system fine-tuning
• Programmable performance improvement logic based on system configuration.
Enhanced Memory Controller Unit
• Programmable memory controller unit supporting SDRAM /async SRAM/boot ROM/Flash
interface
• 16-bit data bus with 12-bit address supporting up to 4MB and up to 103 MHz (100/133MHz
SDRAM)
• 8-bit data bus with addressing support up to 1MB of boot ROM/Flash
• Programmable SDRAM timing and size parameters, such as CAS latencies and number of
banks, columns and rows
• Flexible independent DMA engines for Ethernet MAC, Digital Radio and External Bus
functional units
FEC codec
• High performance Reed-Solomon coding for error correction (255:239 block coding)
• Reduces error probability of a typical 10e-3 error rate environment to 10e-9
• Programmable rate FEC engine to optimize channel efficiency
• Low latency, fully pipelined hardware encoding and decoding. Supports byte-wise single
cycle throughput up to 77MHz, with a sustain rate of 77MBps
• Double buffering (63 Dword read/write buffer) to enhance system performance
Digital Wireless Radio MAC
• Glue-less interface to 802.11b radio baseband transceiver
• 11Mbps data rate
• 32 Dword transmit/receive FIFO
• Supports clear channel assessment (CCA)
Ethernet Interface
• IEEE802.3 Ethernet MAC controller
• Two independent full-duplex DMA channels transfer between Ethernet interface to system
memory
• Standard 7-pin serial interfaces to AUI or Twisted Pair 10-BaseT
• Standard half-duplex CSMA/CD and full-duplex operation
USB Device Configuration Interface
• USB 1.1 compliant
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2 Features and Benefits
Power Management
• ACPI compliant
• Programmable sleep timer for ARM core and system power management
• Independent power management control for individual functional blocks
• Supports variable rate radio transmit, receive and standby radio power modes
Clock and PLL Interface
• Single 44MHz crystal oscillator reference clock
• Internal PLL to generate internal and on board clocks
Chip Processing and Packaging
• 208 FPBGA package and 0.18um state of the art CMOS process
• 1.8 V core for low power consumption. 3.3V I/O
High Speed Parallel Interface
• Multi-purpose 32bit bus for connecting with other high speed devices
• Supports operations at ½ the speed of the ARM clock (up to 38MHz)
• Two independent full-duplex DMA channels transfer between external devices to ARM
system memory
• Supports one external interrupt pin to the ARM core
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IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not
yet available. "Advance" product information describes products that are in development and subject to development
changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is
accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without
warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to
verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the
terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent
infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use
of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or
implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights.
Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information
only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does
not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating
any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products
or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be
exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of
the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH,
PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS").
CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFESUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN
SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product
names in this document may be trademarks or service marks of their respective owners.
Use of this product in any manner that complies with the MPEG-2 video standard as defined in ISO documents IS 138181 (including annexes C, D, F, J, and K), IS 13818-2 (including annexes A, B, C, and D, but excluding scalable extensions),
and IS 13818-4 (only as it is needed to clarify IS 13818-2) is expressly prohibited without a license under applicable
patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C. 250 Steele Street, Suite 300,
Denver, Colorado 80296.
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3 Functional Description
y
y
Figure 2. Block Diagram of Major Functional Units
DMA
stem Memor
S
Memory/Boot ROM
Controller
Arbiter
7pinSerial
Interface
High Speed
Parallel
Interface
Ethernet
MAC
w/ DMA
Controller
Parallel
Interface
Controller
Sleep
Timer
DMA
DMA
Controller
DMA
FEC codec
Read/Write Buffer
ARM 7TDMI
Interrupt
controller
77MHz System Control Bus
Config.
Registers
Timer
(2)
4KB
Cache
Clock/PLL
DMA
Radio MAC
w/DMACtrl
USB
JTAG/Test Interface
Digital Radio
Interface
USB Device
Configuration Interface
Crystal or
Oscillator
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3.1 Embedded ARM core and System Support Logic
The processing elements of the CS22250 include the ARM7TDMI core and its associated
system control logic. The ARM processor and system controller consist of a memory
management unit, 4-KB write through cache controller, 20 IRQ and 4 FIRQ interrupt
controller, and 2 general purpose timers. The ARM processor and integrated system
support logic provide the necessary execution engine to support a real time multi-tasking
operating system, the network protocol stack, and firmware services.
Memory Management UnitThe ARM instructions and data are fetched from system
memory per “cache-line” (4/8 – Dwords /Programmable) when caching is turned on.
During a cache line fill, critical word data, i.e., the access that caused the miss, is
forwarded to the ARM and also written into the data RAM cache. The non-critical words
in the line fetched following the critical word are then written to the cache on a Dword
basis, as they become available.
Memory writes are posted to dual 4-Dwords (32-bit) memory write posting buffers. Write
posts use the sequential addressing feature on the memory bus. With dual buffering, an
out-of-sequence write will post to one write buffer while the other buffer is flushed to
memory.
There is one 8Dword read buffer in the MEM block. The buffer is used for both cacheable
and non-cacheable memory space.
Interrupt Controller
The Interrupt Controller provides two interrupt channels to the ARM processor. One
interrupt channel is presented to the ARM on its nFIQ and the other channel is presented
on its nIRQ pin. These are referred to as the FIQ channel and the IRQ channel. Both
channels operate in identical but independent fashion. The FIQ channel has a higher
priority on the ARM processor than the IRQ channel.
The Interrupt Controller includes a CONTROL register for each logical interrupt in the
ARM Complex. The CONTROL register serves the following main purposes:
• Provides the mapping between the EXT_INT inputs (physical interrupts) and the
logical interrupt
• Selects the particular type of signaling expected on the EXT_INT inputs: level, edge,
active level high/low, etc.
• Enables or disables a logical interrupt
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3.2 Digital Wireless Radio Interface
The CS22250 digital radio MAC I/F supports multiple radio baseband and RF interfaces.
The baseband registers can be programmed during the configuration time using the
control port interface. The MAC also provides the capability of programming the signal,
service and length on a per packet basis without ARM intervention. This significantly
improves the performance of the system.
There are three primary digital interface ports for the CS22250 that are used for
configuration and during normal operation.
These ports are:
• The Control Port, which is used to configure, set power consumption modes, write
and/or read the status of the radio base band registers
• The TX Port, which is used to output the data that needs to be transmitted from the
network processor
• The RX Port, which is used to input the received demodulated data to the network
processor
3.3 FEC Codec
The FEC codec performs Reed-Solomon code encoding to protect the data before it is
transmitted to a noisy channel. It is a similar code as employed by the digital broadcast
industry, such as ITU-T J.83 for DVB. The RS(255, 239) code implemented by the
CS22250 can reduce error probability to 1/10e-9 in a typical 1/10e-3 error rate
environment. The encoder/decoder can be programmed to vary the coding block length
(N) and correctable error (t) to optimize the tradeoff between channel utilization and data
protection. The range of N is currently set from 20 to 255, and the t is 8. The symbol size
is fixed at 8 bits.
Coding parameters can be set real time, allowing maximum flexibility for the system to
adjust the FEC setting, such as block size, in order to optimize channel efficiency. The
encoder also has a very low latency of two cycles. Both the encoder and decoder are
fully pipelined in structure to achieve single cycle throughput. The FEC can be disabled in
firmware.
3.4 High Speed Parallel Interface
This optional connectivity interface is the extension of the ARM control bus brought
outside of the CS22250 chip. In order to reduce the pin count, address and data are
multiplexed in a 32-bit address/data External Control Bus. For ease of connecting other
devices to the CS22250, this bus runs at half the speed of the internal ARM control bus.
The external control Bus interface exchanges data with the main memory via DMAC
(DMA controller block). This functional block supports two DMA engines for full duplex
operation. Moreover, one external interrupt pin is supported.
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3.5 Programmable Memory Controller
The CS22250 incorporates a general-purpose memory controller. The memory controller
supports both SDRAM/async SRAM memory interface and a FLASH memory interface.
In the RAM configuration, the system memory interface supports up to 4-Mbyte of 16-bit
SDRAM running at frequency up to 103 MHz single-state access cycles or 256KB of 16
bit async SRAM. The memory controller provides programming of SDRAM parameters
such as CAS latency, refresh rate etc; these registers are located in miscellaneous
configuration registers. The CS22250 memory controller supports power saving feature
of the SDRAM by toggling the Clock Enable (CKE) signal. When there are no pending
memory requests from any internal requester, the CS22250 will keep CKE low to cause
the SDRAM to stay in power down mode. Once a memory request is active, the CS22250
will assert CKE high to cause the SDRAM to come out of power down mode.
Typicallythis can reduce memory power consumption by up to 50%.
In ROM configuration, firmware for CS22250 is stored in non-volatile memory and is
accessed through the Boot ROM interface. The maximum addressable ROM space
supported is 1MB. ROM read/write and output enable are shared with RAM control pins.
3.6 Ethernet MAC Controller
The Ethernet MAC controller interface allows the Cirrus Logic CS22250 to provide
connectivity to an Ethernet local area network. The controller can be used to interface
with a cable or xDSL modem to share high speed internet multimedia and data traffic in a
wireless home network. The Ethernet MAC controller is fully compliant with the IEEE
802.3 standard. The controller supports both half-duplex CSMA/CD and full-duplex
operation at 10Mbps.
The Ethernet MAC incorporates two power safe modes. The first disable mode disables
the entire MAC core including clocks. The second is a partial sleep mode, which only
disables transmit logic. In this mode, the entire MAC is powered upon receiving an
Ethernet packet. The Ethernet MAC uses two independent DMA controllers to support full
duplex operations with the system memory. The DMA controller is programmed and
configured by the ARM.
3.7 USB Configuration Interface
The USB interface is a device interface that allows for bridge configuration from a USBenabled PC. Switching between normal and configuration modes is controlled by external
logic.
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4 Pinout and Signal Descriptions
K
A
Figure 3. CS22250 Logical Pin Groupings
System
Memory
Interface
JTAG Interface
Clock Interface
PLL Power
Interface
DMA
Interface
SMCL
nSMCS[1:0]
nSMRAS
nSMCAS
nSMWE
SMDQM[1:0]
SMCKE
SMA[11:0]
SMD[15:0]
nBRCE
TDO
TDI
TCK
TMS
nTRST
NTEST
XTALIN
XTALOUT
XTRACLK
PLLAGND
PLLAVCC
PLLDVCC
PLLDGND
PLLPLUS
OSAD[31:0]
nOSWAIT
OSRNW
OSCLK
nOSRESET
OSCTLDIR
OSREQ
OSNINT
DMAREQ
DMAREQB
nPERR, nSERR
CS22250
Controller
EXT RESET
CSS
CSR
WC_WiFi
ERXCLK
ERXDO
ECOL
ECRS
ETXDO
ETXEN
USBVP
USBVM
USB_ENUM
TXCLK
TXPE
TXD
TXRDY
CCA
BBRNW
nRESETBB
BBAS
nBBCS
TXPAPE
TXPEBB
RXPEBB
BBSCLK
BBSDX
SYNTHLE
nRPD
RXCLK
MDRDY
RXD
SPIO’s
Ethernet
802.3 MAC
I/F
Digital
Wireless
Radio
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This section provides detailed information on the CS22250 signals. The signal descriptions are
useful for hardware designers who are interfacing the CS22250 with other devices.
System Memory Interface
The system memory interface supports standard SDRAM interface, Async SRAM and FLASH.
There are a total of 37 signals in this interface.
SMCLK Output
System mem clock for SDRAM. Currently the interface supports 103
MHz for a maximum bandwidth of 200Mbytes/sec.
nSMCS0 Output
Chip select bit 0. This signal is used to select or deselect the SDRAM for
command entry. When SMNCS is low it qualifies the sampling of
nSMRAS, nSMCAS and nSMWE. Also, used as testmode(2) when
NTEST pin is '0'.
nSMCS1 Output
Chip select bit 1.
NBRCE Output
Chip select for ROM access. This signal is used to select or deselect the
boot ROM memory. Also used during reset to latch in the strap value for
Ethernet; if set to a '1' implies Ethernet functional unit block is ‘enable’.
NSMRAS Output
Row address select. Used in combination with nSMCAS, nSMWE and
nSMCS to specify which SDRAM page to open for access. Also used
during reset to latch in the strap value for clk_bypass; if set to a '1'
implies bypassing clock module; whatever clk is applied on the input
clock is used for memclk and ctlclk. Also shared as the ROMOE signal.
NSMCAS Output
Column address select. Used in combination with nSMRAS, nSMWE
and nSMCS to specify which piece of data to access in selected page.
Also used during reset to latch in the strap value for same_freq; if set to
a '1' implies internal mem_clk and arm_clk are running at the same
frequency and 180 degrees out of phase.
NSMWE Output
Write Enable. Used in combination with nSMRAS, nSMCAS, and
nSMWE to specify whether the current cycle is a read or a write cycle.
Also used during reset to latch in the strap value for tst_bypass; if set to
a '1' implies PLL bypass. Also shared as the ROMWE to do flash
programming.
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