Cirrus Logic CS2200-OTP User Manual
Auxiliary
Output
6 to 75 MHz
PLL Output
3.3 V
8 MHz to 75 MHz
Low-Jitter Timing
Reference
Output to Input
Clock Ratio
N
Timing Reference
PLL Output
PLL Lock Indicator
Fractional-N
Divider
Voltage Controlled
Oscillator
Internal
Loop Filter
Phase
Comparator
Delta-Sigma
Modulator
Hardware Configuration
Hardware Control
CS2200-OTP
Fractional-N Frequency Synthesizer
Features
Delta-Sigma Fractional-N Frequency Synthesis
– Generates a Low Jitter 6 - 75 MHz Clock
Relative to 8 - 75 MHz Reference Clock
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM
One-Time Programmability
– Configurable Hardware Control Pins
– Configurable Auxiliary Output
Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2200-OTP is an extremely versatile system
clocking device that utilizes a programmable phase lock
loop. The CS2200-OTP is based on an analog PLL architecture comprised of a Delta-Sigma Fractional-N
Frequency Synthesizer. This architecture allows for frequency synthesis and clock generation from a stable
reference clock. The CS2200-OTP has many configuration options which are set once prior to runtime. At
runtime there are three hardware configuration pins
available for mode and feature selection.
The CS2200-OTP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) and Automotive
(-40°C to +85°C) grades. Customer development kits
are also available for custom device prototyp ing, small
production programming, and device evaluation.
Please see “Ordering Information” on page 23 for complete details.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY '10
DS842F2
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DC ELECTRICAL CHARACTERISTICS . ... ... .... ... ... ... .... ... ... .................................................................. 6
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
4. ARCHITECTURE OVERVIEW ............................................................................................................... 8
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 8
5. APPLICATIONS ..................................................................................................................................... 9
5.1 One Time Programmability .............................................................................................................. 9
5.2 Timing Reference Clock Input ..................... ..................................................................................... 9
5.2.1 Internal Timing Reference Clock Divider .. ... .... ... ... ... .... ... ... ..................................................... 9
5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 10
5.2.3 External Reference Clock (REF_CLK) .................................................................................. 10
5.3 Output to Input Frequency Ratio Configuration ............................................................................. 11
5.3.1 User Defined Ratio (RUD) ..................................................................................................... 11
5.3.2 Ratio Modifier (R-Mod) .......................................................................................................... 11
5.3.3 Effective Ratio (REFF) .......................................................................................................... 11
5.3.4 Ratio Configuration Summary ............................................................................................... 12
5.4 PLL Clock Output ........................................................................................................................... 13
5.5 Auxiliary Output ................. ... ... .... ... ... ....................................... ... ... ... .... ......................................... 14
5.6 Mode Pin Functionality ...................... ... ... ....................................... ... .... ... ... ... .... ... ... ...................... 14
5.6.1 M1 and M0 Mode Pin Functionality ....................................................................................... 14
5.6.2 M2 Mode Pin Functionality .................................................................................................... 15
5.6.2.1 M2 Configured as Output Disable .............................................................................. 15
5.6.2.2 M2 Configured as R-Mod Enable .............. ... .... ... ... ....................................... ... ... ... ... 15
5.6.2.3 M2 Configured as AuxOutSrc Override ..................................................................... 15
5.7 Clock Output Stability Considerations ......... ... ... ... .... ... ... ... .... ...................................... ... .... ... ......... 16
5.7.1 Output Switching ................................................................................................................... 16
5.7.2 PLL Unlock Conditions .......................................................................................................... 16
5.8 Required Power Up Sequencing for Programmed Devices .................. ......................................... 16
6. PARAMETER DESCRIPTIONS ........................................................................................................... 17
6.1 Modal Configuration Sets ..................... ... ....................................... ... .... ... ... ... .... ... ... ...................... 17
6.1.1 R-Mod Selection (RModSel[1:0]) ........................ ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ...17
6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) .................... ......................................... 18
6.2 Ratio 0 - 3 .. ... ....................................... ... .... ...................................... .... ... ...................................... 18
6.3 Global Configuration Parameters ................................................................................................... 18
6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 18
6.3.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 18
6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 19
6.3.4 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 19
7. CALCULATING THE USER DEFINED RATIO .................................................................................... 20
7.1 12.20 Format ........................ ... ....................................... ... .... ... ... ... ................................................ 20
8. PROGRAMMING INFORMATION ....................................................................................................
9. PACKAGE DIMENSIONS .................................................................................................................... 22
THERMAL CHARACTERISTICS ......................................................................................................... 22
10. ORDERING INFORMATION ........... ... ... ... ... .... ... ....................................... ... ... ... .... ... ... ... ... .... ... ......... 23
11. REVISION HISTORY ................................ ... .... ... ....................................... ... ... ... .... ... ... ... ................... 23
CS2200-OTP
.... 21
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
DS842F2 2
Figure 2. Delta-Sigma Fractional-N Frequency Synthesizer .......................................................................8
Figure 3. Internal Timing Reference Clock Divider ..................................................................................... 9
Figure 4. REF_CLK Frequency vs. a Fixed CLK_OUT ............................................................................. 10
Figure 5. External Component Requirements for Crystal Circuit .............................................................. 10
Figure 6. Ratio Feature Summary ............................................................................................................. 12
Figure 7. PLL Clock Output Options ......................................................................................................... 13
Figure 8. Auxiliary Output Selection .......................................................................................................... 14
Figure 9. M2 Mapping Options .................................................................................................................. 15
Figure 10. Parameter Configuration Sets .................................................................................................. 17
LIST OF TABLES
Table 1. Modal and Global Configuration ........................ .... ... ... ... .... ... ... ... ... .... ... ........................................ 9
Table 2. Ratio Modifier .............................................................................................................................. 11
Table 3. Example 12.20 R-Values ............................................................................................................ 20
CS2200-OTP
DS842F2 3
1. PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
XTO
CLK_OUT
GND
VD
XTI/REF_CLK
M2
M1
M0
AUX_OUT
TST_IN
Pin Name # Pin Description
VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.
GND 2 Ground (Input) - Ground reference.
CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.
AUX_OUT 4
TST_IN
XTO
XTI/REF_CLK
M2 8 Mode Select (Input) - M2 is a configurable mode selection pin.
M1 9 Mode Select (Input) - M1 is a configurable mode selection pin.
M0 10 Mode Select (Input) - M0 is a configurable mode selection pin.
Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on configuration.
5 Test Input (Input) - This pin is for factory test purposes and must be connected to GND for proper
operation.
Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -
6
XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input
7
clock. REF_CLK is an input for an externally generated low-jitter reference clock.
CS2200-OTP
4 DS842F2
2. TYPICAL CONNECTION DIAGRAM
2
1
GND
M2
M1
XTI/REF_CLK
TST_IN
XTO
CLK_OUT
AUX_OUT
0.1 µF
VD
+3.3 V
M0
Low-Jitter
Timing Reference
System Microcontroller
1 µF
1
or
2
REF_CLK
XTO
XTI
XTO
or
40 pF
x
40 pF
Crystal
To circuitry which requires
a low-jitter clock
N.C.
To other circuitry or
Microcontroller
Figure 1. Typical Connection Diagram
CS2200-OTP
CS2200-OTP
DS842F2 5
CS2200-OTP
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note ?)
Parameters Symbol Min Typ Max Units
DC Power Supply VD 3.1 3.3 3.5 V
Ambient Operating Temperature (Power Applied)
Commercial Grade
Automotive Grade
T
AC
T
AD
-10
-40
-
-
+70
+85
°C
°C
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits
may adversely affect device reliability.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply VD -0.3 6.0 V
Input Current I
Digital Input Voltage (Note 3)V
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
IN
IN
A
stg
-±10mA
-0.3 VD + 0.4 V
-55 125 °C
-65 150 °C
WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T
= -40°C to +85°C (Automotive Grade).
A
Parameters Symbol Min Typ Max Units
Power Supply Current - Unloaded (Note 4)I
Power Dissipation - Unloaded (Note 4)P
Input Leakage Current I
Input Capacitance I
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (I
Low-Level Output Voltage (I
= -1.2 mA) V
OH
= 1.2 mA) V
OH
D
D
IN
C
IH
IL
OH
OL
Notes: 3. To calculate the additional current consumption due to loading (per output pin), multiply clock output
frequency by load capacitance and power supply voltage.
For example,
f
CLK_OUT
(49.152 MHz) * CL (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to
these loading conditions on CLK_OUT.
-1218mA
-4060mW
--±10µA
-8-pF
70% - - VD
--30%VD
80% - - VD
--20%VD
6 DS842F2
CS2200-OTP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
= -40°C to +85°C (Automotive Grade); CL=15pF.
T
A
Parameters Symbol Conditions Min Typ Max Units
Crystal Frequency
Fundamental Mode XTAL
Reference Clock Input Frequency f
Reference Clock Input Duty Cycle D
Internal System Clock Frequency f
PLL Clock Output Frequency f
PLL Clock Output Duty Cycle t
Clock Output Rise Time t
Clock Output Fall Time t
Period Jitter t
Base Band Jitter (100 Hz to 40 kHz) (Notes 10, 11) - 50 - ps rms
Wide Band JItter (100 Hz Corner) (Notes 10, 12) - 175 - ps rms
PLL Lock Time - REF_CLK t
Output Frequency Synthesis Resolution (Note 15)f
f
XTAL
REF_CLK
REF_CLK
SYS_CLK
CLK_OUT
OD
OR
OF
JIT
LR
err
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
Measured at VD/2 45 50 55 %
20% to 80% of VD - 1.7 3.0 ns
80% to 20% of VD - 1.7 3.0 ns
(Note 10) - 70 - ps rms
f
REF_CLK
= 8 to 75 MHz - 1 3 ms
8
16
32
8
16
32
45 - 55 %
814MHz
6-75MHz
0-±0.5ppm
-
-
-
-
-
-
14
28
50
14
28
56
MHz
MHz
MHz
MHz
MHz
MHz
Notes: 4.
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.
5. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Inte rval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
6. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Inte rval Error taken with 3rd
order 100 Hz Highpass filter.
7. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
DS842F2 7
4. ARCHITECTURE OVERVIEW
Fractional-N
Divider
Timing Reference
Clock
PLL Output
Voltage Controlled
Oscillator
Internal
Loop Filter
Phase
Comparator
N
Delta-Sigma
Modulator
4.1 Delta-Sigma Fractional-N Frequency Synthesizer
The core of the CS2200 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to
quickly tune to a new frequency. In very simplistic terms, the Fractional-N Freq uency Synthesizer multiplies
the Timing Reference Clock by the value of N to generate the PLL out put clock. The desired output to input
clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 2).
The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase
reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fractional-N divided clock with the original timing reference and generates a control signal. The control signal is filtered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The
delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio betwee n the
reference clock and the VCO output (thus the duty cycle of the modulator sets the fractional value). This
allows the design to be optimized for very fast lock times for a wide rang e of outpu t freq uencies withou t the
need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference
clock should be stable and jitter-free.
CS2200-OTP
8 DS842F2
Figure 2. Delta-Sigma Fractional-N Frequency Synthesizer
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