I²C / SPI
Auxiliary
Output
6 to 75 MHz
PLL Output
3.3 V
I²C/SPI Software
Control
8 MHz to 75 MHz
Low-Jitter Timing
Reference
Output to Input
Clock Ratio
N
Timing Reference
PLL Output
PLL Lock Indicator
Fractional-N
Divider
Voltage Controlled
Oscillator
Internal
Loop Filter
Phase
Comparator
Delta-Sigma
Modulator
CS2200-CP
Fractional-N Frequency Synthesizer
Features
Delta-Sigma Fractional-N Frequency Synthesis
– Generates a Low Jitter 6 - 75 MHz Clock
from an 8 - 75 MHz Reference Clock
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM
I²C™ / SPI™ Control Port
Configurable Auxiliary Output
– Buffered Reference Clock
– PLL Lock Indication
– Duplicate PLL Output
Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2200-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop.
The CS2200-CP is based on an analog PLL architecture comprised of a Delta-Sigma Fractional-N
Frequency Synthesizer. This architecture allows for frequency synthesis and clock generation from a stable
reference clock.
The CS2200-CP supports both I²C and SPI for full software control.
The CS2200-CP is available in a 10-pin MSOP package
in Commercial (-10°C to +70°C) and Automotive (-40°C
to +85°C) grades.
Customer development kits are also available for device
evaluation. Please see “Ordering Information” on
page 25 for complete details.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY '10
DS759F2
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DC ELECTRICAL CHARACTERISTICS . ... ... .... ... ... ... .... ... ... ....................................... ... ... ... .... ... ... ... .... . 6
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ........................ ... ... ..................... 8
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ................................................. 9
4. ARCHITECTURE OVERVIEW ............................................................................................................. 10
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 10
5. APPLICATIONS ................................................................................................................................... 11
5.1 Timing Reference Clock Input ..................... ...................................... .... ... ... ... .... ... ... ... ... .... ............ 11
5.1.1 Internal Timing Reference Clock Divider .. ... .... ... ... ... .... ... ... ................................................... 11
5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 12
5.1.3 External Reference Clock (REF_CLK) .................................................................................. 12
5.2 Output to Input Frequency Ratio Configuration ............................................................................. 12
5.2.1 User Defined Ratio (RUD) ..................................................................................................... 12
5.2.2 Ratio Modifier (R-Mod) .......................................................................................................... 13
5.2.3 Effective Ratio (REFF) .......................................................................................................... 13
5.2.4 Ratio Configuration Summary ............................................................................................... 14
5.3 PLL Clock Output ........................................................................................................................... 14
5.4 Auxiliary Output ................. ... ... .... ... ... ....................................... ... ... ... .... ......................................... 15
5.5 Clock Output Stability Considerations ......... ... ... ... .... ... ... ... .... ...................................... ... .... ... ......... 15
5.5.1 Output Switching ................................................................................................................... 15
5.5.2 PLL Unlock Conditions .......................................................................................................... 15
5.6 Required Power Up Sequencing ................................................................. ... .... ... ... ... ... .... ... ......... 16
6. SPI / I²C CONTROL PORT ...................... ... ... .... ... ... ... .... ...................................... .... ... ... ... ... ................ 16
6.1 SPI Control ........................ ... ....................................... ... ... .... ... ... ................................................... 16
6.2 I²C Control .................. .... ... ... ... .... ... ....................................... ... ... ................................................... 16
6.3 Memory Address Pointer ............................................... ... .... ... ... ... ................................................ 18
6.3.1 Map Auto Increment .............................................................................................................. 18
7. REGISTER QUICK REFERENCE ........................................................................................................ 18
8. REGISTER DESCRIPTIONS ................................................................................................................ 19
8.1 Device I.D. and Revision (Address 01h) . .... ... ... ... .... ... ... ... .... ... ... .......................................... ... ...... 19
8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 19
8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 19
8.2 Device Control (Address 02h) ................. .............................................. ......................................... 19
8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 19
8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 19
8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 20
8.3 Device Configuration 1 (Address 03h) ........................................................................................... 20
8.3.1 R-Mod Selection (RModSel[2:0]) ........................ ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ...20
8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) .................... ......................................... 20
8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ............................ ............................ 21
8.4 Global Configuration (Address 05h) ............................................................................................... 21
8.4.1 Device Configuration Freeze (Freeze) .................................................................................. 21
8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ............................ ............................ 21
8.5 Ratio (Address 06h - 09h) .............................. ... ... .... ... ... ... ....................................... ... ... ................ 21
8.6 Function Configuration 1 (Address 16h) ........................................................ .... ... ... ... ... .... ... ... ...... 22
8.6.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 22
8.6.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 22
CS2200-CP
2 DS759F2
8.7 Function Configuration 2 (Address 17h) ........................................................ .... ... ... ... ... .... ... ... ...... 22
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 22
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 23
9.1 12.20 Format ........................ ... ....................................... ... .... ... ... ... ................................................ 23
10. PACKAGE DIMENSIONS ........................................ .... ... ... ... .... ... ... ... ... ............................................. 24
THERMAL CHARACTERISTICS ......................................................................................................... 24
11. ORDERING INFORMATION ........................................ ... ... ....................................... ... ... ... .... ... ......... 25
12. REFERENCES ....................... ... ... .... ... ... ... ... .... ... ... ....................................... ... ... .... ... ... ...................... 25
13. REVISION HISTORY ................................................................................. ... ... ... .... ... ... ... ................... 26
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5
Figure 2. Control Port Timing - I²C Format .................................................................................................. 8
Figure 3. Control Port Timing - SPI Format (Write Only) ............................................................................ 9
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 10
Figure 5. Internal Timing Reference Clock Divider ................................................................................... 11
Figure 6. REF_CLK Frequency vs. a Fixed CLK_OUT ............................................................................. 11
Figure 7. External Component Requirements for Crystal Circuit .............................................................. 12
Figure 8. Ratio Feature Summary ............................................................................................................. 14
Figure 9. PLL Clock Output Options ......................................................................................................... 14
Figure 10. Auxiliary Output Selection ........................... .......................................... ................................... 15
Figure 11. Control Port Timing in SPI Mode ............................................................................................. 17
Figure 12. Control Port Timing, I²C Write .................................................................................................. 17
Figure 13. Control Port Timing, I²C Aborted Write + Read .......................................................................17
CS2200-CP
LIST OF TABLES
Table 1. Ratio Modifier .............................................................................................................................. 13
Table 2. Example 12.20 R-Values ............................................................................................................ 23
DS759F2 3
1. PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
XTO
CLK_OUT
GND
VD
XTI/REF_CLK
AD0/CS
SCL/CCLK
SDA/CDIN
AUX_OUT
TST_IN
Pin Name # Pin Description
VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.
GND 2 Ground (Input) - Ground reference.
CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.
AUX_OUT
TST_IN
XTO
XTI/REF_CLK
AD0/CS
SCL/CCLK
SDA/CDIN
4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on register configuration.
5 Test Input (Input) - This pin is for factory test purposes and must be connected to GND for proper
operation.
67Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -
XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input
clock. REF_CLK is an input for an externally generated low-jitter reference clock.
8 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C
Mode. CS
9 Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI
mode.
10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data
line for the control port interface in SPI Mode.
is the chip select signal in SPI Mode.
CS2200-CP
4 DS759F2
2. TYPICAL CONNECTION DIAGRAM
2
1
GND
SCL/CCLK
SDA/CDIN
2 kΩ
XTI/REF_CLK
TST_IN
XTO
CLK_OUT
AUX_OUT
0.1 µF
VD
+3.3 V
Notes:
1. Resistors
required for I
2
C
operation.
2 kΩ
AD0/CS
Low-Jitter
Timing Reference
System MicroController
1 µF
Note
1
1
or
2
REF_CLK
XTO
XTI
XTO
or
40 pF
x
40 pF
Crystal
To circuitry which requires
a low-jitter clock
N.C.
To other circuitry or
Microcontroller
Figure 1. Typical Connection Diagram
CS2200-CP
CS2200-CP
DS759F2 5
CS2200-CP
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note 1)
Parameters Symbol Min Typ Max Units
DC Power Supply VD 3.1 3.3 3.5 V
Ambient Operating Temperature (Power Applied)
Commercial Grade
Automotive Grade
T
AC
T
AD
-10
-40
-
-
+70
+85
°C
°C
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits
may adversely affect device reliability.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply VD -0.3 6.0 V
Input Current I
Digital Input Voltage (Note 2)V
Ambient Operating Temperature (Power Applied) T
Storage Temperature T
IN
IN
A
stg
-±10mA
-0.3 VD + 0.4 V
-55 125 °C
-65 150 °C
WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T
= -40°C to +85°C (Automotive Grade).
A
Parameters Symbol Min Typ Max Units
Power Supply Current - Unloaded (Note 3)I
Power Dissipation - Unloaded (Note 3)P
Input Leakage Current I
Input Capacitance I
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (I
Low-Level Output Voltage (I
= -1.2 mA) V
OH
= 1.2 mA) V
OH
D
D
IN
C
IH
IL
OH
OL
Notes: 3. To calculate the additional current consumption due to loading (per output pin), multiply clock output
frequency by load capacitance and power supply voltage.
For example,
f
CLK_OUT
(49.152 MHz) * CL (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to
these loading conditions on CLK_OUT.
-1218mA
-4060mW
--±10µA
-8-pF
70% - - VD
--30%VD
80% - - VD
--20%VD
6 DS759F2
CS2200-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
= -40°C to +85°C (Automotive Grade); CL=15pF.
T
A
Parameters Symbol Conditions Min Typ Max Units
Crystal Frequency
Fundamental Mode XTAL
Reference Clock Input Frequency f
Reference Clock Input Duty Cycle D
Internal System Clock Frequency f
PLL Clock Output Frequency f
PLL Clock Output Duty Cycle t
Clock Output Rise Time t
Clock Output Fall Time t
Period Jitter t
Base Band Jitter (100 Hz to 40 kHz) (Notes 4, 5) - 50 - ps rms
Wide Band JItter (100 Hz Corner) (Notes 4, 6) - 175 - ps rms
PLL Lock Time - REF_CLK t
Output Frequency Synthesis Resolution (Note 7)f
f
XTAL
REF_CLK
REF_CLK
SYS_CLK
CLK_OUT
OD
OR
OF
JIT
LR
err
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
Measured at VD/2 45 50 55 %
20% to 80% of VD - 1.7 3.0 ns
80% to 20% of VD - 1.7 3.0 ns
(Note 4) - 70 - ps rms
f
REF_CLK
= 8 to 75 MHz - 1 3 ms
8
16
32
8
16
32
45 - 55 %
814MHz
6-75MHz
0-±0.5ppm
-
-
-
-
-
-
14
28
50
14
28
56
MHz
MHz
MHz
MHz
MHz
MHz
Notes: 4.
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.
5. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Inte rval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
6. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Inte rval Error taken with 3rd
order 100 Hz Highpass filter.
7. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
DS759F2 7
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT
t
buf
t
hdst
t
hdst
t
low
t
r
t
f
t
hdd
t
high
t
sud
t
sust
t
susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
VD
t
dpor
Figure 2. Control Port Timing - I²C Format
Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.
Parameter Symbol Min Max Unit
SCL Clock Frequency f
Bus Free-Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 8)t
SDA Setup Time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling t
Delay from Supply Voltage Stable to Control Port Ready t
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
ack
dpor
- 100 kHz
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
300 1000 ns
100 - µs
CS2200-CP
Notes: 8. Data must be held for sufficient time to bridge the transition time, t
, of SCL.
f
8 DS759F2
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
csh
t
spi
t
dpor
VD
Figure 3. Control Port Timing - SPI Format (Write Only)
Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
CCLK Edge to CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CS
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 10)t
Rise Time of CCLK and CDIN (Note 11)t
Fall Time of CCLK and CDIN (Note 11)t
Delay from Supply Voltage Stable to Control Port Ready t
Notes: 9.
Falling (Note 9)t
t
is only needed before first falling edge of CS after power is applied. t
spi
ccllk
spi
csh
css
scl
sch
dsu
dh
r2
f2
dpor
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For f
< 1 MHz.
cclk
-6MHz
500 - ns
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
- 100 ns
- 100 ns
100 - µs
= 0 at all other times.
spi
CS2200-CP
DS759F2 9
4. ARCHITECTURE OVERVIEW
Fractional-N
Divider
Timing Reference
Clock
PLL Output
Voltage Controlled
Oscillator
Internal
Loop Filter
Phase
Comparator
N
Delta-Sigma
Modulator
4.1 Delta-Sigma Fractional-N Frequency Synthesizer
The core of the CS2200 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to
quickly tune to a new frequency. In very simplistic terms, the Fractional-N Freq uency Synthesizer multiplies
the Timing Reference Clock by the value of N to generate the PLL out put clock. The desired output to input
clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 4).
The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase
reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fractional-N divided clock with the original timing reference and generates a control signal. The control signal is filtered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The
delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio betwee n the
reference clock and the VCO output (thus the one’s density of the modulator sets the fractional value). This
allows the design to be optimized for very fast lock times for a wide rang e of outpu t freq uencies withou t the
need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference
clock should be stable and jitter-free.
CS2200-CP
10 DS759F2
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer
5. APPLICATIONS
Figure 5. Internal Timing Reference Clock Divider
N
Internal Timing
Reference Clock
PLL Output
Fractional-N
Frequency
Synthesizer
Timing Reference
Clock Divider
÷1
÷2
÷4
XTI/REF_CLK
RefClkDiv[1:0]
8 MHz < SysClk < 14 MHz
8 MHz < RefClk <
Timing Reference Clock
50 MHz (XTI)
58 MHz (REF_CLK)
-80 -60 -40 -20 0 20 40 60 80
20
40
60
80
100
120
140
160
180
Normalized REF__CLK Frequency (kHz)
Typical Base Band Jitter (psec)
CLK__OUT Jitt er
-15 kHz +15 kHz
CLK__OUT
f
*32/N
Figure 6. REF_CLK Frequency vs. a Fixed CLK_OUT
fLf
RefClkfH
≤≤
fLf
CLK_OUT
31
32
----- -
15kHz+×=
12.288MHz 0.96875 15kHz+×=
11.919MHz=
fHf
CLK_OUT
32
32
----- -
15kHz–×=
12.288MHz 115kHz+×=
12.273MHz=
5.1 Timing Reference Clock Input
The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an
external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL output the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock
directly affects the performance of the PLL and hence the quality of the PLL output.
5.1.1 Internal Timing Reference Clock Divider
The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency th an what is allowed on
the XTI/REF_CLK pin. The CS2200 supports the wider external frequency range by offering an internal
divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls
within the valid range as indicated in “AC Electrical Characteristics” on page 7.
CS2200-CP
It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent
upon its configuration as either a crystal connection or external clock input. See the “AC Electrical Char-
acteristics” on page 7 for more details.
For the lowest possible output jitter, attention should be paid to th e absolute frequency of the Timing Reference Clock relative to the PLL Output frequency ( CLK_OUT ). To minimize outp ut jitter, the Timing Reference Clock frequency should be chosen such that f
where N is an integer. Figure 6 shows the effect of varying the RefClk frequency around f
It should be noted that there will be a jitter null at the zero point when N = 32 (not shown in Figure 6). An
example of how to determine the range of RefClk frequencies around 12 MHz to be used in order to
achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows:
where:
and
DS759F2 11
Referenced Control Register Location
RefClkDiv[1:0].......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 22
is at least +/-15 kHz from f
RefClk
CLK_OUT
CLK_OUT
*N/32
*N/32.
5.1.2 Crystal Connections (XTI and XTO)
XTI XTO
40 pF 40 pF
Figure 7. External Component Requirements for Crystal Circuit
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 7. As shown,
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer
to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range.
5.1.3 External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the
reference clock source and XTO should be left unconnected or pulled low through a 47 kΩ resistor to
GND.
CS2200-CP
5.2 Output to Input Frequency Ratio Configuration
5.2.1 User Defined Ratio (RUD)
The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number, stored in the Ratio register set,
which determines the basis for the desired input to output clock ratio. The 32-bit R
12.20 format where the 12 MSBs represent the integer binary portion while the remaining 20 LSBs represent the fractional binary portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Calculating the User Defined Ratio” on page 23 for more
information.
The status of internal dividers, such as the internal timing reference clock divider, are automatically taken
into account. Therefore R
Referenced Control Register Location
Ratio......................................“Ratio (Address 06h - 09h)” on page 21
is simply the desired ratio of the output to input clock frequencies.
UD
is represented in a
UD
12 DS759F2
5.2.2 Ratio Modifier (R-Mod)
The Ratio Modifier is used to internally multiply/divide the RUD (the Ratio stored in the register space remains unchanged). The available options for R
The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio
(R
), see “Effective Ratio (REFF)” on page 13. If R-Mod is not desired, RModSel[2:0] should be left at
EFF
its default value of ‘000’, which corresponds to an R-Mod value of 1, thereby effectively disabling the ratio
modifier.
RModSel[2:0] Ratio Modifier
000
001
010
011
100
101
110
111
are summarized in Table 1 on page 13.
MOD
Table 1. Ratio Modifier
CS2200-CP
1
2
4
8
0.5
0.25
0.125
0.0625
Referenced Control Register Location
Ratio......................................“Ratio (Address 06h - 09h)” on page 21
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 20
5.2.3 Effective Ratio (R
The Effective Ratio (R
previously described. R
R
= RUD • R
EFF
To simplify operation the device handles some of the ratio calculation functions automatically (such as
when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need
to be altered to account for internal dividers.
Ratio modifiers which would produce an overflow or truncation of R
if R
is 1024 an R
UD
12.20 format. In all cases, the maximum and minimum allowable values for R
quency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on
page 7.
MOD
MOD
)
EFF
) is an internal calculation comprised of RUD and the appropriate modifiers, as
EFF
is calculated as follows:
EFF
should not be used; For example
of 8 would produce an R
value of 8192 which exceeds the 4096 limit of the
EFF
EFF
are dictated by the fre-
EFF
DS759F2 13
5.2.4 Ratio Configuration Summary
Effective Ratio R
EFF
Ratio Format
SysClk
PLL Outpu
Frequency
Synthesizer
R Correction
N
Ratio 12.20
Ratio
Modifier
RModSel[2:0]
RefClkDiv[1:0]
Timing Reference Clock
(XTI/REF_CLK)
Divide
RefClkDiv[1:0]
User Defined Ratio R
UD
PLL Locked/Unlocked
PLL Output
2:1 Mux
ClkOutDis
2:1 Mux
ClkOutUnl
0
PLL Clock Output Pin
(CLK_OUT)
0
1
0
1
PLL Clock Output
PLLClkOut
The RUD is the user defined ratio stored in the register space. R-Mod is applied if selected. The user defined ratio, and ratio modifier make up the effective ratio R
output to input clock ratio. The effective ratio is then corrected for the internal dividers. The conceptual
diagram in Figure 8 summarizes the features involved in the calculation of the ratio values used to generate the fractional-N value which controls the Frequency Synthesizer.
Figure 8. Ratio Feature Summary
CS2200-CP
, the final calculation used to determine the
EFF
5.3 PLL Clock Output
14 DS759F2
Referenced Control Register Location
Ratio......................................“Ratio (Address 06h - 09h)” on page 21
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 20
RefClkDiv[1:0].......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 22
The PLL clock output pin (CLK_OUT) provides a buffered version of the outp ut of the frequency synthesizer.
The driver can be set to high-impedance with the ClkOutDis bit.
The output from the PLL automatically drives a sta tic low condition while the PLL is un-locked (when the
clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state
CLK_OUT may then be unreliable during an unlock condition.
Referenced Control Register Location
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 22
ClkOutDis..............................“PLL Clock Output Disable (ClkOutDis)” on p age 20
Figure 9. PLL Clock Output Options
5.4 Auxiliary Output
3:1 Mux
Auxiliary Output Pin
(AUX_OUT)
AuxOutDis
AuxOutSrc[1:0]
AuxLockCfg
Timing Reference Clock
(RefClk)
PLL Clock Output
(PLLClkOut)
PLL Lock/Unlock Indication
(Lock)
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 10, to one of three signals: reference clock (RefClk), additional PLL clock output (CLK_OUT) , or a PLL lock indicator (Lock). The mux is controlled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control
the output driver type and polarity of the LOCK signal (see section 8.6.1 on page 22). If AUX_OUT is set to
CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The
driver for the pin can be set to high-impedance using the AuxOutDis bit.
CS2200-CP
Figure 10. Auxiliary Output Selection
Referenced Control Register Location
AuxOutSrc[1:0]......................“Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 20
AuxOutDis.............................“Auxiliary Output Disable (AuxOutDis)” on page 19
AuxLockCfg...........................“AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 22
5.5 Clock Output Stability Considerations
5.5.1 Output Switching
CS2200 is designed such that re-configuration of the clock routing functions do not result in a partial clock
period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an
output, changing the auxiliary output source between REF_CLK and CLK_OUT, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period.
The following exceptions/limitations exist:
• Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 11 (unlock indicator)
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
• Changing the ClkOutUnl bit while the PLL is in operation.
When any of these exceptions occur, a partial clock period on the output may result.
5.5.2 PLL Unlock Conditions
DS759F2 15
Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the presence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go unlocked:
• Changes made to the registers which affect the Fraction-N value that is used by the Frequency Syn-
CS2200-CP
thesizer. This includes all the bits shown in Figure 8 on page 14.
• Any discontinuities on the Timing Reference Clock, REF_CLK.
5.6 Required Power Up Sequencing
• Apply power to the device. The output pins will remain low until the device is configured with a valid ratio
via the control port.
• Write the desired operational configurations. The EnDevCfg1 and EnDevCfg2 bits must be set to 1 dur-
ing the initialization register writes; the order does not matter.
– The Freeze bit may be set prior to this step and cleared afterward to ensure all settings take effect
at the same time.
6. SPI / I²C CONTROL PORT
The control port is used to access the registers and allows the device to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to device inpu ts
and outputs. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
The control port operates wit h eith er t he SPI o r I²C inter face , with the CS 2200 ac ting a s a s lav e de vice. SPI Mo de
is selected if there is a high-to-low transition on the AD0/CS
the AD0/CS
In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.
pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state.
pin after power-up. I²C Mode is selected by connecting
WARNING:All “Reserved” registers must maintain their default state to ensure proper functional operation.
Referenced Control Register Location
EnDevCfg1............................“Enable Device Configuration Registers 1 (EnDevCfg1)” on page 21
EnDevCfg2............................“Enable Device Configuration Registers 2 (EnDevCfg2)” section on page 21
6.1 SPI Control
In SPI Mode, CS is the chip select signal; CCLK is the control port bit clock (sour ced from a microcontroller),
and CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The
device only supports write operations.
Figure 11 shows the operation of the control port in SPI Mode. To write to a register , bring CS
eight bits on CDIN form the chip address and must be 10011110. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be upd ated. The next eight bits ar e
the data which will be placed into the register designated by the MAP.
There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the
MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will automatically increment after each byte is read or written, allowing block writes of successive registers.
low. The first
6.2 I²C Control
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL.
There is no CS
to VD or GND as appropriate. The stat e of the AD0 pin should be maintained throughout operation of the
device.
pin. The AD0 pin forms the least-significant bit of the chip address and should be connected
16 DS759F2
CS2200-CP
4 5 6 7
CCLK
CHIP ADDRESS MAP BYTE DATA
1 0 0 1 1 1 1 0
CDIN
INCR 6 5 4 3 2 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 10 11 13 14 15
DATA +n
CS
7 6 1 0
Figure 11. Control Port Timing in SPI Mode
4 5 6 7 24 25
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA
DATA +1
START
ACK
STOP
ACKACKACK
1 0 0 1 1 1 AD0 0
SDA
INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 2826
DATA +n
Figure 12. Control Port Timing, I²C Write
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
1 0 0 1 1 1 AD0 0
SDA
1 0 0 1 1 1 AD0 1
CHIP ADDRESS (READ)
START
INCR 6 5 4 3 2 1 0
7 0 7 0 7 0
NO
16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24
26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 13. Control Port Timing, I²C Aborted Write + Read
The signal timings for a read and write cycle are sh own in Figure 12 and Figure 13. A Start condition is de-
fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
a Start condition consists of the 7-bit chip address field and a R/W
bit (high for a read, low for a write). The
upper 6 bits of the 7-bit address field are fixed at 100111 followed by the logic state of the AD0 pin. The
eighth bit of the address is the R/W
bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or
writes of consecutive registers. Each byte is sepa rated by an acknowledge bit. The ACK bit is output from
the
CS2200 after each input byte is read and is input from the microcontroller after each transmitted byte.
CS2200 after
Since the read operation cannot set the MAP, an aborted write operation is u sed a s a pr eamble. As sho wn
in Figure 12, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100111x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
DS759F2 17
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100111x1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
6.3 Memory Address Pointer
The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read
or written. Refer to the pseudocode above for implementation details.
6.3.1 Map Auto Increment
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto increment after each byte is read or written, allowing block reads or writes of successive registers.
CS2200-CP
7. REGISTER QUICK REFERENCE
This table shows the register and bit names with their associated default values.
EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.
WARNING:All “Reserved” registers must maintain their default state to ensure proper functional operation.
Adr Name 7 6 5 4 3 2 1 0
01h
Device ID Device4 Device3 Device2 Device1 Device0 Revision2 Revision1 Revision0
p19
02h
Device Ctrl Unlock Reserved Reserved Reserved Reserved Reserved AuxOutDis ClkOutDis
p19
03h
Device Cfg 1 RModSel2 RModSel1 RModSel0 Reserved Reserved AuxOutSrc1 AuxOutSrc0 EnDevCfg1
p20
05h
Global Cfg Reserved Reserved Reserved Reserved Freeze Reserved Reserved EnDevCfg2
p21
06h
-
32-Bit Ratio
09h
16h
Funct Cfg 1 Reserved AuxLockCfg Reserved RefClkDiv1 RefClkDiv0 Reserved Reserved Reserved
p22
17h
Funct Cfg 2 Reserved Reserved Reserved ClkOutUnl Reserved Reserved Reserved Reserved
p22
00000xxx
xxx00000
00000000
00000000
MSB ........................................................................................................................... MSB-7
MSB-8 ........................................................................................................................... MSB-15
LSB+15 ........................................................................................................................... LSB+8
LSB+7 ...........................................................................................................................LSB
00000000
00000000
18 DS759F2
CS2200-CP
8. REGISTER DESCRIPTIONS
In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Reserved” registers must maintain their default state to ensure proper functional operation. The default state of each
bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register
Quick Reference” on page 18.
Control port mode is entered when the device recognizes a valid chip address input on its I²C/SPI serial control pins
and the EnDevCfg1 and EnDevCfg2 bits are set to 1.
8.1 Device I.D. and Revision (Address 01h)
76543210
Device4 Device3 Device2 Device1 Device0 Revision2 Revision1 Revision0
8.1.1 Device Identification (Device[4:0]) - Read Only
I.D. code for the CS2200.
Device[4:0] Device
00000 CS2200.
8.1.2 Device Revision (Revision[2:0]) - Read Only
CS2200 revision level.
REVID[2:0] Revision Level
100 B2 and B3
110 C1
8.2 Device Control (Address 02h)
76543210
Unlock Reserved Reserved Reserved Reserved Reserved AuxOutDis ClkOutDis
8.2.1 Unlock Indicator (Unlock) - Read Only
Indicates the lock state of the PLL.
Unlock PLL Lock State
0 PLL is Locked.
1 PLL is Unlocked.
8.2.2 Auxiliary Output Disable (AuxOutDis)
This bit controls the output driver for the AUX_OUT pin.
AuxOutDis Output Driver State
0 AUX_OUT output driver enabled.
1 AUX_OUT output driver set to high-impedance.
Application: “Auxiliary Output” on page 15
DS759F2 19
CS2200-CP
8.2.3 PLL Clock Output Disable (ClkOutDis)
This bit controls the output driver for the CLK_OUT pin.
ClkOutDis Output Driver State
0 CLK_OUT output driver enabled.
1 CLK_OUT output driver set to high-impedance.
Application: “PLL Clock Output” on page 14
8.3 Device Configuration 1 (Address 03h)
76543210
RModSel2 RModSel1 RModSel0 Reserved Reserved AuxOutSrc1 AuxOutSrc0 EnDevCfg1
8.3.1 R-Mod Selection (RModSel[2:0])
Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N.
RModSel[2:0] R-Mod Selection
000 Left-shift R-value by 0 (x 1).
001 Left-shift R-value by 1 (x 2).
010 Left-shift R-value by 2 (x 4).
011 Left-shift R-value by 3 (x 8).
100 Right-shift R-value by 1 (÷ 2).
101 Right-shift R-value by 2 (÷ 4).
110 Right-shift R-value by 3 (÷ 8).
111 Right-shift R-value by 4 (÷ 16).
Application: “Ratio Modifier (R-Mod)” on page 13
8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0] Auxiliary Output Source
00 RefClk.
01 Reserved.
10 CLK_OUT.
11 PLL Lock Status Indicator.
Application: “Auxiliary Output” on page 15
Note: When set to 11, AuxLckCfg sets the polarity and driver type. See “AUX PLL Lock Output Config-
uration (AuxLockCfg)” on page 22.
20 DS759F2
CS2200-CP
8.3.3 Enable Device Configuration Registers 1 (EnDevCfg 1)
This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the co ntrol por t acce ss seq uen ce, h owever they mu st
both be set before normal operation can occur.
EnDevCfg1 Register State
0 Disabled.
1 Enabled.
Application: “SPI / I²C Control Port” on page 16
Note: EnDevCfg2 must also be set to enable control port mode. See “SPI / I²C Control Port” on
page 16.
8.4 Global Configuration (Address 05h)
76543210
Reserved Reserved Reserved Reserved Freeze Reserved Reserved EnDevCfg2
8.4.1 Device Configuration Freeze (Freeze)
Setting this bit allows writes to the Device Control and Device Configuration registers (ad dress 02h - 04h)
but keeps them from taking effect until this bit is cleared.
FREEZE Device Control and Configuration Registers
0 Register changes take effect immediately.
1
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the co ntrol por t acce ss seq uen ce, h owever they mu st
both be set before normal operation can occur.
EnDevCfg2 Register State
0 Disabled.
1 Enabled.
Application: “SPI / I²C Control Port” on page 16
Note: EnDevCfg1 must also be set to enable control port mode. See “SPI / I²C Control Port” on
page 16.
8.5 Ratio (Address 06h - 09h)
76543210
MSB ............................................................................................................................ MSB-7
MSB-8 ............................................................................................................................ MSB-15
LSB+15 ............................................................................................................................ LSB+8
LSB+7 ............................................................................................................................ LSB
These registers contain the User Defined Ratio as shown in the “Register Quick Reference” section on
page 18. These 4 registers form a single 32-bit ratio value as shown above. See “Output to Input Fr equency
Ratio Configuration” on page 12 and “Calculating the User De fined Ratio” on page 23 for more details.
DS759F2 21
CS2200-CP
8.6 Function Configuration 1 (Address 16h)
76543210
Reserved AuxLockCfg Reserved RefClkDiv1 RefClkDiv0 Reserved Reserved Reserved
8.6.1 AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
AuxLockCfg AUX_OUT Driver Configuration
0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
1 Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
Application: “Auxiliary Output” on page 15
Note: AUX_OUT is an unlock indicator, signalling an error co ndition when the PLL is u nlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
8.6.2 Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
RefClkDiv[1:0] Reference Clock Input Divider REF_CLK Frequency Range
00 ÷4. 32 MHz to 56 MHz (50 MHz with XTI)
01 ÷ 2. 16 MHz to 28 MHz
10 ÷ 1. 8 MHz to 14 MHz
11 Reserved.
Application: “Internal Timing Reference Clock Divider” on page 11
8.7 Function Configuration 2 (Address 17h)
76543210
Reserved Reserved Reserved ClkOutUnl Reserved Reserved Reserved Reserved
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl Clock Output Enable Status
0 Clock outputs are driven ‘low’ when PLL is unlocked.
1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
Application: “PLL Clock Output” on page 14
22 DS759F2
CS2200-CP
9. CALCULATING THE USER DEFINED RATIO
Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User
Defined Ratio. This section is for those who are not interested in the software or who are developing their
systems without the aid of the evaluation kit.
Most calculators do not interpr et the fixe d point bina ry representation which the CS2200 uses to define the output
to input clock ratio (see Section 5.2.1 on page 12); However, with a simple conversion we can use these tools to
generate a binary or hex value which can be written to the Ratio register.
9.1 12.20 Format
To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desir ed output clock frequency by the given input clock (RefClk). Then multiply the desired ratio by the scaling factor of 2
scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and
write to the register. A few examples have been provided in Table 2.
Scaled Decimal
Desired Output to Input Clock Ratio
(output clock/input clock)
12.288 MHz/10 MHz=1.2288
11 .2896 MHz/44.1 kHz=256
Table 2. Example 12.20 R-Values
Representation =
(output clock/input clock)
1288490 00 13 A9 2A
268435456 10 00 00 00
• 2
Hex Representation of
20
Binary R
20
to get the
UD
DS759F2 23
10.PACKAGE DIMENSIONS
10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1)
E
N
1
23
e
b
A1
A2
A
D
SEATING
PLANE
E1
1
L
SIDE VIEW
END VIEW
TOP VIEW
∝
L1
c
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.0433 -- -- 1.10
A1 0 -- 0.0059 0 -- 0.15
A2 0.0295 -- 0.0374 0.75 -- 0.95
b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5
c 0.0031 -- 0.0091 0.08 -- 0.23
D -- 0.1181 BSC -- -- 3.00 BSC -- 2
E -- 0.1929 BSC -- -- 4.90 BSC --
E1 -- 0.1181 BSC -- -- 3.00 BSC -- 3
e -- 0.0197 BSC -- -- 0.50 BSC -L 0.0157 0.0236 0.0315 0.40 0.60 0.80
L1 -- 0.0374 REF -- -- 0.95 REF --
CS2200-CP
Notes: 1. Reference document: JEDEC MO-187
2. D does not include mold flash or protrusions which is 0.15 mm max. per side.
3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side.
4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
5. Exceptions to JEDEC dimension.
THERMAL CHARACTERISTICS
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance JEDEC 2-Layer
24 DS759F2
JEDEC 4-Layer
θ
JA
θ
JA
-
-
170
100
-
-
°C/W
°C/W
11.ORDERING INFORMATION
CS2200-CP
Product Description Package
CS2200-CP Clocking Device 10L-MSOP Yes
CS2200-CP Clocking Device 10L-MSOP Yes -10° to +70°C
CS2200-CP Clocking Device 10L-MSOP Yes
CS2200-CP Clocking Device 10L-MSOP Yes -40° to +85°C
CDK2000 Evaluation Platform - Yes - - - CDK2000-CLK
Pb-Free Grade
Commercial
Automotive
Temp Range Container
-10° to +70°C Rail CS2200CP-CZZ
Tape and
Reel
-40° to +85°C Rail CS2200CP-DZZ
Tape and
Reel
Order#
CS2200CP-CZZR
CS2200CP-DZZR
12.REFERENCES
1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measurements Jitter performance specifications,” May 2007.
2. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998.
http://www.semiconductors.philips.com
13.REVISION HISTORY
Release Changes
F1 Updated Period Jitter specification in “AC Electrical Characteristics” on page 7.
Updated Crystal and Ref Clock Frequency specifications in “AC Electrical Characteristics” on page 7.
Updated “Internal Timing Reference Clock Divider” on page 11 and added Figure 6 on page 11.
F2 Updated to add Automotive Grade temperature ranges and ordering options.
DS759F2 25
CS2200-CP
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without noti ce and is provided “AS IS” wi thout war ranty of any kind (express or impli ed). Cust omers ar e advised t o obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowled gment, including tho se pertaining to warra nty, indemnification, an d limitation of liability. No responsibility is assumed by Cirrus
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IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
INDEMNIFY CIRRUS, ITS OFFICERS, DI RECTORS, EMPL OYEES, DIST RIBUT ORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES .
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trade marks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
26 DS759F2
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