Cirrus Logic CS2200-CP User Manual

I²C / SPI

Auxiliary

Output

6 to 75 MHz

PLL Output

3.3 V

I²C/SPI Software

Control

8 MHz to 75 MHz
Low-Jitter Timing

Reference

Output to Input

Clock Ratio

N

Timing Reference
PLL Output
PLL Lock Indicator

Fractional-N

Divider

Voltage Controlled

Oscillator

Internal

Loop Filter

Phase

Comparator

Delta-Sigma

Modulator

CS2200-CP

Fractional-N Frequency Synthesizer

Features

 Delta-Sigma Fractional-N Frequency Synthesis

– Generates a Low Jitter 6 - 75 MHz Clock

from an 8 - 75 MHz Reference Clock

 Highly Accurate PLL Multiplication Factor

– Maximum Error Less Than 1 PPM

 I²C™ / SPI™ Control Port
 Configurable Auxiliary Output

– Buffered Reference Clock
– PLL Lock Indication
– Duplicate PLL Output

 Flexible Sourcing of Reference Clock

– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal

 Minimal Board Space Required

– No External Analog Loop-filter

Components

General Description

The CS2200-CP is an extremely versatile system clock­ing device that utilizes a programmable phase lock loop.
The CS2200-CP is based on an analog PLL architec­ture comprised of a Delta-Sigma Fractional-N
Frequency Synthesizer. This architecture allows for fre­quency synthesis and clock generation from a stable
reference clock.

The CS2200-CP supports both I²C and SPI for full soft­ware control.

The CS2200-CP is available in a 10-pin MSOP package
in Commercial (-10°C to +70°C) and Automotive (-40°C
to +85°C) grades.

Customer development kits are also available for device
evaluation. Please see “Ordering Information” on

page 25 for complete details.

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2010

(All Rights Reserved)

MAY '10

DS759F2

TABLE OF CONTENTS

1. PIN DESCRIPTION ................................................................................................................................. 4

2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5

3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6

RECOMMENDED OPERATING CONDITIONS .................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6

DC ELECTRICAL CHARACTERISTICS . ... ... .... ... ... ... .... ... ... ....................................... ... ... ... .... ... ... ... .... . 6

AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7

CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ........................ ... ... ..................... 8

CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ................................................. 9

4. ARCHITECTURE OVERVIEW ............................................................................................................. 10

4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 10

5. APPLICATIONS ................................................................................................................................... 11

5.1 Timing Reference Clock Input ..................... ...................................... .... ... ... ... .... ... ... ... ... .... ............ 11

5.1.1 Internal Timing Reference Clock Divider .. ... .... ... ... ... .... ... ... ................................................... 11

5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 12

5.1.3 External Reference Clock (REF_CLK) .................................................................................. 12

5.2 Output to Input Frequency Ratio Configuration ............................................................................. 12

5.2.1 User Defined Ratio (RUD) ..................................................................................................... 12

5.2.2 Ratio Modifier (R-Mod) .......................................................................................................... 13

5.2.3 Effective Ratio (REFF) .......................................................................................................... 13

5.2.4 Ratio Configuration Summary ............................................................................................... 14

5.3 PLL Clock Output ........................................................................................................................... 14

5.4 Auxiliary Output ................. ... ... .... ... ... ....................................... ... ... ... .... ......................................... 15

5.5 Clock Output Stability Considerations ......... ... ... ... .... ... ... ... .... ...................................... ... .... ... ......... 15

5.5.1 Output Switching ................................................................................................................... 15

5.5.2 PLL Unlock Conditions .......................................................................................................... 15

5.6 Required Power Up Sequencing ................................................................. ... .... ... ... ... ... .... ... ......... 16

6. SPI / I²C CONTROL PORT ...................... ... ... .... ... ... ... .... ...................................... .... ... ... ... ... ................ 16

6.1 SPI Control ........................ ... ....................................... ... ... .... ... ... ................................................... 16

6.2 I²C Control .................. .... ... ... ... .... ... ....................................... ... ... ................................................... 16

6.3 Memory Address Pointer ............................................... ... .... ... ... ... ................................................ 18

6.3.1 Map Auto Increment .............................................................................................................. 18

7. REGISTER QUICK REFERENCE ........................................................................................................ 18

8. REGISTER DESCRIPTIONS ................................................................................................................ 19

8.1 Device I.D. and Revision (Address 01h) . .... ... ... ... .... ... ... ... .... ... ... .......................................... ... ...... 19

8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 19

8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 19

8.2 Device Control (Address 02h) ................. .............................................. ......................................... 19

8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 19

8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 19

8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 20

8.3 Device Configuration 1 (Address 03h) ........................................................................................... 20

8.3.1 R-Mod Selection (RModSel[2:0]) ........................ ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ...20

8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) .................... ......................................... 20

8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ............................ ............................ 21

8.4 Global Configuration (Address 05h) ............................................................................................... 21

8.4.1 Device Configuration Freeze (Freeze) .................................................................................. 21

8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ............................ ............................ 21

8.5 Ratio (Address 06h - 09h) .............................. ... ... .... ... ... ... ....................................... ... ... ................ 21

8.6 Function Configuration 1 (Address 16h) ........................................................ .... ... ... ... ... .... ... ... ...... 22

8.6.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 22

8.6.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 22

CS2200-CP

2 DS759F2

8.7 Function Configuration 2 (Address 17h) ........................................................ .... ... ... ... ... .... ... ... ...... 22

8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 22

9. CALCULATING THE USER DEFINED RATIO .................................................................................... 23

9.1 12.20 Format ........................ ... ....................................... ... .... ... ... ... ................................................ 23

10. PACKAGE DIMENSIONS ........................................ .... ... ... ... .... ... ... ... ... ............................................. 24

THERMAL CHARACTERISTICS ......................................................................................................... 24

11. ORDERING INFORMATION ........................................ ... ... ....................................... ... ... ... .... ... ......... 25

12. REFERENCES ....................... ... ... .... ... ... ... ... .... ... ... ....................................... ... ... .... ... ... ...................... 25

13. REVISION HISTORY ................................................................................. ... ... ... .... ... ... ... ................... 26

LIST OF FIGURES

Figure 1. Typical Connection Diagram ........................................................................................................ 5

Figure 2. Control Port Timing - I²C Format .................................................................................................. 8

Figure 3. Control Port Timing - SPI Format (Write Only) ............................................................................ 9

Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 10

Figure 5. Internal Timing Reference Clock Divider ................................................................................... 11

Figure 6. REF_CLK Frequency vs. a Fixed CLK_OUT ............................................................................. 11

Figure 7. External Component Requirements for Crystal Circuit .............................................................. 12

Figure 8. Ratio Feature Summary ............................................................................................................. 14

Figure 9. PLL Clock Output Options ......................................................................................................... 14

Figure 10. Auxiliary Output Selection ........................... .......................................... ................................... 15

Figure 11. Control Port Timing in SPI Mode ............................................................................................. 17

Figure 12. Control Port Timing, I²C Write .................................................................................................. 17

Figure 13. Control Port Timing, I²C Aborted Write + Read .......................................................................17

CS2200-CP

LIST OF TABLES

Table 1. Ratio Modifier .............................................................................................................................. 13

Table 2. Example 12.20 R-Values ............................................................................................................ 23

DS759F2 3

1. PIN DESCRIPTION

1
2
3
4
5

6

7

8

9

10

XTO

CLK_OUT

GND

VD

XTI/REF_CLK

AD0/CS

SCL/CCLK

SDA/CDIN

AUX_OUT

TST_IN

Pin Name # Pin Description

VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.
GND 2 Ground (Input) - Ground reference.
CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.

AUX_OUT

TST_IN

XTO
XTI/REF_CLK

AD0/CS

SCL/CCLK

SDA/CDIN

4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,

or a status signal, depending on register configuration.

5 Test Input (Input) - This pin is for factory test purposes and must be connected to GND for proper

operation.

67Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -

XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input
clock. REF_CLK is an input for an externally generated low-jitter reference clock.

8 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C

Mode. CS

9 Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI

mode.

10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data

line for the control port interface in SPI Mode.

is the chip select signal in SPI Mode.

CS2200-CP

4 DS759F2

2. TYPICAL CONNECTION DIAGRAM

2

1

GND

SCL/CCLK
SDA/CDIN

2 kΩ

XTI/REF_CLK

TST_IN

XTO

CLK_OUT

AUX_OUT

0.1 µF

VD

+3.3 V

Notes:

1. Resistors

required for I

2

C

operation.

2 kΩ

AD0/CS

Low-Jitter

Timing Reference

System MicroController

1 µF

Note

1

1

or

2

REF_CLK
XTO

XTI
XTO

or

40 pF

x

40 pF

Crystal

To circuitry which requires

a low-jitter clock

N.C.

To other circuitry or

Microcontroller

Figure 1. Typical Connection Diagram

CS2200-CP

CS2200-CP

DS759F2 5

CS2200-CP

3. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V; all voltages with respect to ground. (Note 1)

Parameters Symbol Min Typ Max Units

DC Power Supply VD 3.1 3.3 3.5 V
Ambient Operating Temperature (Power Applied)

Commercial Grade

Automotive Grade

T

AC

T

AD

-10

-40

-

-

+70
+85

°C
°C

Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits

may adversely affect device reliability.

ABSOLUTE MAXIMUM RATINGS

GND = 0 V; all voltages with respect to ground.

Parameters Symbol Min Max Units

DC Power Supply VD -0.3 6.0 V
Input Current I
Digital Input Voltage (Note 2)V
Ambient Operating Temperature (Power Applied) T
Storage Temperature T

IN

IN
A

stg

-±10mA

-0.3 VD + 0.4 V

-55 125 °C

-65 150 °C

WARNING:Operation at or beyond these limits may result in permanent damage to the device.

Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin.

DC ELECTRICAL CHARACTERISTICS

Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
T

= -40°C to +85°C (Automotive Grade).

A

Parameters Symbol Min Typ Max Units

Power Supply Current - Unloaded (Note 3)I
Power Dissipation - Unloaded (Note 3)P
Input Leakage Current I
Input Capacitance I
High-Level Input Voltage V
Low-Level Input Voltage V
High-Level Output Voltage (I

Low-Level Output Voltage (I

= -1.2 mA) V

OH

= 1.2 mA) V

OH

D

D

IN

C

IH
IL

OH
OL

Notes: 3. To calculate the additional current consumption due to loading (per output pin), multiply clock output

frequency by load capacitance and power supply voltage.
For example,

f

CLK_OUT

(49.152 MHz) * CL (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to

these loading conditions on CLK_OUT.

-1218mA

-4060mW

--±10µA

-8-pF

70% - - VD

--30%VD

80% - - VD

--20%VD

6 DS759F2

CS2200-CP

AC ELECTRICAL CHARACTERISTICS

Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);

= -40°C to +85°C (Automotive Grade); CL=15pF.

T

A

Parameters Symbol Conditions Min Typ Max Units

Crystal Frequency
Fundamental Mode XTAL

Reference Clock Input Frequency f

Reference Clock Input Duty Cycle D
Internal System Clock Frequency f
PLL Clock Output Frequency f
PLL Clock Output Duty Cycle t
Clock Output Rise Time t
Clock Output Fall Time t
Period Jitter t
Base Band Jitter (100 Hz to 40 kHz) (Notes 4, 5) - 50 - ps rms
Wide Band JItter (100 Hz Corner) (Notes 4, 6) - 175 - ps rms
PLL Lock Time - REF_CLK t
Output Frequency Synthesis Resolution (Note 7)f

f

XTAL

REF_CLK

REF_CLK
SYS_CLK
CLK_OUT

OD
OR
OF
JIT

LR
err

RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00

RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00

Measured at VD/2 45 50 55 %
20% to 80% of VD - 1.7 3.0 ns
80% to 20% of VD - 1.7 3.0 ns

(Note 4) - 70 - ps rms

f

REF_CLK

= 8 to 75 MHz - 1 3 ms

8
16
32

8
16
32

45 - 55 %

814MHz

6-75MHz

0-±0.5ppm

-

-

-

-

-

-

14
28
50

14
28
56

MHz
MHz
MHz

MHz
MHz
MHz

Notes: 4.

f

CLK_OUT

= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.

5. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Inte rval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.

6. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Inte rval Error taken with 3rd
order 100 Hz Highpass filter.

7. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.

DS759F2 7

CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT

t

buf

t

hdst

t

hdst

t

low

t

r

t

f

t

hdd

t

high

t

sud

t

sust

t

susp

Stop

Start

Start

Stop

Repeated

SDA

SCL

VD

t

dpor

Figure 2. Control Port Timing - I²C Format

Inputs: Logic 0 = GND; Logic 1 = VD; CL=20pF.

Parameter Symbol Min Max Unit

SCL Clock Frequency f
Bus Free-Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 8)t
SDA Setup Time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Acknowledge Delay from SCL Falling t
Delay from Supply Voltage Stable to Control Port Ready t

scl

buf

hdst

low
high
sust
hdd
sud

r

f

susp

ack

dpor

- 100 kHz

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

300 1000 ns
100 - µs

CS2200-CP

Notes: 8. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

f

8 DS759F2