Cirrus Logic CS2000-OTP User Manual

Hardware Configuration

Auxiliary

Output

6 to 75 MHz

PLL Output

Frequency Reference

3.3 V

Hardware Control

8 MHz to 75 MHz

Low-Jitter Timing Reference

Fractional-N

Frequency Synthesizer

Digital PLL & Fractional

N Logic

Output to Input

Clock Ratio

Timing Reference

PLL Output Lock Indicator

50 Hz to 30 MHz

Frequency Reference

Output to Input

Clock Ratio

CS2000-OTP

Fractional-N Clock Synthesizer & Clock Multiplier

Features

 Delta-Sigma Fractional-N Frequency Synthesis

– Generates a Low Jitter 6 - 75 MHz Clock

from an 8 - 75 MHz Reference Clock

 Clock Multiplier / Jitter Reduction

– Generates a Low Jitter 6 - 75 MHz Clock

from a Jittery 50 Hz to 30 MHz Clock Source

 Highly Accurate PLL Multiplication Factor

– Maximum Error Less Than 1 PPM in High-

Resolution Mode

 One-Time Programmability

– Configurable Hardware Control Pins – Configurable Auxiliary Output

 Flexible Sourcing of Reference Clock

– External Oscillator or Clock Source – Supports Inexpensive Local Crystal

 Minimal Board Space Required

– No External Analog Loop-filter

Components

General Description

The CS2000-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2000-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for both frequency synthesis/clock generation from a stable reference clock as well as generation of a low-jitter clock relative to an external noisy synchronization clock with frequencies as low as 50 Hz. The CS2000OTP has many configuration options which are set once prior to runtime. At runtime there are three hardware configuration pins available for mode and feature selection.

The CS2000-OTP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) and Automotive (-40°C to +85°C) grades. Customer development kits are also available for custom device prototyping, small production programming, and device evaluation. Please see “Ordering Information” on page 29 for complete details.

http://www.cirrus.com

MAY '10

DS758F2

TABLE OF CONTENTS

1. PIN DESCRIPTION ................................................................................................................................. 4

2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5

3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6

RECOMMENDED OPERATING CONDITIONS .................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6

DC ELECTRICAL CHARACTERISTICS . ... ... .... ... ... ... .... ... ... .......................................... ........................ 6

AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7

PLL PERFORMANCE PLOTS ............................................................................................................... 8

4. ARCHITECTURE OVERVIEW ............................................................................................................... 9

4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 9

4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 9

4.2.1 Fractional-N Source Selection for the Frequency Synthesizer ........ ... ... .... ... ... ... ... .... ... ... ... ... 10

5. APPLICATIONS ................................................................................................................................... 11

5.1 One Time Programmability ............................................................................................................ 11

5.2 Timing Reference Clock Input ..................... .......................................... ......................................... 11

5.2.1 Internal Timing Reference Clock Divider .. ... .... ... ... ... .... ... ... .......................................... ......... 11

5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 12

5.2.3 External Reference Clock (REF_CLK) .................................................................................. 12

5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 12

5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 13

5.4 Output to Input Frequency Ratio Configuration ............................................................................. 14

5.4.1 User Defined Ratio (RUD), Frequency Synthesizer Mode .................................................... 14

5.4.2 User Defined Ratio (RUD), Hybrid PLL Mode ....... ................................................................ 14

5.4.3 Ratio Modifier (R-Mod) .......................................................................................................... 15

5.4.4 Effective Ratio (REFF) .......................................................................................................... 15

5.4.5 Fractional-N Source Selection ............................................................................................... 15

5.4.5.1 Manual Fractional-N Source Selection for the Frequency Synthesizer ............ ... ... ... 16

5.4.5.2 Automatic Fractional-N Source Selection for the Frequency Synthesizer ................. 16

5.4.6 Ratio Configuration Summary ............................................................................................... 17

5.5 PLL Clock Output ........................................................................................................................... 18

5.6 Auxiliary Output ................. ... ... .... ... ... ....................................... ... ... ... .... ... ...................................... 18

5.7 Mode Pin Functionality ...................... ... ... ....................................... ... .... ... ... ... .... ... ... ... ................... 19

5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 19

5.7.2 M2 Mode Pin Functionality .................................................................................................... 19

5.7.2.1 M2 Configured as Output Disable .............................................................................. 19

5.7.2.2 M2 Configured as R-Mod Enable ........................................................ ... ... ................ 19

5.7.2.3 M2 Configured as Auto Fractional-N Source Selection Disable .... ... ... ... ... .... ... ... ... ... 20

5.7.2.4 M2 Configured as Fractional-N Source Select .................................................... ... ... 20

5.7.2.5 M2 Configured as AuxOutSrc Override ..................................................................... 20

5.8 Clock Output Stability Considerations ......... ... ... ... .... ... ... ... .... ......................................................... 20

5.8.1 Output Switching ................................................................................................................... 20

5.8.2 PLL Unlock Conditions .......................................................................................................... 21

5.9 Required Power Up Sequencing for Programmed Devices .................. ......................................... 21

6. PARAMETER DESCRIPTIONS ........................................................................................................... 22

6.1 Modal Configuration Sets ..................... ... ....................................... ... .... ... ... ... .... ... ... ... ................... 22

6.1.1 R-Mod Selection (RModSel[1:0]) ........................ ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ..

6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) .................... ......................................... 23

6.1.3 Lock Clock Ratio (LockClk[1:0]) ............................................................................................ 23

6.1.4 Fractional-N Source for Frequency Synthesizer (FracNSrc) ................................................. 23

6.2 Ratio 0 - 3 ..... .... ... ... ... ....................................... ... .... ... ....................................... ... ... ...................... 23

6.3 Global Configuration Parameters ................................................................................................... 24

6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 24

CS2000-OTP

.22

DS758F2 2

6.3.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 24

6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 24

6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 24

6.3.5 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 25

6.3.6 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 25

7. CALCULATING THE USER DEFINED RATIO .................................................................................... 26

7.1 High Resolution 12.20 Format ................ .... ... ... ... .......................................... ................................ 26

7.2 High Multiplication 20.12 Format ................................................................................................... 26

8. PROGRAMMING INFORMATION ........................................................................................................ 27

9. PACKAGE DIMENSIONS .................................................................................................................... 28

THERMAL CHARACTERISTICS ......................................................................................................... 28

10. ORDERING INFORMATION ..................................................... ... ... ... ... .... ... ... ... .... ............................ 29

11. REVISION HISTORY ................................................................................. ... ... ... .... ... ... ... ................... 29

LIST OF FIGURES

Figure 1. Typical Connection Diagram ........................................................................................................ 5

Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 8

Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 8

Figure 4. CLK_IN Random Jitter Rejection and Tolerance ....................... ... .... ... ... ... .... ... ...........................8

Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer .......................................................................9

Figure 6. Hybrid Analog-Digital PLL .......................................................................................................... 10

Figure 7. Fractional-N Source Selection Overview ................................................................................... 10

Figure 8. Internal Timing Reference Clock Divider ................................................................................... 11

Figure 9. REF_CLK Frequency vs. a Fixed CLK_OUT ............................................................................. 12

Figure 10. External Component Requirements for Crystal Circuit ............................................................ 12

Figure 11. Low bandwidth and new clock domain .................................................................................... 13

Figure 12. High bandwidth with CLK_IN domain re-use ........................................................................... 13

Figure 13. Ratio Feature Summary ........................................................................................................... 17

Figure 14. PLL Clock Output Options ....................................................................................................... 18

Figure 15. Auxiliary Output Selection ........................... .......................................... ................................... 18

Figure 16. M2 Mapping Options ................................................................................................................ 19

Figure 17. Parameter Configuration Sets .................................................................................................. 22

CS2000-OTP

LIST OF TABLES

Table 1. Modal and Global Configuration ........................ .... ... ... ... .... ... ... ... ... .... ... ...................................... 11

Table 2. Ratio Modifier .............................................................................................................................. 15

Table 3. Example 12.20 R-Values ............................................................................................................ 26

Table 4. Example 20.12 R-Values ............................................................................................................ 26

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CS2000-OTP

1 2 3 4 5

XTO

CLK_OUT

GND

XTI/REF_CLK

AUX_OUT

CLK_IN

1. PIN DESCRIPTION

Pin Name # Pin Description

VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output (Output) - PLL clock output.

AUX_OUT 4 CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference. XTO

XTI/REF_CLK M2 8 Mode Select (Input) - M2 is a configurable mode selection pin.

M1 9 Mode Select (Input) - M1 is a configurable mode selection pin. M0 10 Mode Select (Input) - M0 is a configurable mode selection pin.

Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on configuration.

Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -

XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input

clock. REF_CLK is an input for an externally generated low-jitter reference clock.

4 DS758F2

2. TYPICAL CONNECTION DIAGRAM

GND

M2 M1

XTI/REF_CLK

Frequency Reference CLK_IN

XTO

CLK_OUT

AUX_OUT

0.1 µF

+3.3 V

Low-Jitter

Timing Reference

System Microcontroller

1 µF

REF_CLK XTO

XTI XTO

40 pF

Crystal

To circuitry which requires

a low-jitter clock

N.C.

To other circuitry or

Microcontroller

Figure 1. Typical Connection Diagram

CS2000-OTP

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CS2000-OTP

3. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V; all voltages with respect to ground. (Note 1)

Parameters Symbol Min Typ Max Units

DC Power Supply (Note 2) VD 3.1 3.3 3.5 V Ambient Operating Temperature (Power Applied)

Commercial Grade

Automotive Grade

-10

-40

+70 +85

°C °C

Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits

may adversely affect device reliability.

2. CLK_IN must not be applied when these conditions are not met, including during power up. See section

5.9 on page 21 for required power up procedure.

ABSOLUTE MAXIMUM RATINGS

GND = 0 V; all voltages with respect to ground.

Parameters Symbol Min Max Units

DC Power Supply VD -0.3 6.0 V Input Current I Digital Input Voltage (Note 3)V Ambient Operating Temperature (Power Applied) T Storage Temperature T

IN A

stg

-±10mA

-0.3 VD + 0.4 V

-55 125 °C

-65 150 °C

WARNING:Operation at or beyond these limits may result in permanent damage to the device.

Notes: 3. The maximum over/under voltage is limited by the input current except on the power supply pin.

DC ELECTRICAL CHARACTERISTICS

Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); T

= -40°C to +85°C (Automotive Grade).

Parameters Symbol Min Typ Max Units

Power Supply Current - Unloaded (Note 4)I Power Dissipation - Unloaded (Note 4)P Input Leakage Current I Input Capacitance I High-Level Input Voltage V Low-Level Input Voltage V High-Level Output Voltage (IOH = -1.2 mA) V

Low-Level Output Voltage (I

= 1.2 mA) V

IH IL

OH OL

Notes: 4. To calculate the additional current consumption due to loading (per output pin), multiply clock output

frequency by load capacitance and power supply voltage. For example,

CLK_OUT

(49.152 MHz) * CL (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to

these loading conditions on CLK_OUT.

-1218mA

-4060mW

--±10µA

-8-pF

70% - - VD

--30%VD

80% - - VD

--20%VD

6 DS758F2

CS2000-OTP

AC ELECTRICAL CHARACTERISTICS

Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);

= -40°C to +85°C (Automotive Grade); CL=15pF.

Parameters Symbol Conditions Min Typ Max Units

Crystal Frequency Fundamental Mode XTAL

Reference Clock Input Frequency f

Reference Clock Input Duty Cycle D Internal System Clock Frequency f Clock Input Frequency f Clock Input Pulse Width (Note 5)pw

PLL Clock Output Frequency f PLL Clock Output Duty Cycle t Clock Output Rise Time t Clock Output Fall Time t Period Jitter t Base Band Jitter (100 Hz to 40 kHz) (Notes 6, 7) - 50 - ps rms Wide Band JItter (100 Hz Corner) (Notes 6, 8) - 175 - ps rms PLL Lock Time - CLK_IN (Note 9)t

PLL Lock Time - REF_CLK t Output Frequency Synthesis Resolution (Note 10)f

XTAL

REF_CLK

SYS_CLK

CLK_IN

CLK_OUT

OD OR OF JIT

LR err

RefClkDiv[1:0] = 10 RefClkDiv[1:0] = 01 RefClkDiv[1:0] = 00

8 16 32

14 28 50

14 28 56

45 - 55 %

814MHz

50 Hz - 30 MHz

CLK_IN

< f > f

SYS_CLK SYS_CLK

/96 /96

2 10

6-75MHz

Measured at VD/2 45 50 55 % 20% to 80% of VD - 1.7 3.0 ns 80% to 20% of VD - 1.7 3.0 ns

(Note 6) - 70 - ps rms

< 200 kHz

CLK_IN

> 200 kHz

CLK_IN

REF_CLK

= 8 to 75 MHz - 1 3 ms

High Resolution

High Multiplication

100

0 0

200

±0.5

±112

MHz MHz MHz

UI ns

ppm ppm

Notes: 5. 1 UI (unit interval) corresponds to t

CLK_OUT

= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.

SYS_CLK

or 1/f

SYS_CLK

7. In accordance with AES-12id-2006 section 3.4.2. Measurem ents are Time Interval Error taken with 3rd order 100 Hz to 40 kHz bandpass filter.

8. In accordance with AES-12id-2006 section 3.4.1. Measurem ents are Time Interval Error taken with 3rd order 100 Hz Highpass filter.

9. 1 UI (unit interval) corresponds to t

CLK_IN

or 1/f

CLK_IN

10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the reference clock.

DS758F2 7

PLL PERFORMANCE PLOTS

1 10 100 1,000 10,000

0.1

100

1,000

10,000

Input Jitter Frequency ( Hz )

Max Input Jitter Level (usec)

1 Hz Bandwidth 128 Hz Bandwidth

1 10 100 1000 10000

-60

-50

-40

-30

-20

-10

Input Jitter Frequency (Hz)

Jitter Transfer (dB)

1 Hz Bandwidth 128 Hz Bandwi dth

Figure 2. CLK_IN Sinusoidal Jitter Tolerance Figure 3. CLK_IN Sinusoidal Jitter Transfer

Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz). Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).

Figure 4. CLK_IN Random Jitter Rejection and To lerance

0.01 0.1 1 10 100 1000

0.01

0.1

100

1000

Inpu t Jitter Level ( nsec)

Output Jitt er Level ( nsec)

1 Hz Bandwidt h 128 Hz Bandwidt h

Unlock

Test Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; f

CLK_IN

= 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] =11.

CLK_OUT

CS2000-OTP

= 12.288 MHz;

8 DS758F2

4. ARCHITECTURE OVERVIEW

Fractional-N

Divider

Timing Reference

Clock

PLL Output

Voltage Controlled

Oscillator

Internal

Loop Filter

Phase

Comparator

Delta-Sigma

Modulator

4.1 Delta-Sigma Fractional-N Frequency Synthesizer

The core of the CS2000 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to quickly tune to a new frequency. In very simplistic terms, the Fractional-N Freq uency Synthesizer multiplies the Timing Reference Clock by the value of N to generate the PLL out put clock. The desired output to input clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 5).

The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fractional-N divided clock with the original timing reference and generates a control signal. The control signal is filtered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio betwee n the reference clock and the VCO output (thus the duty cycle of the modulator sets the fractional value). This allows the design to be optimized for very fast lock times for a wide rang e of outpu t freq uencies withou t the need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference clock should be stable and jitter-free.

CS2000-OTP

4.2 Hybrid Analog-Digital Phase Locked Loop

DS758F2 9

Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer

The addition of the Digital PLL and Fractional-N Logic (shown in Figure 6) to the Fractional-N Frequency Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical analog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges without the need to change external loop filter components while maintaining impressive jitter reduction performance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the frequency reference and compares that to the desired ratio. The digital logic generates a value of N which is then applied to the Fractional-N frequency synthesizer to generate the desired PLL outpu t frequency. Notice that the frequency and phase of the timing reference signal do not affect the output of the PLL since the digital control loop will correct for the PLL output. A major advantage of the Digital PLL is the ease with which the loop filter bandwidth can be altered. The PLL bandwidth is set to a wide-bandwidth mode to quickly achieve lock and then reduced for optimal jitter rejection.

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