Cirrus Logic CS1810xx User Manual

CS1810xx, CS4961xx, & CM-2

Digital Audio Networking Processor

CobraNet

Silicon Series

™

CS18100x, CS18101x, CS18102x, and CM-2 CS49610x, CS49611x, and CS49612x

Hardware User’s Manual

Version 2.3

Preliminary Product Information

http://www.cirrus.com

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

DS651UM23

CobraNet Hardware User’s Manual

List of Figures.........................................................................................................................................4

1.0 .Introduction ..................................................................................................................................... 5

2.0 Features ...........................................................................................................................................6

2.1 CobraNet............................................................................................................................. 6

2.2 CobraNet Interface.............................................................................................................. 6

2.3 Host Interface...................................................................................................................... 7

2.4 Asynchronous Serial Interface ............................................................................................ 7

2.5 Synchronous Serial Audio Interface.................................................................................... 7

2.6 Audio Clock Interface .......................................................................................................... 7

2.7 Audio Routing and Processing............................................................................................ 7

3.0 Hardware..........................................................................................................................................8

4.0 Pinout and Signal Descriptions ........................................................................................................ 9

4.1 CS1810xx & CS4961xx Package Pinouts......................................................................... 10

4.1.1 CS1810xx/CS4961xx Pinout .............................................................................10

4.1.2 CM-2 Connector Pinout..................................................................................... 11

4.2 Signal Descriptions ...........................................................................................................12

4.2.1 Host Port Signals ..............................................................................................12

4.2.2 Asynchronous Serial Port (UART Bridge) Signals ............................................ 12

4.2.3 Synchronous Serial (Audio) Signals.................................................................. 13

4.2.4 Audio Clock Signals ..........................................................................................13

4.2.5 Miscellaneous Signals....................................................................................... 14

4.2.6 Power and Ground Signals ...............................................................................14

4.2.7 System Signals .................................................................................................15

4.3 Characteristics and Specifications .................................................................................... 16

4.3.1 Absolute Maximum Ratings ..............................................................................16

4.3.2 Recommended Operating Conditions ...............................................................16

4.3.3 Digital DC Characteristics .................................................................................16

4.3.4 Power Supply Characteristics ...........................................................................16

5.0 Synchronization..............................................................................................................................17

5.1 Synchronization Modes ..................................................................................................... 17

5.1.1 Internal Mode .................................................................................................... 18

5.1.2 External Word Clock Mode ...............................................................................18

5.1.3 External Master Clock Mode .............................................................................18

6.0 Digital Audio Interface ....................................................................................................................19

6.1 Digital Audio Interface Timing ........................................................................................... 20

6.1.1 Normal Mode Data Timing ................................................................................21

6.1.2 I

6.1.3 Standard Mode Data Timing .............................................................................22

7.0 Host Management Interface (HMI)................................................................................................. 23

7.1 Hardware...........................................................................................................................23

7.4 Protocol and Messages.....................................................................................................28

7.4.1 Messages .......................................................................................................... 28

7.4.1.1. Translate Address ................................................................................. 29

7.4.1.2. Interrupt Acknowledge........................................................................... 29

7.4.1.3. Goto Packet........................................................................................... 29

7.4.1.4. Goto Translation ....................................................................................29

7.4.1.5. Packet Received ...................................................................................30

7.4.1.6. Packet Transmit ....................................................................................30

7.4.1.7. Goto Counters ....................................................................................... 30

7.4.2 Status ................................................................................................................31

Table of Contents

S Mode Data Timing .......................................................................................21

Version 2.3

CobraNet Hardware User’s Manual

Table of Contents

7.4.3 Data................................................................................................................... 32

7.4.3.1. Region length ........................................................................................ 32

7.4.3.2. Writable Region .....................................................................................32

7.4.3.3. Translation Complete ............................................................................ 32

7.4.3.4. Packet Transmission Complete............................................................. 32

7.4.3.5. Received Packet Available ....................................................................32

7.4.3.6. Message Togglebit ................................................................................ 32

8.0 HMI Reference Code ..................................................................................................................... 33

8.1 HMI Definitions.................................................................................................................. 33

8.2 HMI Access Code .............................................................................................................34

8.3 CM-1, CM-2 Auto-detection .............................................................................................. 36

9.0 Mechanical Drawings and Schematics ..........................................................................................37

9.1 CM-2 Mechanical Drawings .............................................................................................. 38

9.2 CM-2 Schematics.............................................................................................................. 44

9.3 CS1810xx/CS4961xx Package ......................................................................................... 51

9.4 Temperature Specifications ..............................................................................................52

10.0 Ordering Information ....................................................................................................................53

10.1 Device Part Numbers ...................................................................................................... 53

10.2 Device Part Numbering Scheme .....................................................................................53

CobraNet Hardware User’s Manual

List of Figures

Figure 1. CobraNet Data Services .........................................................................................................5

Figure 2. CobraNet Interface Hardware Block Diagram.........................................................................8

Figure 3. Audio Clock Sub-system ....................................................................................................... 17

Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) -

CS18100x/CS49610x & CS18101x/CS49611x............................................................ 19

Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) -

CS18102x/CS49612x ................................................................................................... 19

Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1..................................... 20

Figure 7. Serial Port Data Timing Overview......................................................................................... 20

Figure 8. Audio Data Timing Detail - Normal Mode, 64FS -

CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21

Figure 9. Audio Data Timing Detail - Normal Mode, 128FS -

CS18102x/CS49612x ................................................................................................... 21

Figure 10. Audio Data Timing Detail - I

CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21

Figure 11. Audio Data Timing Detail - I

CS18102x & CS49612x................................................................................................ 21

Figure 12. Audio Data Timing Detail - Standard Mode, 64FS -

CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 22

Figure 13. Audio Data Timing Detail - Standard Mode, 128FS -

CS18102x/CS49612x ................................................................................................... 22

Figure 14. Host Port Read Cycle Timing - Motorola Mode ..................................................................25

Figure 15. Host Port Write Cycle Timing - Motorola Mode................................................................... 25

Figure 16. Parallal Control Port - Intel Mode Read Cycle ....................................................................27

Figure 17. Parallel Control Port - Intel Mode Write Cycle .................................................................... 27

Figure 18. CM-2 Module Assembly Drawing, Top ...............................................................................38

Figure 19. CM-2 Module Assembly Drawing, Bottom ..........................................................................39

Figure 20. General PCB Dimensions ................................................................................................... 40

Figure 21. Example Configuration, Side View...................................................................................... 41

Figure 22. Faceplate Dimensions ........................................................................................................ 42

Figure 23. Connector Detail ................................................................................................................. 43

Figure 24. CM-2 RevF Schematic Page 1 of 7 ....................................................................................44

Figure 25. CM-2 RevF Schematic Page 2 of 7 ....................................................................................45

Figure 26. CM-2 RevF Schematic Page 3 of 7 ....................................................................................46

Figure 27. CM-2 RevF Schematic Page 4 of 7 ....................................................................................47

Figure 28. CM-2 RevF Schematic Page 5 of 7 ....................................................................................48

Figure 29. CM-2 RevF Schematic Page 6 of 7 ....................................................................................49

Figure 30. CM-2 RevF Schematic Page 7 of 7 ....................................................................................50

Figure 31. 144-Pin LQFP Package Drawing........................................................................................51

Figure 32. Device Part Numbering Explanation...................................................................................53

S Mode, 64FS -

S Mode, 128FS -

List of Figures

Version 2.3

1.0 Introduction

This document is intended to help hardware designers integrate the CobraNetTM interface into an audio system design. It covers the CS18100x, CS18101x, CS18102x, CS49610x, CS49611x, and CS49612x members of the CobraNet “x” is the ROM version (ROM ID). This document also describes the CM-2 module with schematics, mechanical drawings, etc.

CobraNet is a combination of hardware (the CobraNet interface), network protocol, and firmware. CobraNet operates on a switched Ethernet network and provides the following additional communications services.

• Isochronous (Audio) Data Transport

• Sample Clock Distribution

• Control and Monitoring Data Transport

The CobraNet interface performs synchronous-to-isochronous and isochronous-tosynchronous conversions as well as the data formatting required for transporting real-time digital audio over the network.

The CobraNet interface has provisions for carrying and utilizing control and monitoring data such as Simple Network Management Protocol (SNMP) through the same network connection as the audio. Standard data transport capabilities of Ethernet are shown here as unregulated traffic. Since CobraNet is Ethernet based, in most cases, data communications and CobraNet applications can coexist on the same physical network.

Figure 1 illustrates the different data services available through the CobraNet system.

CobraNet Hardware User’s Manual

Introduction

Silicon Series of devices, where

Isochronous Data

(Audio)

Ethernet

Unregulated

Traffic

Tr af fi c

Control Data

Clock

Figure 1. CobraNet Data Services

CobraNet Hardware User’s Manual

Features

2.0 Features

2.1 CobraNet

• Real-time Digital Audio Distribution via Ethernet

• No Overall Limit on Network Channel Capacity

• Fully IEEE 802.3 Ethernet Standards Compliant

• Fiber optic and gigabit Ethernet variants are fully supported.

• Ethernet infrastructure can be used simultaneously for audio and data communications.

• Free CobraCAD™ Audio Network Design Tool

• High-quality Audio Sample Clock Delivery Over Ethernet

• Bit-transparent 16-, 20-, and 24-bit Audio Transport

• Professional 48-kHz and 96-kHz sample rate

• Select Latency as Low as 1.33ms

• Flexible Many-to-many Network Audio Routing Capabilities

• Reduced-cost, Improved-performance, Convergent Audio Distribution Infrastructure

2.2 CobraNet Interface

• 120 MIPS Customer-configurable Audio DSP

• Auto-negotiating 100Mbit Full-duplex Ethernet Connections

• Up to 32-channel Audio I/O Capability

• Implements CobraNet Protocol for real-time transport of audio over Ethernet.

• Local Management via 8-bit Parallel Host Port

• UDP/IP Network Stack with Dynamic IP Address Assignment via BOOTP or RARP

• Remote Management via Simple Network Management Protocol (SNMP)

• Economical Three-chip Solution

• Available Module form factor allows for flexible integration into audio products.

• Non-volatile Storage of Configuration Parameters

• Safely Upgrade Firmware Over Ethernet Connection

• LED Indicators for Ethernet Link, Activity, Port Selection, and Conductor Status

• Watchdog Timer Output for System Integrity Assurance

• Comprehensive Power-on Self-test (POST)

• Error and Fault Reporting and Logging Mechanisms

Version 2.3

2.3 Host Interface

• 8-bit Data, 4-bit Address

• Virtual 24-bit Addressing with 32-bit Data

• Polled, Interrupt, and DMA Modes of Operation

• Configure and Monitor CobraNet Interface

• Transmit or Receive Ethernet Packets at Near-100-Mbit Wire Speed

2.4 Asynchronous Serial Interface

• Full-duplex Capable

• 8-bit Data Format

• Supports all Standard Baud Rates

2.5 Synchronous Serial Audio Interface

• Up to Four Bi-directional Interfaces Supporting up to 32 Channels of Audio I/O

CobraNet Hardware User’s Manual

Features

• 64FS (3.072 MHz) Bit Rate for CS18100x/CS49610x and CS18101x/ CS49611x

• 128FS (6.144 MHz) Bit Rate for CS18102x/CS49612x

• Accommodates Many Synchronous Serial Formats Including I

• 32-bit Data Resolution on All Audio I/O

2.6 Audio Clock Interface

• 5 Host Audio-clocking Modes for Maximum Flexibility in Digital Audio Interface Design

• Low-jitter Master Audio Clock Oscillator (24.576 MHz)

• Synchronize to Supplied Master and/or Sample Clock

• Sophisticated jitter attenuation assures network perturbations do not affect audio performance.

2.7 Audio Routing and Processing

• Single-channel Granularity in Routing From Synchronous Serial Audio Interface to CobraNet Network

• Two levels of inward audio routing affords flexibility in audio I/O interface design in the host system.

• Local Audio Loopback and Output Duplication Capability

• Peak-read Audio Metering with Ballistics

CobraNet Hardware User’s Manual

Hardware

3.0 Hardware

Figure 2 shows a high-level view of the CobraNet CM-2 interface hardware architecture.

Clock

Control

Audio

Serial

Host

Figure 2. CobraNet Interface Hardware Block Diagram

VCXO

CS1810xx/

CS4961xx

Clock

Flash

Memory

Ethernet

Controller

CobraNet CM-2

Module

Ethernet

Magnetics

Flash memory holds the CobraNet firmware and management interface variable settings.

The CS1810xx or CS4961xx network processor is the heart of the CobraNet interface. It implements the network protocol stacks and performs the synchronous-to-isochronous and isochronous-to-synchronous conversions. The network processor has a role in sample clock regeneration and performs all interactions with the host system.

The sample clock is generated by a voltage-controlled crystal oscillator (VCXO) controlled by the network processor. The VCXO frequency is carefully adjusted to achieve lock with the network clock.

The Ethernet controller is a standard interface chip that implements the 100-Mbit Fast Ethernet standard. As per Ethernet requirements the interface is transformer isolated.

Version 2.3

4.0 Pinout and Signal Descriptions

This section details the chip pinout and signal interfaces for each module and is divided as follows:

• "CS1810xx & CS4961xx Package Pinouts" on page 10

• "Host Port Signals" on page 12

• "Asynchronous Serial Port (UART Bridge) Signals" on page 12

• "Synchronous Serial (Audio) Signals" on page 13

• "Audio Clock Signals" on page 13

• "Miscellaneous Signals" on page 14

• "Power and Ground Signals" on page 14

• "System Signals" on page 15

CobraNet Hardware User’s Manual

Pinout and Signal Descriptions

CobraNet Hardware User’s Manual

Pinout and Signal Descriptions

4.1 CS1810xx & CS4961xx Package Pinouts

4.1.1 CS1810xx/CS4961xx Pinout

Ta b l e 1 lists the pinout for the 144-pin LQFP CS1810xx/CS4961xx device. The interfaces

for these signals are expanded in the following sections.

Table 1. CS1810xx/CS4961xx Pin Assignments

Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name

1 VCXO_CTRL 37 DATA1 73 VDDIO 109 HADDR1

33 VDDIO 69 GND 105 HADDR3 141 NC

MCLK_SEL 38 WE 74 ADDR10 110 HADDR0

DBDA 39 DATA0 75 ADDR14 111 HDATA7

DBCK 40 DATA15 76 GND 112 HDATA6

NC 41 DATA14 77 ADDR13 113 VDDIO

NC 42 DATA13 78 NC 114 HDATA5

NC 43 DATA12 79 NC 115 HDATA4

DAO_MCLK 44 VDDIO 80 NC 116 GND

TEST 45 DATA11 81 NC 117 HDATA3

VDDD 46 DATA10 82 ADDR15 118 HDATA2

HS3 47 GND 83 VDDD 119 VDDD

NC 48 DATA9 84 ADDR16 120 HDATA1

GND 49 DATA8 85 ADDR17 121 HDATA0

DAO2_LRCLK 50 NC 86 GND 122 GND

DAO1_DATA3 51 NC 87 ADDR18 123 XTAL_OUT

DAO1_DATA2/HS2 52 NC 88 ADDR19 124 XTO

DAO1_DATA1/HS1 53 NC 89 OE 125 XTI

VDDIO 54 VDDD 90 CS1 126 GND_a

DAO1_DATA0/HS0 55 ADDR12 91 VDDIO 127 FILT2

DAO1_SCLK 56 ADDR11 92 MUTE 128 FILT1

GND 57 GND 93 HRESET 129 VDDA

DAO1_LRCLK 58 ADDR9 94 GND 130 VDDD

UART_TX_OE 59 ADDR8 95 WATCHDOG 131 DAI1_DATA3

VDDD 60 VDDIO 96 IOWAIT 132 DAI1_DATA2

UART_TXD 61 ADDR7 97 REFCLK_IN 133 GND

UART_RXD 62 ADDR6 98 VDDD 134 DAI1_DATA1

GND 63 GND 99 GPIO0 135 DAI1_DATA0

NC 64 ADDR5 100 GPIO1 136 VDDIO

DATA7 65 CS2 101 GND 137 DAI1_SCLK

DATA6 66 VDDD 102 HACK 138 DAI1_LRCLK

DATA5 67 ADDR4 103 HDS 139 GND

DATA4 68 ADDR3 104 HEN 140 HREQ

DATA3 70 ADDR2 106 HADDR2 142 NC

DATA2 71 ADDR1 107 HR/W 143 IRQ1

GND 72 ADDR0 108 GPIO2 144 IRQ2

Version 2.3

CobraNet Hardware User’s Manual

Pinout and Signal Descriptions

4.1.2 CM-2 Connector Pinout

Ta b l e 1 lists the pinout for the four pinout connectors on the CM-2 board (J1-J4). The

interfaces for these signals are expanded following the table.

Table 2. CM-2 Pin Assignments

Conn. Pin # Pin Name Conn. Pin # Pin Name Conn. Pin # Pin Name

J1/J2 A1 UART_RXD J1/J2 B8 GND J3/J4 A15 DAI1_DATA3

J1/J2 A2 UART_TX_OE J1/J2 B9 VCC_+3.3V J3/J4 A16 RSVD3

J1/J2 A3 HACK

J1/J2 A4 HR/W

J1/J2 A5 HDS

J1/J2 A6 HREQ

J1/J2 A7 HEN

J1/J2 A8 HADDR0 J1/J2 B15 VCC_+3.3V J3/J4 B2 VCC_+3.3V

J1/J2 A9 HADDR1 J1/J2 B16 GND J3/J4 B3 GND

J1/J2 A10 HADDR2 J1/J2 B17 VCC_+3.3V J3/J4 B4 VCC_+3.3V

J1/J2 A11 HDATA0 J1/J2 B18 RSVD1 J3/J4 B5 GND

J1/J2 A12 HDATA1 J1/J2 B19 GND J3/J4 B6 VCC_+3.3V

J1/J2 A13 HDATA2 J1/J2 B20 VCC_+3.3V J3/J4 B7 GND

J1/J2 A14 HDATA3 J3/J4 A1 RSVD2 J3/J4 B8 VCC_+3.3V

J1/J2 A15 HDATA4 J3/J4 A2 MUTE

J1/J2 A16 HDATA5 J3/J4 A3 FS1 J3/J4 B10 VCC_+3.3V

J1/J2 A17 HDATA6 J3/J4 A4 MCLK_OUT J3/J4 B11 GND

J1/J2 A18 HRESET

J1/J2 A19 HDATA7 J3/J4 A6 REFCLK_IN J3/J4 B13 GND

J1/J2 A20 HADDR3 J3/J4 A7 DAO1_SCLK/DAI1_SCLK J3/J4 B14 VCC_+3.3V

J1/J2 B1 UART_TXD J3/J4 A8 DAO1_DATA0 J3/J4 B15 GND

J1/J2 B2 GND J3/J4 A9 DAO1_DATA1 J3/J4 B16 GND

J1/J2 B3 VCC_+3.3V J3/J4 A10 DAO1_DATA2 J3/J4 B17 VCC_+5V

J1/J2 B4 GND J3/J4 A11 DAO1_DATA3 J3/J4 B18 VCC_+5V

J1/J2 B5 VCC_+3.3V J3/J4 A12 DAI1_DATA0 J3/J4 B19 AUX_POWER3

J1/J2 B6 GND J3/J4 A13 DAI1_DATA1 J3/J4 B20 AUX_POWER1

J1/J2 B7 VCC_+3.3V J3/J4 A14 DAI1_DATA2

J1/J2 B10 GND J3/J4 A17 WATCHDOG

J1/J2 B11 VCC_+3.3V J3/J4 A18 RSVD4

J1/J2 B12 GND J3/J4 A19 AUX_POWER2

J1/J2 B13 VCC_+3.3V J3/J4 A20 AUX_POWER0

J1/J2 B14 GND J3/J4 B1 GND

J3/J4 B9 GND

J3/J4 A5 MCLK_IN J3/J4 B12 VCC_+3.3V

CobraNet Hardware User’s Manual

Pinout and Signal Descriptions

4.2 Signal Descriptions

4.2.1 Host Port Signals

The host port is used to manage and monitor the CobraNet interface. Electrical operation and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this Manual.

The host port can operate in two modes in order to accomodate Motorola interfaces. The default mode is Motorola. Intel mode is set via a firmware modification.

Table 2-1: Host Port Signals

Signal Description Direction

HDATA[7:0] Host Data In/Out

HADDR[3:0] Host Address In

HRW

HRD Host Read In J1:A4 107 Host Read (Intel mode).

Host Request Out J1:A6 140 Host port data request.

HREQ

Host Alert Out J1:A3 102 Host port interrupt request.

HACK

HDS

Host Strobe In J1:A5 103 Host port strobe (Motorola mode).

HWR

Host Enable In J1:A7 104 Host Port Enable.

HEN

Host

Direction

Host Write In J1:A5 103 Host Write (Intel mode).

In J1:A4 107 Host port transfer direction (Motorola mode).

CM-2 Pin #

J1:A19,

A[17:11]

J1:A20,

A[10:8]

CS1810xx/

CS4961xx Pin #

111, 112, 114, 115, 117, 118,

102, 121

105, 106, 109,110 Host port address.

Host port data.

Notes

or Intel® style

HCS

Select In J1:A7 104 Select (Intel mode).

4.2.2 Asynchronous Serial Port (UART Bridge) Signals

Level-shifting drive circuits are typically required between these signals and any external connections.

Signal Description Direction

UART_RXD

UART_TXD

UART_TX_OE Transmit Drive Enable Out J1:A2 23

Asynchronous Serial

Receive Data

Asynchronous Serial

Transmit Data

In J1:A1 26 Pull-up to VCC if unused.

Out J1:B1 25

CM-2 Pin #

CS1810xx/

CS4961xx Pin #

Notes

Enable transmit (active high) drive for two wire multi-drop interface.

Version 2.3

4.2.3 Synchronous Serial (Audio) Signals

The synchronous serial interfaces are used to bring digital audio into and out of the system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing and format is described in "Digital Audio Interface" on page 19.

CobraNet Hardware User’s Manual

Pinout and Signal Descriptions

Signal Description Direction

DAO1_SCLK Audio Bit Clock Out J3:A7 20

DAO1_DATA[3:0]

DAI1_DATA[3:0] Audio Input Data In

DAI1_SCLK Audio Bit Clock In J4:A7 137

Audio Output

Data

Out

CM-2 Pin #

J3:A18,

B18

J3:

A[15:12]

CS1810xx/

CS4961xx Pin #

15-17, 19

131, 132, 134, 135

4.2.4 Audio Clock Signals

See "Synchronization" on page 17 for an overview of synchronization modes and issues.

Notes

Synchronous serial bit clock. 64 FS for CS18100x & CS49610x (2x1 channel) 64 FS for CS18101x & CS49611x (2x4 channels) 128 FS for CS18102x & CS49612x (4x4 channels) Typically tied to DAI1_SCLK.

Output synchronous serial audio data DAO1_DATA[3:1] not used for CS18100x & CS49610x.

Input synchronous serial audio data DAI1_DATA[3:1] not used for CS18100x & CS49610x.

Should be tied to DAO1_SCLK. Synchronous serial bit clock.

Signal Description Direction

DAI1_LRCLK

DAO1_LRCLK

(FS1)

DAO2_LRCLK

(FS1)

REFCLK_IN Reference clock In J3:A6 97

MCLK_IN

MCLK_OUT

Sample clock

input

Sample clock

output

Sample clock

output

Master audio

clock input

Master audio

clock output

In 138 Should be tied to DAO1_LRCLK for all devices.

Out J3:A3 22

Out J3:A3 14 FS1 (word clock) for CS18102x & CS49612x.

In J3:A5 8*

Out J3:A4 8* Low jitter 24.576 MHz master audio clock.

CM-2 Pin #

CS1810xx/

CS4961xx Pin #

*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out implementation.

Notes

FS1 (word clock) for CS18100x/CS49610x and CS18101x/CS49611x.

Clock input for synchronizing network to an external clock source, for redundancy control and synchronization of FS divider chain to external source. See "Synchronization" on

page 17 for more detail.

For systems featuring multiple CobraNet interfaces operating off a common master clock. See "Synchronization" on page 17 for more detail.

CobraNet Hardware User’s Manual

Pinout and Signal Descriptions

4.2.5 Miscellaneous Signals

Signal Description Direction

HRESET Reset In J1:A18 93

WATCHDOG Watch Dog Out J3:A17 95

MUTE

NC No Connect - -

Interface

Ready

Out J3:A2 92

CM-2 Pin #

CS1810xx/

CS4961xx Pin #

28, 50-53, 78-

81, 141, 142

4.2.6 Power and Ground Signals

Signal Description CM-2 Pin #

J1:B20, B17, B15,

B13, B11, B9, B7,

VCC_+3V

System Digital +3.3 v

B5, B3

J3:B14, B12, B10,

B8, B6, B4, B2

System reset (active low). 10 ns max rise time. 1 ms min assertion time.

Toggles at 750 Hz nominal rate to indicate proper operation. Period duration in excess of 200 ms indicates hardware or software failure has occurred and the interface should be reset. Note that improper operation can also be indicated by short pulses (<100 ns).

Asserts (active low) during initialization and when a fault is detected or connection to the network is lost.

CS1810xx/CS4961xx

Pin #

N/A

Notes

Specification

± 0.3v, 500 mA Typ., 750 mA Max.

3.3

_+5V

VCC

VDDD N/A

VDDIO N/A

VDDA N/A 129 Filtered +1.8 V @ 10mA Typ.

AUX_POWER

[3-0]

GND Digital Ground

J3;B[18:17] N/A Backwards Compatibility

J3:B[20:19],

A[20:19]

J1:B19, B16, B14,

B12, B10, B8, B6,

B4, B2

J3:B16, B15, B13,

B11, B9, B7, B5,

B3, B1

10, 24, 54, 66, 83,

98, 119, 130

18, 33, 44, 60, 73,

91, 113, 136

N/A

13, 21, 27, 36, 47, 57, 63, 69, 76, 86, 94, 101, 116, 122,

126, 133, 139

+1.8 V @ 500mA Typ. for Core Logic

+3.3 V @ 120mA Typ. for I/O Logic

Version 2.3

4.2.7 System Signals

Use these CS1810xx/CS4961xx signals stricktly in the manner described in CM-2 Schematics (Section 9.2 on page 44). Each signal is briefly described below.

CobraNet Hardware User’s Manual

Pinout and Signal Descriptions

Signal Description

VCXO_CTRL A Delta-sigma DAC Output for Controlling the On-board VCXO 1

MCLK_SEL Control Signal for Selecting MCLK Sources 2

DBDA, DBCK I2C Debugger Interface 3, 4

TEST

DATA[15:0] Data Bus for Flash & Ethernet Controller(s)

ADDR[19:0] Address Bus for Flash & Ethernet Controller(s)

CS1

CS2

IOWAIT Wait State Signal from Ethernet Controller(s) 96

GPIO[2:0] General-purpose I/O Signals 99, 100, 108

XTI Reference Clock Input / Crystal Oscillator Input 125

XTO Crystal Oscillator Output 124

Used for testing during manufacturing. Keep grounded for normal operation.

Write Enable for Flash and Ethernet Controller(s) 38

Chip Select for Flash Memory Device 90

Chip Select for Ethernet Controller(s) 65

Output Enable 89

CS1810xx/CS4961xx

Pin #

29-32, 34, 35, 37, 39-43,

45, 46, 48, 49

55, 56, 58, 59, 61, 62, 64,

67, 68, 70-72, 74, 75, 77,

82, 84, 85, 87, 88

XTAL_OUT A Buffered Version of XTI 123

FILT2, FILT1 PLL Loop Filter 127, 128

DAO_MCLK MCLK Input 8

HS[3:0] CS1810xx/CS4961xx Boot Mode Selection 11, 16, 17, 19

CobraNet Hardware User’s Manual

Pinout and Signal Descriptions

4.3 Characteristics and Specifications

4.3.1 Absolute Maximum Ratings

Parameter Symbol Min Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

VDD

VDDA

VDDIO

|VDDA – VDD| Input current, any pin except supplies I Input voltage on FILT1, FILT2 V Input voltage on I/O pins V Storage temperature T

filt

inio

stg

–0.3 –0.3 –0.3

-+/- 10mA

-5.0V

–65 150 °C

2.0

5.0

0.3

2.0 V

Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

4.3.2 Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

DC power supplies: Core supply

PLL supply

I/O supply

|VDDA – VDD|

Ambient operating temperature

- CQ

- DQ

VDD

VDDA

VDDIO

1.71

3.13

- 40

1.8

3.3

1.89

3.46

0.3

+ 70 + 85

V V V V

°C

4.3.3 Digital DC Characteristics

(measurements performed under static conditions.)

Parameter Symbol Min Typ Max Unit

High-level input voltage V Low-level input voltage, except XTI V Low-level input voltage, XTI V Input Hysteresis V High-level output voltage at

= –8.0 mAO = –16.0 mA

Low-level output voltage at I

= 8.0 mAO = –16.0 mA

Input leakage current (all pins without internal pull-

ILXTI

hys

2.0 - - V

VDDIO * 0.9 - - V

up resistors except XTI) Input leakage current (pins with internal pull-up

IN-PU

resistors, XTI)

4.3.4 Power Supply Characteristics

(measurements performed under operating conditions))

Parameter Min Typ Max Unit

Power supply current: Core and I/O operating: VDD (Note 1) PLL operating: VDDA With external memory and most ports operating: VDDIO

--0.8V

--0.6V

0.3 V

--VDDIO * 0.1V

--5µA

--50µA

500

120

mA mA mA

NOTES:1. Dependent on application firmware and DSP clock speed.

Version 2.3

5.0 Synchronization

Figure 3 shows clock related circuits for the CS1810xx/CS4961xx and board design

(CM-2). This circuitry allows the synchronization modes documented below to be achieved. Modes are distinguished by different settings of the multiplexors and software elements.

CobraNet Hardware User’s Manual

Synchronization

MCLK_OUT

DAC

MCLK_IN

MCLK_SEL

RefClkEnable

RefClkPolarity

REFCLK_IN

BeatReceived

VCXO

24.576 MHz

Edge

Detect

AClkConfig

Sample

Phase

Counter

Legend:

Detector

External

Hardware

Component

(CM2)

Audio Clock

Generator

Phase

Hardware

Component

(CS1810xx, CS4961xx)

CS1810xx/CS4961xx

FS1

SLCK

Loop Filter

Internal

Software

Component

Figure 3. Audio Clock Sub-system

5.1 Synchronization Modes

Clock synchronization mode for conductor and performer roles is independently selectable via management interface variables syncConductorClock and syncPerformerClock. The role (conductor or performer) is determined by the network environment including the conductor priority setting of the device and the other devices on the network. It is possible to ensure you will never assume the conductor role by selecting a conductor priority of zero. However, it is not reasonable to assume that by setting a high conductor priority, you will always assume the conductor role. For more information, refer to CobraNet Programmer’s Reference Manual.

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