Cirrus Logic CS1631 User Manual

CS1630

R13

NTC

BR1 BR1

Mains

BR1 BR 1

R11

R14

Z1 C4

CS1630 /31

IAC

SOURCE

FBAUX

BSTOUT

GNDSGND

CLAMP

FBSENSE

eOTP

BSTAUX

R10

NTC

BST

rect

VDD

R12

C11

C12

D11

R15 D10

R16

C10

IGND

LED2 +

LED 1+

LED 1-

LED2 -

GND

_QVCC

CS1631

2-Channel TRIAC Dimmable LED Driver IC

Features

• Best-in-class Dimmer Compatibility

- Leading-edge (TRIAC) Dimmers

- Trailing-edge Dimmers

- Digital Dimmers (with Integrated Power Supply)

• Correlated Color Temperature (CCT) Control System

• Up to 85% Efficiency

• Flicker-free Dimming

• Programmable Dimming Profile

- Constant CCT Dimming

- Black Body Line Dimming

• 0% Minimum Dimming Level

• Temperature Compensated LED Current

• End-of-line Programming Using Power Line Calibration

- Lower LED Binning Requirement

• Programmable Series or Parallel Two-Channel Output

- Interleaved Output Eliminates Additional Transformer

• Programmable Quasi-resonant Second Stage with Constant-current Output

- Flyback, Buck, and Tapped Buck

• Register Lockout

• Fast Startup

• Tight LED Current Regulation: Better than ±5%

• Primary-side Regulation (PSR)

• >0.9 Power Factor

• IEC-61000-3-2 Compliant

• Soft Start

• Protections:

- Output Open/Short

- Current-sense Resistor Open/Short

- External Overtemperature Using NTC

Overview

The CS1630 and CS1631 are high-performance offline AC /DC LED drivers for dimmable and high color rendering index (CRI) LED replacement lamps and luminaires. They feature Cirrus Logic’s proprietary digital dimmer compatibility control technology and digital correlated color temperature (CCT) control system that enables two-channel LED color mixing. The CS1630 is designed for 120VAC line voltage applications, and the CS1631 is optimized for 230VAC line voltage applications.

The CS1630/31 integrates a critical conduction mode boost converter, providing power factor correction and superior dimmer compatibility with a primary-side regulated quasi-resonant second stage, which is configurable for isolated and non-isolated topologies. The digital CCT control system provides the ability to program dimming profiles, such as constant CCT dimming and black body line dimming. The CS1630/31 optimizes LED color mixing by temperature compensating LED current with an external NTC. The IC controller is also equipped with power line calibration for remote system calibration and end-of-line programming. The CS1630/31 provides a register lockout feature for security against potential access to proprietary registers.

Applications

• Dimmable Retrofit LED Lamps and LED Luminaries

• High CRI Lighting

• Offline LED Drivers

• Commercial Lighting

Ordering Information

See page 55.

Cirrus Logic, Inc.

http://www.cirrus.com

APR’13

DS954F3

CS1630/31

TABLE OF CONTENTS

1.INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.CHARACTERISTICS AND SPECIFICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.2 I

C™ Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.3 Power Line Calibration Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.TYPICAL PERFORMANCE PLOTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

5.2 Startup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

5.3 Dimmer Switch Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

5.3.1 Dimmer Learn Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3.2 Dimmer Validate Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3.3 No-dimmer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3.4 Leading-edge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3.5 Trailing-edge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4 Correlated Color Temperature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

5.5 Dimming Signal Extraction and the Dim Mapping Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.6 Boost Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.6.1 Maximum Peak Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.6.2 Output BSTOUT Sense & Input IAC Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.6.3 Boost Auxiliary Winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.6.4 Boost Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.7 Voltage Clamp Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.7.1 Clamp Overpower Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.8 Quasi-resonant Second Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.8.1 Series & Parallel Two-Channel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.8.2 Primary-side Current Control for Two-Channel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.8.3 Auxiliary Winding Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.8.4 Control Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.8.5 Frequency Dithering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.8.6 Output Open Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.8.7 Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.8.8 Open Loop Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.9 Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.9.1 Internal Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.9.2 External Overtemperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.10 Power Line Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.10.1 Power Line Calibration Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.10.2 PLC Program Mode Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.10.3 Calibration Mode Operation Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.10.4 Register Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.11 I

C™ Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.11.1 I

5.11.2 Control Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.11.3 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.11.4 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.11.5 Customer I

5.12 OTP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

5.12.1 Programming the OTP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

C Control Port Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

C Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2 DS954F3

CS1630/31

6.ONE-TIME PROGRAMMABLE (OTP) REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

6.2 Configuration 0 (Config0) – Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

6.3 Lockout Key (LOCK0, LOCK1, LOCK2, LOCK3) – Address 1 - 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

6.4 Color Polynomial Coefficient (P30, P20, P10, P03, P02, P01, P21, P12, P11, P00) – Address 5 - 24 . . . . . . . . . . . .29

6.5 Color Polynomial Coefficient (Q3, Q2, Q1, Q0) – Address 25 - 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6.6 Gate Drive Duration (GD_DUR) – Address 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6.7 Configuration 2 (Config2) – Address 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

6.8 Configuration 3 (Config3) – Address 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.9 Configuration 4 (Config4) – Address 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.10 Second Stage Dim (S2DIM) – Address 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.11 Maximum TT (TTMAX) – Address 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.12 Configuration 7 (Config7) – Address 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

6.13 Configuration 8 (Config8) – Address 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

6.14 Channel 1 Output Current (CH1CUR) – Address 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

6.15 Configuration 10 (Config10) – Address 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

6.16 Channel 2 Output Current (CH2CUR) – Address 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

6.17 Configuration 12 (Config12) – Address 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

6.18 PU Coefficient (PID) – Address 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

6.19 Maximum Switching Frequency (TTFREQ) – Address 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

6.20 Configuration 15 (Config15) – Address 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.21 Configuration 16 (Config16) – Address 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.22 Configuration 17 (Config17) – Address 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

6.23 Configuration 18 (Config18) – Address 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

6.24 Peak Current (PEAK_CUR) – Address 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

6.25 Configuration 38 (Config38) – Address 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

6.26 Configuration 44 (Config44) – Address 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

6.27 Configuration 45 (Config45) – Address 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

6.28 Configuration 46 (Config46) – Address 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

6.29 Configuration 47 (Config47) – Address 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

6.30 Configuration 48 (Config48) – Address 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

6.31 Configuration 49 (Config49) – Address 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

6.32 Configuration 50 (Config50) – Address 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

6.33 Configuration 51 (Config51) – Address 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

6.34 Configuration 52 (Config52) – Address 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

6.35 Configuration 53 (Config53) – Address 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

6.36 Configuration 54 (Config54) – Address 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

6.37 Configuration 55 (Config55) – Address 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

6.38 PLC Dim (PLC_DIM) – Address 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

6.39 Configuration 58 (Config58) – Address 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

6.40 Configuration 59 (Config59) – Address 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

6.41 Configuration 60 (Config60) – Address 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

6.42 Configuration 61 (Config61) – Address 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

6.43 Configuration 62 (Config62) – Address 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

6.44 CRC Tag (CRC_TAG) – Address 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

6.45 Channel 1 Color Calibration 3A (CH1_CAL3A) – Address 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

6.46 Channel 2 Color Calibration 3A (CH2_CAL3A) – Address 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

6.47 CRC Memory Tag 3A (CRC_MTAG3A) – Address 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

6.48 Channel 1 Color Calibration 3B (CH1_CAL3B) – Address 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

6.49 Channel 2 Color Calibration 3B (CH2_CAL3B) – Address 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

6.50 CRC Memory Tag 3B(CRC_MTAG3B) – Address 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

6.51 Channel 1 Color Calibration 3C (CH1_CAL3C) – Address 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

6.52 Channel 2 Color Calibration 3C (CH2_CAL3C) – Address 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

6.53 CRC Memory Tag 3C (CRC_MTAG3C) – Address 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

7.PACKAGE DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 55

10.REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

DS954F3 3

1. INTRODUCTION

POR

Volt age

Regul ator

VDD

FBSENSE

FBAUX

IAC

DAC

Peak

Contr ol

Fl yback Z CD

Output O pen

GND

OLP

BSTOUT

OCP

BSTAUX

Boost Z CD

CLAMP

ST(th )

STP(th )

OCP(th)

FBZC D(th)

OVP (th )

OLP(th)

FBZC D(th)

Pk_Max(th)

SGND

SOURCE

VDD

CONNECT

CONNECT(th)

SOURCE(th)

SCL

SDA

SYNC

eOTP

15 k

ADC

MUX

15k

VDD

ref

FBZC D

CLAMP

BSTZCD

SOURCE

Blank 3

CS1630/31

Figure 1. CS1630/31 Block Diagram

A typical schematic using the CS1630/31 IC is shown on the front page.

Startup current is provided from a patent-pending, external high-voltage source-follower network. In addition to providing startup current, this unique topology is integral in providing compatibility with digital dimmers by ensuring V always available to the IC. During steady-state operation, an auxiliary winding on the boost inductor back-biases the

power is

source-follower circuit and provides steady-state operating current to the IC to improve system efficiency.

The rectified input voltage is sensed as a current into pin IAC and is used to control the adaptive dimmer compatibility algorithm and extract the phase of the input voltage for output dimming control. During steady-state operation, the external high-voltage, source-follower circuit is source-switched in critical conduction mode (CRM) to boost the input voltage. This allows the boost stage to maintain good power factor, provide dimmer compatibility, reduce bulk capacitor ripple current, and provide a regulated input voltage to the second stage.

The current into the boost output voltage sense pin BSTOUT senses the output voltage of the CRM boost front-end.

4 DS954F3

The quasi-resonant second stage is implemented with peakcurrent mode primary-side control, which eliminates the need for additional components to provide feedback from the secondary and reduces system cost and complexity.

Voltage across an external user-selected resistor is sensed through pin FBSENSE to control the peak current through the second stage inductor. Leading-edge and trailing-edge blanking on pin FBSENSE prevents false triggering.

Pin FBAUX is used to sense the second stage inductor demagnetization to ensure quasi-resonant switching of the output stage.

An internal current source is adjusted by a feedback loop to regulate a constant reference voltage on pin eOTP for external negative temperature coefficient (NTC) thermistor measurements. An external NTC is connected to pin eOTP to provide thermal protection of the system and LED temperature compensation. The output current of the system is steadily reduced when the system temperature exceeds a programmable temperature set point. If the temperature reaches a designated high set point, the IC is shutdown and stops switching.

2. PIN DESCRIPTION

I2C Clock

Source Switch

Source Ground

Boost Zero-current Detect

Rectifier Voltage Sense

No Connection

SCL

SDAI

C Data

SOURCE

SGND

BSTAUX

eOTP

FBSENSE

GND

GD Gate Driver

VDD

IC Supply Voltage

FBAUX

Second Stage Zero-current Detect

BSTOUT

Boost Output Voltage Sense

IAC

CLAMP

oltage Clamp Current Source

16-lead SOIC

SYNC

External Overtemperature Protection

Second Stage Current Sense

Ground

Second Stage Synchronization

Figure 2. CS1630/31

CS1630/31

Pin Name

BSTAUX

IAC

CLAMP

SGND

SOURCE

SDA

SCL

SYNC

eOTP

FBSENSE

GND

VDD

FBAUX

BSTOUT

DS954F3 5

Pin # I/O

1IN

2IN

3OUT

4PWR

5IN

6 I/O

7IN

9OUT

10 IN

11 IN

12 PWR

13 OUT

14 PWR

15 IN

16 IN

Description

Boost Zero-current Detect — Boost Inductor demagnetization sensing input for

zero-current detection (ZCD) information. The pin is connected to the PFC boost inductor auxiliary winding through an external resistor divider.

Rectifier Voltage Sense — A current proportional to the rectified line voltage is fed into this pin. The current is measured with an A/D converter.

Voltage Clamp Current Source — Connect to a voltage clamp circuit on the output of the boost stage.

Source Ground — Common reference current return for the SOURCE pin.

Source Switch — Connected to the source of the boost stage external high-voltage

FET.

I2C™ Data — I2C data.

I2C™ Clock — I2C clock.

No Connection — Leave pin unconnected.

Second Stage Synchronization — A digital synchronization signal that indicates

which channel the controller is signaling for each gate switching period. External Overtemperature Protection — Connect an external NTC thermistor to this pin, allowing the internal A/D converter to sample the change to NTC resistance.

Second Stage Current Sense — The current flowing in the second stage FET is sensed across a resistor. The resulting voltage is applied to this pin and digitized for use by the second stage computational logic to determine the FET's duty cycle. Ground — Common reference. Current return for both the input signal portion of the IC and the gate driver.

Gate Driver — Gate drive for the second stage power FET.

IC Supply Voltage

— Connect a storage capacitor to this pin to serve as a reservoir for

operating current for the device, including the gate drive current to the power transistor.

Second Stage Zero-current Detect — Second stage inductor sensing input. The pin is connected to the second stage inductor’s auxiliary winding through an external resistor divider. Boost Output Voltage Sense — A current proportional to the boost output is fed

into this pin. The current is measured with an A/D converter.

CS1630/31

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 Electrical Characteristics

Typical characteristics conditions:

=25ºC, VDD= 12V, GND = 0V

•T

• All voltages are measured with respect to GND.

• Unless otherwise specified, all currents are positive when flowing into the IC.

Parameter Condition Symbol Min Typ Max Unit

VDD Supply Voltage

Operating Range After Turn-on V

Turn-on Threshold Voltage V

Turn-off Threshold Voltage (UVLO) V

Zener Voltage (Note 1) I

Increasing V

Decreasing V

=20mA V

VDD Supply Current

Startup Supply Current V

Operating Supply Current (Note 5)

DD<VST(th)

CL= 0.25nF, Fsw60 kHz

Reference

Reference Current

CS1630 CS1631

= 200 V

BST

= 400 V

BST

Boost

Maximum Switching Frequency f

Clamp Current I

Dimmer Attach Peak Current

CS1630 CS1631

108  V 207 V

line

Boost Zero-current Detect

BSTZCD Threshold V

ZCD Sink Current (Note 2) I

BSTAUX Upper Voltage I

BSTZCD

Boost Protection

Clamp Turn-on

CS1630 CS1631

108  V 207 V

line

Second Stage Zero-current Detect

FBZCD Threshold V

ZCD Sink Current (Note 2) I

FBAUX Upper Voltage I

=1mA - VDD+0.6 - V

FBZCD

Second Stage Current Sense

Peak Control Threshold V

Delay to Output --100ns

Minimum/Maximum characteristics conditions:

= -40°C to +125°C, VDD= 11V to 17V, GND = 0 V

•T

ST(th)

STP(th)

11 - 17 V

-8.5-V

-7.5-V

18.5 - 19.8 V

--200A

-5.8-mA

132 253

ref

BST(Max)

CLAMP

BSTZCD(th)

BSTZCD

--200kHz

--3.8-mA

-200-mV

-2 - - mA

133 133

590 508

A A

mA mA

=1mA - VDD+0.6 - V

132 253

FBZCD(th)

FBZCD

Pk_Max(th)

-200-mV

-2 - - mA

-1.4-V

146.7

141.7

A A

6 DS954F3

CS1630/31

GD OU T

GND

VDD

Buffer

+15V

-15V

0.25 nF

Parameter Condition Symbol Min Typ Max Unit

Second Stage Pulse Width Modulator

Minimum Switching Frequency t

Maximum Switching Frequency t

FB(Min)

FB(Max)

Second Stage Gate Driver

Output Source Resistance

Output Sink Resistance

Rise Time (Note 5)

Fall Time (Note 5)

VDD=12V

CL=0.25nF

Second Stage Protection

Overcurrent Protection (OCP) V

Overvoltage Protection (OVP) V

Open Loop Protection (OLP) V

OCP(th)

OVP(th)

OLP(th)

External Overtemperature Protection (eOTP)

Pull-up Current Source – Maximum I

CONNECT

Conductance Accuracy (Note 3) - - ±5 

Conductance Offset (Note 3) - ± 250 - nS

Current Source Voltage Threshold V

CONNECT(th)

Internal Overtemperature Protection (iOTP)

Thermal Shutdown Threshold (Note 4) T

Thermal Shutdown Hysteresis (Note 4) T

Notes: 1. The CS1630/31 has an internal shunt regulator that limits the voltage on the VDD pin. VZ, the shunt regulation voltage, is defined

in the VDD Supply Voltage section on page 6.

2. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased does not exceed specification.

3. Conductance is the inverse of resistance (1/) and is expressed in siemens (S). A decrease in conductance is equivalent to an increase in resistance.

4. Specifications are guaranteed by design and are characterized and correlated using statistical process methods.

5. For test purposes, load capacitance (C

) is 0.25nF and is connected as shown in the following diagram.

SD(Hy)

-625-Hz

-200-kHz

-24-

-11-

--30ns

--20ns

-1.69-V

-1.25-V

-200-mV

-80-A

-1.25-V

-135-ºC

-14-ºC

DS954F3 7

3.2 I2C™ Port Switching Characteristics

Stop

SDA

SCL

susp

Stop

hdst

sust

hddo

sud

high

hddi

low

hdst

buf

Start

Repeated

Start

Test conditions (unless otherwise specified):

• Inputs: Logic 0 = GND = 0 V, Logic 1 = 3.3 V.

• The CS1630 / 31 control port only supports I

• It is recommended that a 2.2 k pull-up resistor be placed from the SDA pin to V

Parameter Symbol Min Typ Max Unit

SCL Clock Frequency f

Bus Free Time Between Transmissions t

Start Condition Hold Time (prior to first clock pulse) t

Clock Low time t

Clock High Time t

Setup Time for Repeated Start Condition t

SDA Input Hold Time from SCL Falling

SDA Setup time to SCL Rising t

Setup Time for Stop Condition t

SDA Input Voltage Low V

SDA Input Voltage High V

SDA Output Voltage Low V

C slave functionality.

scl

buf

hdst

low

high

sust

hddi

sud

susp

CS1630/31

--400kHz

1.3 - - µs

0.6 - - µs

1.3 - - µs

0.6 - - µs

0-0.9µs

100 - - ns

0.6 - - µs

-1.5-V

-1.85-V

-0.25-V

8 DS954F3

CS1630/31

3.3 Power Line Calibration Characteristics

Typical characteristics conditions:

•TA=25ºC, VDD= 12V, GND = 0V

• All voltages are measured with respect to GND.

• Unless otherwise specified, all current is positive when flowing into the IC.

Parameter (Note 6) Min Typ Max Units

Input Line Frequency (Note 7) 47 50/60 63 Hz

Input Voltage (Note 7)

CS1630 CS1631

Dual-bit 00 (“00”) 24 34 44 Degrees

Dual-bit 01 (“01”) 52 62 72 Degrees

Dual-bit 10 (“10”) 108 118 128 Degrees

Dual-bit 11 (“11”) 136 146 156 Degrees

Special Character (SC) 80 90 100 Degrees

Notes: 6. The CS1630/31 supports leading-edge phase-cut waveforms only for power line calibration.

7. Range is recommended for power line calibration operation only.

Minimum/Maximum characteristics conditions:

TJ=25ºC, VDD= 11V to 17V, GND = 0 V

114 218

120 230

126 242

V V

DS954F3 9

CS1630/31

3.4 Thermal Resistance

Symbol Parameter Value Unit



Junction-to-ambient Thermal Impedance 2 Layer PCB

Junction-to-case Thermal Impedance 2 Layer PCB

4 Layer PCB

3.5 Absolute Maximum Ratings

Characteristics conditions:

All voltages are measured with respect to GND.

Pin Symbol Parameter Value Unit

14 V

1, 2, 5, 6, 7, 9,

10, 11, 15, 16

1, 2, 6, 7, 9, 10,

11,15,16

13 V

13 I

SOURCE

-P

-T

All Pins ESD

CLAMP

Stg

IC Supply Voltage 18.5 V

Analog Input Maximum Voltage -0.5 to (V

Analog Input Maximum Current 5 mA

Gate Drive Output Voltage -0.3 to (VDD+0.3) V

Gate Drive Output Current -1.0 / +0.5 A

Current into Pin 1.1 A

Clamp Output Current 5 mA

Total Power Dissipation 400 mW

Junction Temperature Operating Range (Note 8) -40 to +125 ºC

Storage Temperature Range -65 to +150 ºC

Electrostatic Discharge Capability Human Body Model

Charged Device Model

84 47

39 31

2000

500

°C/W °C/W

+0.5) V

V V

Note: 8. Long-term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at

the rate of 50mW/ ºC for variation over temperature.

WARNING:

Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

10 DS954F3

4. TYPICAL PERFORMANCE PLOTS

-50 0 50 100 150

UVLO Hysteresis

Temperature (°C)

-2

0 2 4 6 8 10 12 14 16 18 20

(mA)

VDD(V)

-50 0 50 10 0 150

VDD (V)

Temperature (

°C)

Turn On

Turn Off

18.5

19.5

-50 0 50 100 150

(V)

Temperature (C°)

-50 0 50 100 150

OUT

(:)

Temperature (ºC)

Source

Sink

-2

-1.5

-1

-0.5

0.5

-50 0 50 100 150

Drift (%)

Temperature (°C)

CS1630/31

Figure 3. UVLO Characteristics

Figure 5. Turn-on/off Threshold Voltage vs. Temperature

Figure 4. Supply Current vs. Voltage

Figure 6. Zener Voltage vs. Temperature

Figure 7. Gate Drive Resistance vs. Temperature

DS954F3 11

Figure 8. Reference Current (I

) Drift vs. Temperature

ref

5. GENERAL DESCRIPTION

5.1 Overview

The CS1630/31 integrates a critical conduction mode (CRM) boost converter, providing power factor correction and superior dimmer compatibility with a primary-side regulated quasiresonant second stage, which is configurable for isolated and non-isolated topologies. The digital CCT control system provides the ability to program dimming profiles, such as constant CCT dimming and black body line dimming. The CS1630/31 optimizes LED color mixing by temperature compensating LED current with an external negative temperature coefficient (NTC) thermistor. The IC controller is also equipped with power line calibration for remote system calibration and end-of-line programming. The CS1630/31 provides a register lockout feature for security against potential access to proprietary registers.

5.2 Startup Circuit

An external, high-voltage source-follower circuit is used to deliver startup current to the IC. During steady-state operation, an auxiliary winding on the boost inductor biases this circuit to an off state to improve system efficiency, and all IC supply current is generated from the auxiliary winding. The patent pending technology of the external, high-voltage sourcefollower circuit enables system compatibility with digital dimmers (dimmers containing an internal power supply) by providing a continuous path for a dimmer’s power supply to recharge during its off state. During steady-state operation, high-voltage FET Q1 is source-switched by a variable internal current source on the SOURCE pin to create the boost circuit. A Schottky diode with a forward voltage less than 0.6V is recommended for diode D5. Schottky diode D5 will limit inrush current through the internal diode, preventing damage to the IC.

5.3 Dimmer Switch Detection

The CS1630/ 31 dimmer switch detection algorithm determines if the solid-state lighting system is controlled by a regular switch, a leading-edge dimmer, or a trailing-edge dimmer. Dimmer switch detection is implemented using two modes: Dimmer Learn Mode and Dimmer Validate Mode. These assist in limiting the system power losses. Once the IC reaches UVLO start threshold V in Dimmer Learn Mode, allowing the dimmer switch detection

and begins operating, the CS1630/31 is

ST(th)

CS1630/31

circuit to set the operating state of the IC to one of three modes: No-dimmer Mode, Leading-edge Mode, or Trailing-edge Mode.

5.3.1 Dimmer Learn Mode

In Dimmer Learn Mode, the dimmer detection circuit spends approximately two line-cycles learning whether there is a dimmer switch and, if present, whether it is a trailing-edge or leading-edge dimmer. A modified version of the leading-edge algorithm is used. The trailing-side slope of the input line voltage is sensed to decide whether the dimmer switch is a trailing-edge dimmer. The dimmer detection circuit transitions to Dimmer Validate Mode once the circuit detects that a dimmer is present.

5.3.2 Dimmer Validate Mode

During normal operation, CS1630/31 is in Dimmer Validate Mode. This instructs the dimmer detection circuit to periodically validate that the IC is executing the correct algorithm for the attached dimmer. The dimmer detection algorithm periodically verifies the IC operating state as a protection against incorrect detection. As additional protection, the output of the dimmer detection algorithm is low-pass filtered to prevent noise or transient events from changing the IC’s operating mode. The IC will return to Dimmer Learn Mode when it has determined that the wrong algorithm is being executed.

5.3.3 No-dimmer Mode

Upon detection that the line is not phase cut with a dimmer, the CS1630/ 31 operates in No-dimmer Mode, where it provides a power factor that is in excess of 0.9. The CS1630/31 accomplishes this by boosting in CRM and DCM mode. The peak current is modulated to provide link regulation. The CS1630/ 31 alternates between two settings of peak current. To regulate the boost output voltage, the CS1630/31 uses a peak current set by register PEAK_CUR (see "Peak Current (PEAK_CUR) – Address 51" on page 39). The time that this current is used is determined by an internal compensation loop to regulate the boost output voltage. The internal algorithm will reduce the peak current of the boost stage to maintain output voltage regulation and obtain the desired power factor.

5.3.4 Leading-edge Mode

In Leading-edge Mode, the CS1630/31 regulates boost output voltage V Figure 9. on page 13). The device executes a CCM boost algorithm using dimmer attach current as the initial peak current for the initial firing event of the dimmer. Upon gaining control of the incoming current, the CS1630/ 31 transitions to a CRM boost algorithm to regulate boost output voltage V device periodically executes a probe event on the incoming

while maintaining the dimmer phase angle (see

BST

. The

12 DS954F3

CS1630/31

Figure 9. Leading-edge Mode Phase-cut Waveform

Figure 10. Trailing-edge Mode Phase-cut Waveform

Gain

White

dim

White

ref

White

ref

Color

ADC

NTC

Color

Gain

Color

Figure 11. Block Diagram of Color Control System

waveform. The information from the probe event is used to maintain proper operation with the dimmer circuitry.

5.3.5 Trailing-edge Mode

In Trailing-edge Mode, the CS1630/31 determines its operation based on the falling edge of the input voltage waveform (see Figure 10). To provide proper dimmer operation, the CS1630/ 31 executes the boost algorithm on the falling edge of the input line voltage that maintains a charge in the dimmer capacitor. To ensure maximum compatibility with dimmer components, the device boosts during this falling edge event using a peak current that must meet a minimum value. Trailing-edge Mode, only the CRM boost algorithm is used.

Red and amber LEDs are necessary components in color-mixing applications when providing warm white or other CCTs. When mixing colors, red and amber LEDs are the most temperature sensitive, so they cause a large variation in temperature. The CS1630/31 is capable of providing LED CCT and luminosity with temperature compensation using the NTC thermistor to resolve the significant change in the luminous output due to temperature variations.

Since LED lumens are mainly a function of temperature and forward current, color temperature and luminosity can be maintained by independently adjusting each string's output current as the ambient temperature changes. This can be done by mapping the NTC reading to a required value of the current in each string using a digital mapping block.

In the CS1630/31, only one of the LED string currents is compensated for due to temperature variations. The current in the other string is kept constant over temperature, which may result in the luminosity decreasing slightly as temperature increases. In order for the ADC to resolve the entire range of possible temperature variation in the LEDs, it is recommended to select series resistor R

and NTC resistor R

appropriate Beta value, which retains the total resistance (RS+R

) at all possible operating temperatures within the

NTC

tracking range of the ADC. The final temperature-to-digital code mapping depends on these variables.

The CS1630/31 color control system also has the ability to maintain a constant CCT or change CCT as the light dims.

OTP configurations allow the selection of the dimming profile. A specific CCT profile can be programmed to the digital mapping device. In this case, the mapping is two-dimensional: one current versus temperature profile is generated for each dim level. The CS1630/31 provides two-dimensional mapping for the color LED’s current only, and one-dimensional mapping (current versus dim level) for the other string. A simplified block diagram of the color control system is shown in Figure 11.

NTC

with the

5.4 Correlated Color Temperature Control

The CS1630/31 color control system can adjust and maintain the correlated color temperature (CCT) for the LED colormixing application by connecting an external negative temperature coefficient (NTC) thermistor to the eOTP pin. The LED temperature variation can be accurately detected by the internal eOTP feedback loops Protection" on page 19).

DS954F3 13

(see "External Overtemperature

CS1630/31

where,

T = the measured normalized temperature and is 0 T 1.0

D = the normalized dim value and is 0

D1.0

GAIN

DTR

= gain of the channel based on the temperature measurement and the dim value:

where,

D = the normalized dim value and is 0

D1.0

GAIN

= gain of the channel based on the dim value

GAIN

DTR

P30 T3 P20 T2 P10++T P03 D3 P02++D2 P01 D P21 T2D++= P12 T D2 P11 T D P00+++

[Eq.1]

GAIN

Q3= D3 Q2 D2 Q1 D Q0+++

[Eq.2]

IN max

 I

PKVRMS typ



------------------------------------------------

[Eq.3]

The reference currents are the required values at ambient temperature TA= 25ºC and dim = 100%. They are multiplied by the appropriate gains, and these values are passed to the final power stage. The CS1630 / 31 uses polynomial approximations in one and two dimensions to generate the color gains. These polynomials can be up to third-order.

GAIN compensation profile and dimming profile of the temperaturesensitive LEDs (see Equation 1). Profiles are programmed through the Color Polynomial Coefficient registers (see "Color Polynomial Coefficient (P30, P20, P10, P03, P02, P01, P21, P12, P11, P00) – Address 5 - 24" on page 29).

GAIN white LEDs (see Equation 2). The profile is programmed through the Color Polynomial Coefficient registers (see "Color Polynomial Coefficient (Q3, Q2, Q1, Q0) – Address 25 - 32" on page 30).

Cirrus Logic, Inc. and its affiliates and subsidiaries generally make no representations or warranties that the combination of Cirrus Logic’s products with light-emitting diodes (“LEDs”), converter materials, and/or other components will not infringe any third-party patents, including any patents related to color mixing in LED lighting applications, such as, for example, U.S. Patent No. 7,213,940 and related patents of Cree, Inc. For more information, please see Cirrus Logic’s Terms and Conditions of Sale, or contact a Cirrus Logic sales representative.

approximations create a custom temperature

DTR

approximation allows custom dimming profile of the

5.5 Dimming Signal Extraction and the

5.6 Boost Stage

The high-voltage FET in the source-follower startup circuit is source-switched by a variable current source on the SOURCE pin to operate a boost circuit. Peak FET switching current is set by the PEAK_CUR register (see "Peak Current (PEAK_CUR) – Address 51" on page 39).

In No-dimmer Mode, the boost stage begins operating when the start threshold is reached during each rectified half line-cycle and is disabled at the nominal boost output voltage. The peak FET switching current determines the percentage of the rectified input voltage conduction angle over which the boost stage will operate. The control algorithm adjusts the peak FET switching current to maximize the operating time of the boost stage, thus improving the input power factor.

When operating in Leading-edge Mode, the boost stage ensures the hold current requirement of the dimmer is met from the initiation of each half-line dimmer conduction cycle until the peak of the rectified input voltage. Trailing-edge Mode boost stage ensures that the trailing-edge is exposed at the correct time with the correct current.

5.6.1 Maximum Peak Current

The maximum boost inductor peak current is configured by adjusting the peak switching current with peak current code I (PEAK_CUR) – Address 51" on page 39) is used to store peak current code I to peak current code I

. The PEAK_CUR register (see "Peak Current

PK(code)

. Maximum power output is proportional

PK(code)

, as shown in Equation 3:

PK(code)

Dim Mapping Algorithm

When operating with a dimmer, the dimming signal is extracted in the time domain and is proportional to the conduction angle of the dimmer. A control variable is passed to the quasi-resonant second stage to achieve output currents from 0% to 100%.

where,

 = the correction term at 0.55

RMS(typ)

= nominal operating input RMS voltage

= peak current code I

PK(code)

 4.1mA

14 DS954F3

CS1630/31

BST

CS1630 /31

15 k

ADC

BST

BSTOUT

ref

BSTOU T

Figure 12. BSTOUT Input Pin Model

BST

ref

--------------

400V

133A

------------------

3M==

[Eq.4]

IA C

IAC

rect

CS1630 /31

15 k

ADC

ref

Figure 13. IAC Input Pin Model

IAC

BST

[Eq.5]

5.6.2 Output BSTOUT Sense & Input IAC Sense

A current proportional to boost output voltage V to the IC on pin BSTOUT and is used as a feedback control signal (see Figure 12). The ADC is used to measure the magnitude of current I magnitude of current I reference current I

Resistor R

BST

of 133A.

ref

sets the feedback current at the nominal boost

BSTOUT

through resistor R

BSTOUT

is then compared to an internal

output voltage. For 230VAC line voltage applications, resistor R

is calculated as shown in Equation 4:

BST

where,

= nominal boost output voltage

BST

= internal reference current

ref

For 120VAC line voltage applications (CS1630), nominal boost output voltage V

is 200V, and resistor R

BST

1.5M. By using digital loop compensation, the voltage

feedback signal does not require an external compensation network.

A current proportional to the AC input voltage is supplied to the IC on pin IAC and is used by the boost control algorithm (see Figure 13).

is supplied

BST

. The

BST

Resistor R

For optimal performance, resistors R 1% tolerance or better resistors for best V

sets current IAC and is derived from Equation 5:

IAC

and R

should use

BST

voltage

accuracy.

5.6.3 Boost Auxiliary Winding

The boost auxiliary winding is used for zero-current detection (ZCD). The voltage on the auxiliary winding is sensed through the BSTAUX pin of the IC. It is also used to deliver startup current during startup time (see "Startup Circuit" on page 12).

5.6.4 Boost Overvoltage Protection

The CS1630/31 supports boost overvoltage protection (BOP) to protect the bulk capacitor C8 (see Figure 14. on page 16). If the boost output voltage exceeds the overvoltage protection thresholds programmed in the OTP registers a BOP fault signal is generated. The voltage level, V within 227V to 257V for a CS1630 and 432V to 462V for a CS1631 (see "Configuration 53 (Config53) – Address 85" on page 45). The control logic continuously averages the BOP fault signal using a leaky integrator. When the output of the leaky integrator exceeds a certain threshold, which can be set using bits BOP_INTEG[3:0] in register Config53 (see "Configuration 53 (Config53) – Address 85" on page 45), a boost overvoltage fault is declared and the system stops boosting. More information on the leaky integrator size and sample rate is provided in section 6.23 "Configuration 18 (Config18) – Address 50" on page 38.

During a boost overvoltage protection event, the second stage is kept enabled only if the MAX_CUR bit in register Config45 (see "Configuration 45 (Config45) – Address 77" on page 40) is set to ‘1’ (enabled), and its dim input is railed to full scale. This allows the second stage to quickly dissipate the stored energy on the bulk capacitor C8, bringing down the boost output voltage to a safe value. A visible flash on the LED might appear, indicating that an overvoltage event has occurred. When the boost output voltage drops to 195V (for a 120V application), or 392V (for a 230V application), the boost stage is enabled if bit BOP_RSTART in register Config54 (see "Configuration 54 (Config54) – Address 86" on page 46) is set to ‘1’, and the system returns to normal operation. If bit BOP_RSTART is set to ‘0’, a boost overvoltage fault is latched and the system stays in the fault mode until the input power is recycled.

BOP(th)

, can be set

DS954F3 15

5.7 Voltage Clamp Circuit

To keep dimmers conducting and prevent them from misfiring, a minimum power needs to be delivered from the dimmer to the load. This power is nominally around 2W for 230 V and 120V TRIAC dimmers. At low dim angles ( power cannot be converted into light by the second stage due to the dim mapping at light loads. The boost output voltage V

can rise above the safe operating voltage of the

BST

primary-side bulk capacitor C8.

90°), this excess

CS1630/31

CLAMP

R10

CLAMP

BST

CS1630 /31

VDD

Figure 14. CLAMP Pin Model

R13

R11

R14

CS1630/31

FBAUX

GND

FBSENSE

BST

R12

C11

C12

D11

R15 D10

R16

C10

IGND

LED2 +

LED 1+

LED 1-

LED2 -

GND

_QVCC

Figure 15. Flyback Parallel Output Model

R13

R11

R14

CS1630 /31

FBAUX

GND

FBSENSE

BST

R12

C11

C12

D11

R15 D10

R16

C10

IGND

LED 2+

LED1 +

LED 1-

LED 2-

GND

_QVCC

Figure 16. Buck Parallel Output Model

The CS1630/31 provides active clamp circuitry on the CLAMP pin, as shown in Figure 14.

A PWM control loop ensures that the boost output voltage V

does not exceed 227V for 120VAC applications

BST

or 424V for 230VAC applications. This control turns on the BJT of the voltage clamp circuit, allowing the clamp circuit to sink current through the load resistor, preventing boost output voltage V

from exceeding the maximum safe voltage.

BST

5.7.1 Clamp Overpower Protection

The CS1630/31 clamp overpower protection (COP) control logic continuously monitors the turn-on time of the clamp circuit. If the cumulative turn-on time exceeds 84.48ms during the internally generated 1 second window time, a COP event is actuated, disabling the boost and second stages. The clamp circuitry is turned off during the fault event.

Figure 15 illustrates a quasi-resonant flyback stage configured for two-channel parallel output.

The flyback stage is controlled by measuring current in the transformer primary and voltage on the auxiliary winding. Quasi-resonant operation is achieved by detecting transformer flyback using an auxiliary winding.

A quasi-resonant buck stage configured for two-channel parallel output is illustrated in Figure 16.

5.8 Quasi-resonant Second Stage

The second stage is a quasi-resonant current-regulated DCDC converter capable of flyback, buck, or tapped buck operation. The second stage output configuration is set by bit S2CONFIG in register Config12 (see "Configuration 12 (Config12) – Address 44" on page 36) and bits BUCK[3:0] in register Config10 (see "Configuration 10 (Config10) – Address 42" on page 35). To deliver the highest possible efficiency, the second stage can operate in quasi-resonant mode and provides constant output current with minimum line-frequency ripple. Primary-side control is used to simplify system design and reduce system cost and complexity.

The digital algorithm ensures monotonic dimming from 0 % to 100% of the dimming range with a linear relationship between the dimming signal and the LED current.

16 DS954F3

The buck stage is controlled by measuring current in the buck

R13

R11 R14

CS1630 /31

FBAUX

GND

FBSEN SE

BST

R12

C11

C12

D11

R15 D10

R16

C10

IGND

LED2 +

LED1 +

LED1 -

LED 2-

GND

_QVCC

Figure 17. Tapped Buck Parallel Output Model

R13

R11

R14

CS1630 /31

FBAUX

GND

FBSENSE

BST

R12

R15 D10

R16

C10

GND

_QVCC

IGND

C12

LED 2+

LED2 -

C11

LED 1+

LED 1-

D11

Figure 18. Flyback Series Output Model

R13

R11 R14

CS1630 /31

FBAUX

GND

FBSENSE

BST

R12

R15 D10

R16

C10

GND

_QVCC

IGND

D11

C12

LED1 +

LED1 -

C11

LED2 +

LED 2-

Figure 19. Buck Series Output Model

inductor and voltage on the auxiliary winding. Quasi-resonant operation is achieved by detecting buck inductor demagnetization using an auxiliary winding. The digital control algorithm rejects line-frequency ripple created on the second stage input by the front-end boost stage, resulting in the highest possible LED efficiency and long LED life.

The tapped buck stage operates similar to a buck stage. The tapped buck topology provides minimum turn-on time and improves conversion efficiency when large input-to-output voltage ratio is present. The tapped buck inductor behaves as a transformer for voltage conversion and is controlled by measuring current in the tapped inductor and voltage on the auxiliary winding. Quasi-resonant operation is achieved by detecting tapped inductor demagnetization using an auxiliary winding.

CS1630/31

Similarly, a series connection in a flyback stage and buck stage use an NMOS switch and a PMOS switch, respectively, as shown in Figures 18 and 19.

5.8.1 Series & Parallel Two-Channel Output

The CS1630/31 is designed to be programmed to support series or parallel two-channel output configurations using one set of power magnetics. Series or parallel configuration is set by bit STRING and bit LED_ARG in the Config3 register (see "Configuration 3 (Config3) – Address 35" on page 32). A parallel connection for a flyback stage and buck stage are connected differently: an NMOS switch is used in flyback configuration, and a PMOS switch is used in buck / tapped buck configuration (see Figures 15, 16, and 17).

DS954F3 17

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