or Pressure-sensitive copy paper
Size57.5±0.5 mm
Roll diameter80 mm or less
Paper thicknessUpper : 0.066mm
Lower : 0.058mm
— 1 —
Page 4
2. INITIALIZE (MAC) OPERATION
1. Set the mode switch to "OFF" position.
2. Press the "INIT SW".
3. Turn the mode switch to ""REG" (Except "OFF" or "Z") position.
4. Release the "INIT SW" .
5. Input the MAC CODE. (10 digits)
6. Press "#2" key.
7. Initialize operation is executed.
MAC CODE : D1 to D10 (10 digits)
D1 to D6: Date input data (DD-MM-YY) Note: YY= 00 (2000) to 99 (2099)
D7 to D9: Any number input digit.(exp : 000)
D10:select figure break point symbol (1:"." , 2: "," )
NOTE: In case the ECR works abruptly caused cange ROM without removing the battery,
Turn the power off and remove the battery connector then perform the MAC operation.
3. F-INIT (FMAC) OPERATION
1. Set the mode switch to "OFF" position.
2. Press the "INIT SW" .
3. Turn the mode switch to "REG" (Except "OFF" or "Z") position.
4. Release the "INIT SW".
5. Press "#2" key.
Note : The location of "#2" key, see "HARD KEY CODE TABLE" on page 18.
— 2 —
INIT SW
Page 5
4. BLOCK DIAGRAM
4-1. PCB CONNECTION
— 3 —
Page 6
4-2. BLOCK DIAGRAM (CIRCUIT)
Reset circuit
Printer
M190G
S80719AN
MD
FD
Head drive cuicuit
HD.A~HD.H
PWD detection
CPU
uPD78052G-A46-8BT
A8~A15
AD0~AD7
CUSTOMER DISPLAY
SH101MA
Sensor signal
DI,DO,CLK,STB
A0~A7
uPD16312GB-3B4
Select addess
AD0~AD5
MAIN DISPLA
SH101MAY
Segment & Digit data
DRWS
PNES
KC0~KC4
Keyboard
FPC
Mode
Key
VPP sensor circuit
RS232C circuit
ROM
RAM
A0~A7
A8~A15
FB0~FB5
FISCAL ROM
D0~D7
Address data bus
AD0~AD7
— 4 —
Page 7
5.DISASSEMBLY (FE-700)
5-1.MAIN PARTS
1.Open the printer cover.
Remove the 2 screws of the upper case.
Remove the 2 screws.
2.Slide the upper case to the front side.
3.Open upper case from the left side.
4.The battery is located at the printer fixing stand.
Battery VL3032/1F2
— 5 —
Page 8
5. Release the hook them Remove the write side.
Hook
6. Release 3screws to remove printer plastic stand.
Remove the 4 screws.
7. Release 2screws to remove printer unit.
Remove the 2 screws.
8. Release 1 screw to remove display case.
Remove 1 screw.
— 6 —
Page 9
9. Lift up upper case.
10. To remove the main PCB, release 7 screws and
2 screws for the COM port.
Remove the 7 screws.
Remove the 2 screws for the COM port.
— 7 —
Page 10
6.CIRCUIT EXPLANATION
6-1. Power supply circuit
Q1 : Power transistor
Q2 : Voltage detection transistor
A
B
C
D
Voltage level at above check point (unit : V )
Measurement
position
Voltage (V)12.5V5.3V6.2V 2.47V
AB CD
— 8 —
Page 11
6-2. CPU (IC11: uPD78052GC-A46-8BT)
Pin No.SignalDescriptionIn/Out
1FB3Fiscal ROM bank 3OutHighHigh
2FB4Fiscal ROM bank 4 / RAM bank 3OutHighHigh
3FB5Fiscal ROM bank 5 / RAM bank 4OutHighHigh
4AVSSGND-GNDGND
5PGMPRG signal for Fiscal ROMOutHighHigh
6RAMRAM disableOutHighLow
7AVREFVDD-5V5V
8RXDReceive dataInHighHigh
9TXDSend dataOutHighHigh
10WDWinder motor drive signalOutLowLow
11DIData signal from uPD16312InPulseHigh
12DOData signal to uPD16312OutPulseHigh
13CLKClock signal for uPD16312OutPulseHigh
14STBData strobe signal for uPD16312OutPulseHigh
15KC0Key common signal (KC0)OutPulseHigh
16KC1Key common signal (KC1)OutPulseHigh
17KC2Key common signal (KC2)OutPulseHigh
18KC3Key common signal (KC3)OutPulseHigh
19AD0Address / Data signal (AD0)In/OutPulseHigh
20AD1Address / Data signal (AD1)In/OutPulseHigh
21AD2Address / Data signal (AD2)In/OutPulseHigh
22AD3Address / Data signal (AD3)In/OutPulseHigh
23AD4Address / Data signal (AD4)In/OutPulseHigh
24AD5Address / Data signal (AD5)In/OutPulseHigh
25AD6Address / Data signal (AD6)In/OutPulseHigh
26AD7Address / Data signal (AD7)In/OutPulseHigh
27A8Address signal (A8)OutPulseHigh
28A9Address signal (A9)OutPulseHigh
29A10Address signal (A10)OutPulseHigh
30A11Address signal (A11)OutPulseHigh
31A12Address signal (A12)OutPulseHigh
32A13Address signal (A13)OutPulseHigh
33VSSGND-GNDGND
34A14Address signal (A14)OutPulseHigh
35A15Address signal (A15)OutPulseHigh
36INITINIT switch signalInLowLow
37VPPVPP OUT signalOutHighHigh
38DSRData set ready signalInHighHigh
39KC4Key common signal (KC4)OutPulseHigh
40RDOutput enable signal of RAM/ROM (RD)OutPulseHigh
41WRWrite enable signal of RAM (WR)OutPulseHigh
42RA14Address signal of ROM (Bank 0)OutHighHigh
43ASTBLatch enable for Addres decoder (ASTB)OutPulseLow
44KI12Key input signal (KI12)InHighHigh
45KI13Key input signal (KI3)InHighHigh
46RA16Address signal of ROM (Bank2)OutHighHigh
47RA15Address signal of ROM (Bank 1)OutHighHigh
48MDMotor drive signal of printer (MD)OutLowLow
49DRWDrawer drive signal (DRW)OutLowLow
50BUZBuzzer signal (BUZZ)OutLowLow
51FDPaper feed signal of printer (FD)OutLowLow
52HD.AHead drive signal of printer (HD.A)OutLowLow
53HD.BHead drive signal of printer (HD.B)OutLowLow
54HD.CHead drive signal of printer (HD.C)OutLowLow
55HD.DHead drive signal of printer (HD.D)OutLowLow
Status ofStatus of
Power On Power OFF
— 9 —
Page 12
Pin No.SignalDescriptionIn/Out
Status ofStatus of
Power On Power OFF
56HD.EHead drive signal of printer (HD.E)OutLowLow
57HD.FHead drive signal of printer (HD.F)OutLowLow
58HD.GHead drive signal of printer (HD.G)OutLowLow
59HD.HHead drive signal of printer (HD.H)OutLowLow
60RESETReset signal (RESET)In HighHigh
61DPDot pulse form printer (DP)InLowHigh
62RPReset pulse from printer (RP)InHighHigh
63OFFMode key status (OFF)OutHighLow
64PWDPower down signal (PWD)InLowHigh
65RB0Address signal for RAM (Bank 0)OutHighHigh
66RB1Address signal for RAM (Bank 1)OutHighHigh
67RB2Address signal for RAM (Bank 2)OutHighHigh
68VDDVDD-5V5V
69X2System clock ( 5MHz)InPulseHigh
70X1System clock ( 5MHz)InPulseHigh
71ICGND-GNDGND
72XT2Sub system clock (32.768KHz)InPulsePulse
73XT1Sub system clock (32.768KHz)InPulsePulse
74AVDDVDD-5V5V
75AVREF0VCC-GNDGND
76VPP.SVPP detection signal (VPP.S)InLowLow
77BATNon connection-HighHigh
78FB0Address signal of Fiscal ROM bank 0OutHighHigh
79FB1Address signal of Fiscal ROM bank 1OutHighHigh
80FB2Address signal of Fiscal ROM bank 2OutHighHigh
— 10 —
Page 13
6-3. Display controller (IC2: uPD16312GB-3B4)
Pin No.SignalDescriptionIn/Out
1SW1Not used (GND)-GNDGND
2SW2Not used (GND)-GNDGND
3SW3Not used (GND)-GNDGND
4SW4Not used (GND)-GNDGND
5DOUTData out signal to CPUOutHighHigh
6DINData in signal from CPUInPulseHigh
7VSSGND-GNDGND
8CLKClock signal (CLK)InPulseHigh
9STBData strobe signal (STB)InPulseHigh
10KEY12nd display sensor signal (D.TEST1)-LowLow
11KEY2Peper near end sensor signal (PNES)InHighHigh
12KEY3Drawer sensor signal (DRW.S)InHighHigh
13KEY4VCC-5V5V
14VDDVCC-5V5V
15SEG1Display segment signal (Sa)OutPulseLow
16SEG2Display segment signal (Sb)OutPulseLow
17SEG3Display segment signal (Sc)OutPulseLow
18SEG4Display segment signal (Sd)OutPulseLow
19SEG5Display segment signal (Se)OutPulseLow
20SEG6Display segment signal (Sf)OutPulseLow
21SEG7Display segment signal (Sg)OutPulseLow
22SEG8Display segment signal (Sdp)OutPulseLow
23SEG9Display segment signal (Str)OutPulseLow
24SEG10Display segment common signal (Scom)OutPulseLow
25SEG11Not usedLowLow
26SEG12Not usedLowLow
27VEEPower for display (-VN)--32V-32V
28GRD10Display digit signal (G10)OutPulseLow
29GRD9Display digit signal (G9)OutPulseLow
30GRD8Display digit signal (G8)OutPulseLow
31GRD7Display digit signal (G7)OutPulseLow
32GRD6Display digit signal (G6)OutPulseLow
33GRD5Display digit signal (G5)OutPulseLow
34GRD4Display digit signal (G4)OutPulseLow
35GRD3Display digit signal (G3)OutPulseLow
36GRD2Display digit signal (G2)OutPulseLow
37GRD1Display digit signal (G1)OutPulseLow
38VDDVCC -5V5V
39LED4Not used-PulseLow
40LED3Not used-PulseLow
41LED2Not used-PulseLow
42LED1Not used-PulseLow
43VSSGND-GNDGND
44OSCSystem clock (500KHz)InPulsePulse
Status ofStatus of
Power On Power OFF
— 11 —
Page 14
6-4. Initilize IC (Reset circuit)
VDD : Voltage of memory protection battery
To Pin No.60 of CPU
When the voltage level at Pin No.60 of CPU is not stabilized, CPU does not work properly
in rare case. Therefore, this machine uses the initialize IC for stabilizing the voltage.
Even the voltage lebel of VDD(Pin No.2) is changed, Pin No.1 of initilize IC outputs
stabilized 5 volts. When the VDD voltage become less than 1.9V, the initialize IC send a
reset signal to CPU.
6-5. Power down detection circuit (PWD)
To Pin No.64 of CPU
When the VP voltage become less than 4.8V, the pin No.1 of IC5 become "Low" level.
Then,the transistor Q43 become OFF.
When Q43 become OFF, the voltage lebel of pin No.64 of CPU changes to "High" level
from "Low". Then, CPU knows power failure.
6-6. Address latch circuit
CPU uses 8 port (AD0 ~ AD7) for address bus
and data bus.
To select the address, CPU use the IC13.
CPU send the address to IC13, and send ASTB
signal at same time.
Then, IC13 store the address and output the
address immediately.
In this way, CPU select the address and data
signal.
— 12 —
Page 15
6-7. RAM / ROM / Fiscal ROM bank selection circuit
A11
PGM
C64
100P
VCC
R123
56K
GND
IOGATE
HC32A
GATE
IC22
IC22
IC22
3
HC32A
11
HC32A
8
HC32A
IC22
F. ROM1
F.ROM2
PGM
EEPCE
1
2
12
13
9
9
10
This circuit is used for address decoder for mamory.
Memory Map
0000
2000
Mask ROM
(16K)
000000
Bank
0
4000
EP ROM
6000
Common (16K)
8000
EP ROM
Bank select area
A000
(16K)
C000
RAM common area
(8K)
E000
RAM BANK select
area (4K)
F000
Outer I/O area
FA80
Internal RAM
(High speed access)
FFFF
RAM256K
00001
Bank
1
00011
00010
Bank
2
Direct access
window for
Fiscal ROM
(2K)
KI signal port (F800,F801)
Buffer RAM 32 bytes
Internal RAM
(High speed access)
288 bytes
Internal RAM
(High speed access)
Short direct area
192 bytes
General purpose
register 32 bytes
Special function
register (SFR)
256 bytes
Bank
3
00100
Bank
4
00101
00110
Bank
5
F000
F800
FAC0
FAE0
FD00
FE20
FEE0
FFF0
RAM 1M
11101
Bank
29
— 13 —
Page 16
6-8. Fiscal ROM address and data selection
This circuit is used for interface of Fiscal ROM.
To improve the signal level of interface, this machine is used buffer IC (TC74HC367A) at
all signal lines.
IC8 is used for the gate of data bus between te Fiscal ROM and CPU.
— 14 —
Page 17
6-9. Head drive circuit for printer
TR4
TR5
Motor drive circuit
Normally, the transistor of motor drive circuit is followng condition.
TR3
TR1
TR2
TR1,TR2,TR5 :OFF
TR3, TR4 :ON
MD(-) signal :VP level
When the CPU want to rotate the motor, CPU change the MD signal to "High" from "Low".
Then, TR1,TR2 and TR5 are become ON and MD(-) signal is become GND level,
and then motor is rotated.
Head drive circuit
When the CPU wants to print, CPU send "High" signal from HD.A ~ HD.H terminal.
This signal goes to printer unit, and then print.
RP : Reset pulse from printer
DP : Dot pulse from printer
— 15 —
Page 18
6-10. VPP sensor circuit
This circuit is using for making the voltage when the CPU write the data to Fiscal ROM.
When the CPU wants to write the data to Fiscal ROM, CPU makes the "VPP.ON" signal
to "Low level".
DCS2 (PS10017): Booster circuit ( from 5V to 13V )
IC3 (M5237L) : IC for making 5V from 13V
The following test can be checked in the diagnostic test.
1. Key code test
2. Switch status test
3. Individul function test
4. FISCAL ROM, Vpp test
9999900000
(c) 2001 by CASIO
COMPUTER CO.,LTD.
All rights reserved.
7-3. Operation of each test
1. Key code test
When pressing a key, the machine displays
the following key code with the exception,
"FEED","C","0-9" button.
HARD KEY CODE TABLE
FEED055051
054050
053049
789
456
123
1 9
0 13
046040
045039
044038
DISPLAY
Hard key code
028022
027021
026
(#2)
052C
Note: "026" button is work for "#2" key.
0011012
— 18 —
043037
025
Page 21
7-4. Switch status test
Press "C" button, the switch status is appeared on the display.
[DISPLAY]
No display
No display
No display
No display
Pop up display
1: Not connected
0: Connected
INIT switch
1 : ON
0 : OFF
Vpp level of Fiscal ROM
1 : High level (12V)
0 : Low level (5V)
Paper near end sensor
1 : Normal (Open)
0 : Near End (Short)
Allways 1
Mode switch status
1 : PGM
3 : REG
4 : REG2
5 : X
6 : Z
No display : OFF
— 19 —
Page 22
7-5. Individual function test
1) Series test
This test will perform the following tests in series.
1. All display test (display all segment and TL,CG transactions)
2. Main ROM sum test
3. RAM read test (one time)
4. Drawer open test
5. Print test (one time)
6. Time set and display test (set date 31/12/2000, time 23:59:00 )
7. Issue receipt
8. Test display (1234567890 )
Operation : Y X 1 #2 Key
Y : 0 = Normal test ( It is not necessary to input "0". )
1 = The test will be performed even the error happened at ROM test.
X : 0 = Automatic RAM capacity check ( It is not necessary to input "0". )
1 = 256 K bytes RAM test
2 = 1M bytes RAM test
[PRINT] [DISPLAY]
# 1
ROM SUMOKE600
RAM32K R/WOK
BBBBBBBBBBBBBBBBBBBBBBBB
Error message
[PRINT]
MAIN ROM Error end
ROM ERE600
E600 : Check sum
Error end
RAM 32K ERBB AAAA
BB: Bank No. AAAA: Error address
— 20 —
Page 23
2) Print a ging test
This test will print 45 lines following print pattern in a one minutes.
Opeartion : Y X 2 #2 Key
Y : 0 = Normal test ( It is not necessary to input "0". )
1 = Continuous print test
X : 0 = Print 45 lines in a one minutes.
1 = Print 25 lines and open drawer 5 times in a one minutes.
[PRINT] [DISPLAY]
# 2
BBBBBBBBBBBB 88.88
3) RAM read only test
This test will check the RAM error.
Please check certainly this test after check of "RAM read write test
Opeartion : X 5 #2 Key
X : 0 = Read the data from start to end address and issues receipt.
1 = Read the data from start to end address continuously until power off.
Brink "-" signal on the display during checking.
[PRINT] [DISPLAY]
Normal end
X X X X
RAM 32K READ OK
Error end
RAM ERBB AAAA
BB: Bank No. AAAA: Error address
Note : The common area is no print of Bank Number.
— 21 —
Page 24
4) RS232C port test
This test will execute the RS232C loop back test continuously using loop back connector.
In case an error happens, the machine issues an error receipt then stop this test.
Test description :
1 : Level check at DSR signal ( Low/High)
2 : Send the data (0A5h) from TxD and receive it at RxD terminal.
To stop this test, turn the mode switch to "OFF" position.
Opeartion : 2 0 7 #2 KeyLoop back connection:
TxD2
RxD3
DSR6
[PRINT]
Normal EndError End
232C OK232CERX
X : Error code
0 : Time over
1 : Over run error
2 : Framing error
3 : RXD line data error
4 : DSR line receive error
5) All charactor print test
This test will print the all charactors inside printer controller.
Opeartion : 8 #2 Key
[PRINT] [DISPLAY]
# 8
6) Time display test
This test will display the time until pressing the C key.
Opeartion : 9 #2 Key
[DISPLAY]
— 22 —
Page 25
7-6. Fiscal ROM test
1) Fiscal ROM test
This test will check the fiscal ROM area for the test operation.
Opeartion : 1 X 7 #2 Key
X : 0= Fiscal ROM information print
1= Fiscal ROM data dump print
2= Fiscal ROM write test in the test area
3= VPP (Fiscal ROM write voltage) test
[PRINT]
Normal end
Fiscal NormalEnd
EPERR:00
Test Rest No0016
1 Way codeFFFF
GT Free Area2700
Sub ID:
9999999999999999
Note 1 :Fiscal ROM data dump print will print the data inside of the Fiscal ROM.
It will be printed out by 4 bytes unit. But, it will be skipped when the data is 0FFh.
During dump print time, "-" will be displayed at the left digit with brinking display.
Note 2 :Fiscal ROM wite test will write the test data in the test area. But, if the area is
not formatted, it will be error and test will be stopped. Also, if the test area is
empty, the machine will be error. After this test, the Fiscal ROM infromation print
will be preformed automatically.
Note 3 :VPP (Fiscal ROM write voltage) test will turn on the VPP voltage in the circuit.
And, the results will be display during the test time. To stop this test, turn off the
mode switch or pressing C key.
In case of error, the print will
be " Fiscal Error".
Error code
Balance of write test area
After fiscal system, it will change to "0000".
Balance of GT write area
The charactors will be changed to "Real ID" after
set the ID Number.
[DISPLAY] VPP test
X X X X X X X X X
0 : Vpp Low X : Any number
X X X X X X X X X
1 : Vpp High
7-8. To exit the diagnostic test
To escape the diagnostic test mode, execute " INITIALIZE (MAC)operation".
— 23 —
Page 26
8. ERROR CODE
8-1.Operation error code
When an error condition is generated, one of the following error codes (E01 – E94) is
displayed to indicate the cause of the error and the corrective action.
DISPLAY ERROR REMARKS/CORRECTIVE ACTION
E01Initialize or Flag clear operation errorRetry the operation correctly.
E03Mode switching errorMode switch is operated during registration.
E06Compulsory Subtotal keyFinalization operation entered without
operation error *1confirming subtotal.
E07Compulsory amount tenderFinalization operation entered without entering
entry error *1an amount tender.
E09Compulsory money declarationMoney declaration is not performed.
error *1Perform money declaration before operating
Return mode switch to previous setting.
Press subtotal key.
Enter tendered amount.
X/Z report.
E11No receipt message preset error *2Preset receipt message.
E15No tax status and no tax tableAttempt to perform registration when tax status
preset error(1, 2, 3 ,4, or 5) is not preset for each department
key and PLU No. Preset tax status for each
department key and PLU No. Also, the tax table
linked to the specified tax status 1, 2, 3 ,4 or 5
must be preset with appropriate program codes
E17ID No. error *2Enter the machine number.
E24Receipt message(TAXPayer)Predetermined number over Perform other operation
or buy a new ECR.
E28Transaction cancel buffer full error.Finalize the registration of operation.
E90EURO bulk switching errorSwitch to EURO after returning the totalizer to 0.
E94Printer ErrorRemove the cause and turn the power on (Mode-ON).
*1 These errors only occur when certain functions are programmed as compulsory.
*2 These errors only occur when the register is set as FISCAL ECR.
— 24 —
Page 27
8-2. Fiscal ROM error code
Error code will be printed when the machine has the Fiscal ROM memory trouble.
Error
Code
01
02
03
04
05
07
09
10
11
12
MeaningAction
Read after write error
Verify after write error
Read error
Hard error
Display PCB connection error
Z No. ≠ Fiscal last Z No.
GT over flow error
GT (ECR memory) ≠ GT (Fiscal ROM)
ID No. data error
GT data error
Initialize or Flag clear operation is necessary.
Initialize or Flag clear operation is necessary.
Initialize or Flag clear operation is necessary.
Initialize or Flag clear operation is necessary after
repair the machine.
Connect the display PCB cable. Then, Initialize or
Flag clear operation is necessary. Even if the error
happens, it is necessary to repair the display PCB.
Initialize or Flag clear operation is necessary.
It is not possible to release this error.
Initialize or Flag clear operation is necessary.
Initialize or Flag clear operation is necessary.
Initialize or Flag clear operation is necessary.
13
14,16
15,17
18
19
23,24
26
Fiscal ROM end
Fiscal ROM header data error
Fiscal ROM address line error
Temporary ID No. erase error
Blank check error
Fiscal ROM VAT data error
Fiscal ROM initialization time over error
It is not possible to release this error.
Initialize or Flag clear operation is necessary.
Initialize or Flag clear operation is necessary.
It is not possible to release this error.
It is not possible to release this error.
Initialize or Flag clear operation is necessary.
It is not possible to release this error.
Note: Even in case the error is not possible to release, the fiscal EP-ROM read
report can be issued by read operation after initialize or flag clear operation.
— 25 —
Page 28
8-3. System lock code
The following error code appears on display and receipt when the machine is lock up.
Execute the Flag MAC or MAC operation to clear these errors.
1Sequential trapThe machine try to write to accumulator when the CPU is
hung up.
2Memory write errorError happens when the CPU write the data to memory.
3Trap errorAbnormal address
7Stack pointer overAbnormal address or stack pointer has an error
9Memory creation errorShortage of memory
0Other errorCPU executes wrong jump vector before detect1,3 and
6 error code.
— 26 —
Page 29
9. IC DATA
1. BA10393 (IC5)2. MAX232N (IC27)
BA10393/BA10393F
OUT1
1
-IN1
2
+IN1
3
V
EE
4
3. M5237L (IC3)
M
52
37
L
321
Terminal
1. IN
2. GND
3. Voltage adjust
1
8
Vcc
OUT2
1ch
-
+
2ch
+
IN
(VI)
7
6
-
-IN2
+IN2
5
1
V
IN
C1+
T2
R2IN
VC1C2C2-
V-
OUT
2
3
4
5
6
7
8
MAXIM
MAX232
M5237
16
15
14
13
12
11
10
9
V
CC
GNO
TI
OUT
RI IN
RI OUT
TI IN
T2 IN
R2 OUT
IL
Output
(Vo)
OUT
R2
ASO protection
Heat
Start up
Vref
protection
Standard
Voltage
OP AMP
Current
protection
+
3
Voltage
adjust
R1
2
GND
4. S-80819ANY (IC4) /S-80825ANY/S-80845ANY (IC16)
(1) Nch open drain active low output
2
V
DD
+
-
V
RF.F
V
SS
4
(1) SC-82AB(2) TO-92(2) SOT-89-3
Top v i ew
443
112
OUT
2
V
DD
3
NC
V
SS
312
1
2
3
Bottom view
Top view
OUT
V
DD
V
SS
OUT
1
*
(4) SOT-23-5
1
2
3
312
Top view
OUT
V
DD
V
SS
— 27 —
(2) CMOS active low output
2
V
DD
V
RF.F
V
SS
4
S-808XX AX XX - XXX - T2
45
1
OU
2
V
DD
3
V
SS
4
NC
5
NC
312
*
+
-
OUT
1
*
Tape spec. IC direction
Production short No.
Package No.
NP: SC-82AB
MP: SOT-23-5
UP: SOT-89-3
Y: TO-92
Output
N: Nch open drain (Active "L")
L: CMOS (Active "L")
Detection Voltage X 10 times