Benq S52, Quanta ED2 Schematics

1
2
3
4
5
6
7
8
ED2-UMA DESIGN
A A
RUN POWER SW
PG 34
AC/BATT CONNECTOR
BATT CHARGER
PG 37
PG 37
Dothan
(478 Micro-FCPGA)
PG 5, 6
DC/DC +3V_SRC +5VSUS
PG 34
CPU VR
PG 33
CLOCKS
PG 17
VER : 1C
FSB 133MHZ
LVDS
DDR-SODIMM1
PG 15, 16
333 MHZ DDR I
Alviso 915GM/GML
TVOUT
1257 PCBGA
DDR-SODIMM2
B B
PG 15, 16
SATA - HDD
SATA0
PG 7,8,9,10, 11
DMI interface
USB2.0 (P0~P7)
PG 20
PATA - HDD
PATA 100
ICH6-M
PG 20
609 BGA
VGA
USB2.0 (P3) USB2.0 (P2) USB2.0 (P0~P1,P4)
LAN RTL8100S
PG 25
Internal ODD CD-ROM
PG 20
C C
AC97/Azalia
PG 12,13, 14
CARDBUS PC7411
PG 21,22,23
Panel Connector
S-Video
VGA
Bluetooth
USB2.0 I/O Ports
Magnetics
PCI Bus 33MHz
PG 18
PG 24
PG 19
PG 24
PG 24
PG 26
MINI-PCI
PG 24
S-Video reserved
PR-VGA
PR-USB2.0
P2 reserved for third USB
RJ45
PG 26
PR-LAN
Port Replicator
PG 31
Conexant Audio
PG 28
AUDIO
MDC DAA
Amplifier
PG 29
D D
Jack to Speaker
PG 29
1
Audio Jacks
PG 29
2
PG 30
MODEM RJ 11
PG 26
KBC
NS97551
PG 32
Matrix PG 27
3
Touch Pad
PG 27
LPC
X-Bus
Flash
PG 32
4
Super IO
LPC47N217
PG 31
PCMCIA CON.
PG 21
5
Card Reader
PG 22
Serial
Parallel
IrDA
IEEE1394 CONN.
PG 23
PG 31
Wireless LAN Card
PG 24
PR-COM
PR-Printer
PR-PS/2 PR-Audio outKey
Size Document Number Rev
Block Diagram 1
6
Date: Sheet
PROJECT : ED2
Quanta Computer Inc.
7
C2A
of
138Friday, October 22, 2004
8
1
2
3
4
5
6
7
8
PCI ROUTING TABLE
A A
REQ0# / GNT0# REQ2# / GNT2# REQ1# / GNT1#
IDSEL
AD24 AD19 AD17
INTERUPT
PIRQA# PIRQB# , PIRQD# PIRQC#,PIRQD#,PIRQA#
DEVICE
RTL8110S MINI-PCI TI 7411
SMB I
ICH6
CLK GEN
MOSFET
DIMM1
DIMM0
+3VSUS +3VRUN
B B
C C
SMB II
NS551
551 EPROM
Smart Battery
MOSFET
Thermal IC of CPU
+3VRUN+3VALW
D D
1
2
3
4
5
6
Size Document Number Rev
Block Diagram 2
Date: Sheet
PROJECT : ED2
Quanta Computer Inc.
7
238Friday, October 22, 2004
of
8
C2A
1
2
3
P
o
4
w
er
RailFlow
5
6
7
8
A A
CPU_VID[0..5]
VIN HWPG VRON
STP_CPU# DPRSLPVR
PSI
SC451
VHCORE
IMVP_PWRGD
CLK_EN#
DC_IN
VAFB
LM339 Charger
Battery
VIN +VCCP
MAINON +2_5VSUS
B B
SUSON HWPG
LM27281
AO4414
MAIND
VIN
SC1470
HWPG
AO4414
+1_5VSUSSUSON
+2_5VSUS
Pass Through for SUS Rail
+1_25VSUS
G2966
MAINON
+2_5VRUN
C C
Controlled for RUN Rail
+1_25VRUN
Diode
AO4411
+2_5VRUN
+1_5VRUN
FBMBATT
+5VRUN
AO4404
AOD4411
VIN
MAX1632A
PG
FB+3VRUN
AIC1117 AMCVDD
FB
FB+3VSUS
AVDD
+3V_MODEM
+15VALW
MAIND
+12VALW
+5VALW
MAIND
3.3VREF
+3VALW
HWPG
MAIND
S5_ON
FB
FB
AVDD_CLK
+3_3VDC
FB +3_3VDD
SUSD
SUSD
2N7002
AO4812
AO4812
SI5402
+12VRUN
+5VSUS
+5VRUN
+3VSUS
+3VRUN
+3V_S5
FAN_PWRAO6402+5VRUN
FB+5VRUN +5VODD
FB+3V_S5
+3V_LAN_D 1197
CTRL25
FB+2P5V_LAN
FB
DVDD_LAN+5VRUN +5VHDDFB
+3V_LAN_A
+3VRUN
D D
1
2
3
FB
+3VHDD
4
1197
5
6
+1P8V_LANCTRL18
Size Docum e n t N u mb er Re v
Block Diagram 3
Date: Sheet
7
PROJECT : ED2
Quanta Computer Inc.
338Friday, Oc t o ber 22, 2004
8
of
C2A
1
INDEX
Pg# Description
1-3
Schematic Block Diagram
4
FRONTPAGE
5-6
Dothan/Younah
7-11
A A
B B
ALVISO GM
12-14
ICH6M
15-16
DDRI SO-DIMM(200P)
17
CLOCK GENERATOR
18-19
LCD CONN & CRT CONN
20
SATA & IDE (HDD&CD_ROM)
PCI7411 & CONN & IEEE1394
21-23 24
MINI-PCI & MDC CONN
25-26
LAN & LAN Conn.
27
TOUCH PAD & FAN&KB
28
Azilia AC97 CODEC
Audio Amplifier
29 30 MODEM 31
DOCKING & SIO & FIR
32
KBC PC97551
33
CPU Power
34
3.3V/5V/12V/15V
1.5VSUS/1.5VRUN
35 36
+VCCP/+1.25V/+2.5V
37
Battery & Charger
2
DNI LIST
3
New Label
VA VIN MBATT +15VALW +12VALW +12VRUN
+5VALW
+5V_S5
+5VSUS +5VRUN +5VHDD +5VODD
+5VFDD
FAN_PWR VDDA AMCVDD 3V_MODEM
+3VALW +3V_S5 +3VSUS +3VRUN +3VHDD
4
Power and Ground
NOTE
NO USE
CONNECT TO +5VRUN DIRECTLY CONNECT TO +5VRUN DIRECTLY +5V ODD POWER NO USE
CONNECT TO +3VRUN DIRECTLY
Description
AC ADAPTER (20V) MAIN POWER (10~20V) MAIN BATTERY + (10~17V) +15V ALWAYS +12V ALWAYS +12V RUN
+5V ALWAYS & KBC POWER THIS POWER WILL BE TUNEED OFF IN S5 BATTERY MODE +5V S5 CONTROLED POWER +5V S3 CONTROLED POWER +5V HDD POWER
EXTERNAL FDD POWER (5V) FAN POWER (5V) Amplifier Power 5V RUN Plane AC97 Code DAC Power 3VRUN MODEM Power 3VSUS
8051 POWER (3V) THIS POWER WILL BE TUNEED OFF IN S5 BATTERY MODE SLP_S5# CTRLD POWER SLP_S3# CTRLD POWER SATA HDD Power
5
6
7
8
Control Signal or Source
MAINON
S5_ON
SUSD MAIND
+5VHDD_EN# +5VMOD_EN# +5VFDD_EN#
VFAN, MAX6657_OV# +5VRUN +3VSUS +5VRUN or +3VRUN
S5_ON SUSD MAIND
+3VHDD_EN#
+3V_LAN_D +3V_LAN_A +2P5V_LAN DVDD_LAN RTCVCC
LAN Digital Power LAN Analog Power LAN Analog Power LAN Digital Power 1.8 or 2.5V RTC & PCL POWER
+3V_S5 +3V_S5 +3V_LAN_D (+3V_S5) +2P5V_LAN(+3V_S5)
REF3V
+2_5VSUS +2_5VRUN
C C
+1_8VSUS +1_8VRUN +1_8V_M24
+1_5V_S5
NO USE NO USE NO USE
THIS POWER WILL BE TUNEED OFF IN S5 BATTERY MODE +1_5VSUS +1_5VRUN +1_25VSUS
AGP I/O POWER
SMDDR_VTERM +1_25VRUN
GND
AGND
GNDP
CGNDP
DC_GND
LANGND
NO USE NO USE
ALL PAGES
Page 28,29
NO USE
NO USE
DC Jcak
NO USE
ATI VGA 1.2V
ATI VGA COR E 1 . 0 / 1.2V
AGTL+ POWER (1.05V)
CPU CORE POWER (1.25/1.15V)
DIGITAL GROUND
AUDIO GND
CPU POWER GND
CHARGER GND
DC/DC POWER GND
COMBO CONN GND
4
5
VGA1_2V VGACORE
+VCCP VHCORE
D D
1
2
3
SUSON MAIND
+2_5VRUN
+1_8VSUS or +1_8VRUN
S5_ON SUSON MAIND +2_5VSUS MAINON +2_5VRUN MAINON, POW_SW MAINON VR_ON, HWPG
6
Size Document Number Rev
Date: Sheet of
7
PROJECT : ED2
Quanta Computer Inc.
Index
C2A
438Friday, October 22, 2004
8
1
HADSTB0#7 HADSTB1#7
HBREQ0#7
FERR#12
IGNNE#12
T91 *PAD T93 *PAD
INTR12 NMI12 STPCLK#12
CPUSLP#7,12
DPSLP#12
DPRSTP#12
1 2
HA#[3..31]
HREQ#07 HREQ#17 HREQ#27 HREQ#37 HREQ#47
ADS#7
BPRI#7
BNR#7
HLOCK#7
HIT#7
HITM#7
DEFER#7
HTRDY#7
RS#07 RS#17 RS#27
A20M#12
SMI#12
R3120_4
HA#[3..31]7
A A
B B
C C
CPUPWRGD12
SYS_RESET#13
G1: NC for Dothan and DPRSTP# for Yonah
D D
+VCCP
THERMTRIP#8,12
R311 56_4
1
2
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31
IERR#
BPM0# BPM1# BPM2# BPM3#
A20M# FERR# IGNNE# CPUPWRGD SMI#
TCK TDO TDI TMS TRST#
PREQ# PRDY# DBR#
STPCLK# CPUSLP# DPSLP#
THERMDA THERMDC
THERMTRIP1#
CPU_PROCHOT#
2
AA3 AA2
AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1
AE5
A13 A12 C12 C11 B13 A16 A15 B10 A10
B18 A18
C17 B17
P4
U4
V3
R3
V2
W1
T4
W2
Y4 Y1
U1
Y3
U3
R2
P3 T2 P1 T1
N2
A4
N4
J3
L1
J2
K3 K4 L4
C8
B8
A9 C9 M3 H1
K1
L2 C2
D3
A3
E4
B4
A7 D1
D4 C6
A6
B7 G1
CT_0505: Change footprint to BGA479M-SOCKET from L100505 from MPGA479M
U31A
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31#
ADSTB0# ADSTB1#
REQ0# REQ1# REQ2# REQ3# REQ4#
ADS#
IERR# BREQ0#
BPRI# BNR# LOCK#
HIT# HITM# DEFER#
BPM0# BPM1# BPM2# BPM3# TRDY# RS0# RS1# RS2#
A20M# FERR# IGNNE# PWRGOOD SMI#
TCK TDO TDI TMS TRST# ITP_CLK0 ITP_CLK1 PREQ# PRDY# DBR#
LINT0 LINT1 STPCLK# SLP# DPSLP# DPRSTP#
THERMDA THERMDC
THERMTRIP# PROCHOT#
Dothan Processor
REQUEST PHASE SIGNALS
ERROR SIGNALS
ARBITRATION PHASE SIGNALS
SNOOP PHASE SIGNALS
RESPONSE PHASE SIGNALS
PC COMPATIBILITY SIGNALS
DIAGNOSTIC & TEST SIGNALS
EXECUTION CONTROL SIGNALS
THERMAL DIODE
3
Dothan
1 OF 3
3
DATA PHASE SIGNALS
D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
DSTBN0# DSTBP0# DSTBN1# DSTBP1# DSTBN2# DSTBP2# DSTBN3# DSTBP3#
DINV0# DINV1# DINV2# DINV3#
DBSY# DRDY#
BCLK1 BCLK0
INIT#
RESET#
DPWR#
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9#
A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26
C23 C22 K24 L24 W25 W24 AE24 AE25
D25 J26 T24 AD20
M2 H2
B14 B15
B5 B11 C19
4
CPUINIT# CPURST#
4
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
HD#[0..63]
HDSTBN0# 7 HDSTBP0# 7 HDSTBN1# 7 HDSTBP1# 7 HDSTBN2# 7 HDSTBP2# 7 HDSTBN3# 7 HDSTBP3# 7
HDBI0# 7 HDBI1# 7 HDBI2# 7 HDBI3# 7
DBSY# 7 DRDY# 7
HCLK_CPU# 17 HCLK_CPU 17
+3VRUN
THERMDC
THERMDA
CPUINIT# 12 CPURST# 7 DPWR# 7
5
HD#[0..63] 7
R68 47
10 mil trace / 10 mil space
5
15 MIL
3V_THM
C83 .1U/10V_4
C86 2200P
Signal TDI TMS TRST# TCK TDO
FERR#
IERR#
CPUPWRGD
TCK TRST#
6
+3VRUN
R69 10K-0402
U18
1
VCC
3
DXN
2
DXP
-OVT4GND
MAX6657
SMDATA
SMCLK
-ALT
7 8 6 5
KBSMDAT KBSMCLK
ITP disable guidelines
Resistor Value 150 ohm +/- 5%
680 ohm +/- 5% GND 27 ohm +/- 5%
Open
Note: Populate R58, R62 when ITP connector is populated.
R60 56_4
1 2
R319 56_4
1 2
R58 200/F
1 2
R315 27.4/F
1 2 1 2
R62 680
6
Connect To
VTT VTT
GND VTT
+VCCP +3VSUS
R317
54.9/F
TDI TMS
TDO CPURST#
Size Document Number Rev
Date: Sheet
7
+3VRUN
Q14
2
2N7002
+3VRUN+3VRUN
2
1 2
R72 10K-0402
Q13 2N7002
3
3
+3VRUN
R310 10K-0402
1
R66 10K-0402
1
+3VRUN
Resistor Placement Within 2.0" of the CPU Within 2.0" of the CPU39 ohm +/- 5% Within 2.0" of the CPU Within 2.0" of the CPU Within 2.0" of the CPU
12
R318 150/F_4
DBR#
+VCCP +VCCP
12
12
R56
R316
39.2/F
54.9/F
PROJECT : ED2
Quanta Computer Inc.
Dothan (HOST)
7
R710
12
MBDATA
MBCLK
12
8
MBDATA 32,37
Item9
MBCLK 32,37
THRM# 13 MAX6657_AL# 32
MAX6657_OV# 27,34
R57 150/F_4
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538Friday, October 22, 2004
8
C2A
1
2
3
4
5
6
7
8
R50 *0_NC
R46 *0_NC
1 2
SELPSB2_CLK SELPSB1_CLK
+VCCP
BSEL0 BSEL1
U31C
W23
D10
VCCP0
D12
VCCP1
D14
VCCP2
D16
VCCP3
E11
VCCP4
E13
VCCP5
E15
VCCP6
F10
VCCP7
F12
VCCP8
F14
VCCP9
F16
VCCP10
K6
VCCP11
L5
VCCP12
L21
VCCP13
M6
VCCP14
M22
VCCP15
N5
VCCP16
N21
VCCP17
P6
VCCP18
P22
VCCP19
R5
VCCP20
R21
VCCP21
T6
VCCP22
T22
VCCP23
U21
VCCP24
P23
VCCQ0
W4
VCCQ1
E2
VID0
F2
VID1
F3
VID2
G3
VID3
G4
VID4
H4
VID5
AE7
VCCSENSE
AF6
VSSSENSE
C16
BSEL0
C14
BSEL1
E1
12
PSI
R6
VSS100
R22
VSS101
R25
VSS102
T3
VSS103
T5
VSS104
T21
VSS105
T23
VSS106
T26
VSS107
U2
VSS108
U6
VSS109
U22
VSS110
U24
VSS111
V1
VSS112
V4
VSS113
V5
VSS114
V21
VSS115
V25
VSS116
W3
VSS117
W6
VSS118
W22
VSS119
Dothan Processor
Size Document Number Rev
Date: Sheet
Dothan
3 OF 3
POWER, GROUND AND NC
VID
PROJECT : ED2
Quanta Computer Inc.
Dothan (Power)
7
VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191
W26 Y2 Y5 Y21 Y24 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24
638Friday, October 22, 2004
C2A
of
8
Place voltage
+VCCP
divider within
0.5" of GTLREF
COMP0 COMP1 COMP2 COMP3
A A
Place pulldown resistors within
0.5" of COMP pins
18mils Trace Width of COMP0,2 5mils Trace Width of COMP1,3
B B
C C
12
C37
10U_6.3V_8
12
C407
10U_6.3V_8
12
C419
10U_6.3V_8
C34
10U_6.3V_8
1 2
12
C59
10U_6.3V_8
12
C415
10U_6.3V_8
12
C63
10U_6.3V_8
C61
10U_6.3V_8
1 2
R27
27.4/F
1 2
VHCORE
12
C405
10U_6.3V_8
VHCORE
12
C406
10U_6.3V_8
12
C62
10U_6.3V_8
VHCORE
C423
10U_6.3V_8
1 2
1 2
R307
54.9/F
R19
27.4/F
1 2
12
C412
10U_6.3V_8
12
C404
10U_6.3V_8
12
C414
10U_6.3V_8
C424
10U_6.3V_8
1 2
R22
54.9/F
1 2
12
C418
10U_6.3V_8
12
C32
10U_6.3V_8
12
C411
10U_6.3V_8
C425
10U_6.3V_8
1 2
12
.01U/16V_4
12
C64
10U_6.3V_8
12
C36
10U_6.3V_8
C35
10U_6.3V_8
1 2
C71
12
C409
10U_6.3V_8
12
C421
10U_6.3V_8
C417
10U_6.3V_8
1 2
pin
R15 1K/F-0402
Trace as Wider as possible.
1 2
R16 2K/F
1 2
CPU_VCCA
12
C75
10U_6.3V_8
+1_5VRUN
VHCORE
12
C426
10U_6.3V_8
VHCORE
12
C60
10U_6.3V_8
VHCOREVHCORE
C410
10U_6.3V_8
1 2
T85 T92 T96
12
C420
10U_6.3V_8
12
C416
10U_6.3V_8
C33
10U_6.3V_8
1 2
R55 0_4
Removed +1_8VRUN
12
C408
10U_6.3V_8
12
C413
10U_6.3V_8
C422
10U_6.3V_8
1 2
T94 T89
T97 T95
T84 T83 T90
COMP0 COMP1 COMP2 COMP3
GTLREF0
TEST1 TEST2
CPU_VCCA
VHCORE
Total caps = 1670 uF > 1430 uF (Intel Recommendation) ESR = 9m ohm/4 // 5m ohm/35 ---> = 0.1343m ohm
+VCCP
12
12
12
C427
+
D D
150U/6.3V_7
CC7343
12
C51
C44
.1U/10V_4
.1U/10V_4
1
12
C73
C76
.1U/10V_4
.1U/10V_4
C, mF---------ESR, mW-----------ESL, nH 1 x 150 mF-----42 mW (typ) / 2--------2.5 nH / 12 10 x 0.1 mF----16 mW (typ) / 10-------0.6 nH / 10
2
12
C46
.1U/10V_4
+VCCP
12
C27 .1U/10V_4
12
C52 .1U/10V_4
12
C30 .1U/10V_4
3
12
C45 .1U/10V_4
12
C74 .1U/10V_4
VHCORE
4
P25 P26 AB2 AB1
AD26
AF7
AC1
E26
AC26
D18 D20 D22
E17 E19 E21
G21 H22
K22
V22
W21
Y22 AA5 AA7
AA9 AA11 AA13 AA15 AA17 AA19 AA21
AB6
AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22
AC9 AC11 AC13 AC15 AC17 AC19
AD8 AD10 AD12 AD14 AD16 AD18
AE9 AE11 AE13 AE15 AE17 AE19
AF8 AF10 AF12 AF14 AF16 AF18
C5
F23
B2 C3
N1 B1
F26
D6 D8
E5 E7 E9
F6
F8 F18 F20 F22
G5 H6
J5
J21
U5 V6
W5
Y6
U31B
COMP0 COMP1 COMP2 COMP3
GTLREF0
TEST1 TEST2
NC1 RSVD2
RSVD3 RSVD4 RSVD5
VCCA3 VCCA2 VCCA1 VCCA0
VCC00 VCC01 VCC02 VCC03 VCC04 VCC05 VCC06 VCC07 VCC08 VCC09 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71
Dothan Processor
Dothan
2 OF 3
POWER, GROUND, RESERVED SIGNALS
VSS00 VSS01 VSS02 VSS03 VSS04 VSS05 VSS06 VSS07 VSS08 VSS09 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99
5
A2 A5 A8 A11 A14 A17 A20 A23 A26 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 C24 D2 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4
DothanA DothanB
NC Install
R313
SELPSB2_CLK SELPSB1_CLK
R313 0_4 R314 0_4
PSI
No using for MAX1907
STP_CPU#13,17,33
SELPSB2_CLK8,17 SELPSB1_CLK8,17
CPU_VID033 CPU_VID133 CPU_VID233 CPU_VID333 CPU_VID433 CPU_VID533
1 2 1 2
6
T81 *PAD T82 *PAD
1
2
3
4
5
6
7
8
HXRCOMP
12
R107 100/F
R144 100/F
+VCCP
12
+VCCP
12
12
12
+VCCP
12
+VCCP
12
12
R98
24.9/F
R95
54.9/F
R102 221/F
R152
24.9/F
R133
54.9/F
R143 221/F
A A
B B
C C
HXSCOMP
HXSWING
C130
.1U/10V_4
1 2
HYRCOMP
HYSCOMP
HYSWING
C173
.1U/10V_4
1 2
10mil Trace Length and Width
20mil Trace Length and Width
10mil Trace Length and Width
20mil Trace Length and Width
HD#[0..63]5
HD#[0..63]
HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
U33A
E4
HD0#
E1
HD1#
F4
HD2#
H7
HD3#
E2
HD4#
F1
HD5#
E3
HD6#
D3
HD7#
K7
HD8#
F2
HD9#
J7
HD10#
J8
HD11#
H6
HD12#
F3
HD13#
K8
HD14#
H5
HD15#
H1
HD16#
H2
HD17#
K5
HD18#
K6
HD19#
J4
HD20#
G3
HD21#
H3
HD22#
J1
HD23#
L5
HD24#
K4
HD25#
J5
HD26#
P7
HD27#
L7
HD28#
J3
HD29#
P5
HD30#
L3
HD31#
U7
HD32#
V6
HD33#
R6
HD34#
R5
HD35#
P3
HD36#
T8
HD37#
R7
HD38#
R8
HD39#
U8
HD40#
R4
HD41#
T4
HD42#
T5
HD43#
R1
HD44#
T3
HD45#
V8
HD46#
U6
HD47#
W6
HD48#
U3
HD49#
V5
HD50#
W8
HD51#
W7
HD52#
U2
HD53#
U1
HD54#
Y5
HD55#
Y2
HD56#
V4
HD57#
Y7
HD58#
W1
HD59#
W3
HD60#
Y3
HD61#
Y6
HD62#
W2
HD63#
C1
HXRCOMP
C2
HXSCOMP
D1
HXSWING
T1
HYRCOMP
L1
HYSCOMP
P1
HYSWING
ALVISO
CT_0505: Change footprint to mbga1257-intel-alviso from MBGA-1257
HOST
HA3# HA4# HA5# HA6# HA7# HA8#
HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#
HADS# HADSTB0# HADSTB1#
HVREF
HBNR#
HBPRI#
BREQ0#
HCPURST#
HCLKINN HCLKINP
HDBSY#
HDEFER#
HDINV#0 HDINV#1 HDINV#2 HDINV#3 HDPWR#
HDRDY# HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3# HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3#
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0# HRS1# HRS2#
HCPUSLP#
HTRDY#
G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13
F8 B9 E13 J11 A5 D5 E7 H10
AB1 AB2
C6 E6 H8 K3 T7 U5 G6 F7 G4 K1 R3 V3 G5 K2 R2 W4 F6 D4 D6 B3 A11 A7 D7 B8 C7 A8 A4 C5 B4 G8 B5
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31
HCPUSLP#_GMCH
HA#[3..31]
HA#[3..31] 5
ADS# 5 HADSTB0# 5 HADSTB1# 5
BNR# 5 BPRI# 5 HBREQ0# 5 CPURST# 5
HCLK_MCH# 17 HCLK_MCH 17
DBSY# 5 DEFER# 5 HDBI0# 5 HDBI1# 5 HDBI2# 5 HDBI3# 5
DPWR# 5
DRDY# 5 HDSTBN0# 5 HDSTBN1# 5 HDSTBN2# 5 HDSTBN3# 5 HDSTBP0# 5 HDSTBP1# 5 HDSTBP2# 5 HDSTBP3# 5
HIT# 5 HITM# 5 HLOCK# 5
HREQ#0 5 HREQ#1 5 HREQ#2 5 HREQ#3 5 HREQ#4 5 RS#0 5 RS#1 5 RS#2 5
HTRDY# 5
Do not install R244 for Dothan-A and install for Dothan-B
T7 *PAD
T105 *PAD
CT_0513: Install R39 0 ohm.
R89
1 2
0_4
HVREF
12
C160 .1U/10V_4
Concern about HVREF Trace Length & Width
CPUSLP# 5,12
+VCCP
1 2
12
R129 100/F
R128 200/F
close to Alviso 100mil
D D
Size Document Number Rev
Alviso (HOST)
1
2
3
4
5
6
Date: Sheet
PROJECT : ED2
Quanta Computer Inc.
7
C2A
of
738Friday, October 22, 2004
8
1
DMI_TXN013 DMI_TXN113 DMI_TXN213
12
R169
40.2/F
DMI_TXN313
DMI_TXP013 DMI_TXP113 DMI_TXP213 DMI_TXP313
DMI_RXN013 DMI_RXN113 DMI_RXN213 DMI_RXN313
DMI_RXP013 DMI_RXP113 DMI_RXP213 DMI_RXP313
CLK_SDRAM015 CLK_SDRAM115
T42
CLK_SDRAM315 CLK_SDRAM415
T34
CLK_SDRAM0#15 CLK_SDRAM1#15
T40
CLK_SDRAM3#15 CLK_SDRAM4#15
CKE015,16 CKE115,16 CKE215,16 CKE315,16
SM_CS0#15,16 SM_CS1#15,16 SM_CS2#15,16 SM_CS3#15,16
T36
CLK_SDRAM2
CLK_SDRAM5
CLK_SDRAM2#
CLK_SDRAM5#
CKE0 CKE1 CKE2 CKE3
SM_CS0# SM_CS1# SM_CS2# SM_CS3#
M_OCDCOMP0 M_OCDCOMP1
T116 T44 T43 T45
M_RCOMPN M_RCOMPP
SMDDR_VREF_R
SMXSLEW SMYSLEW
A A
B B
12
R173
40.2/F
C C
Route as short as possible.
2
U33C
AA31
DMIRXN0
AB35
DMIRXN1
AC31
DMIRXN2
AD35
DMIRXN3
Y31
DMIRXP0
AA35
DMIRXP1
AB31
DMIRXP2
AC35
DMIRXP3
AA33
DMITXN0
AB37
DMITXN1
AC33
DMITXN2
AD37
DMITXN3
Y33 AA37 AB33 AC37
AM33
AL1 AE11
AJ34
AF6 AC10
AN33
AK1 AE10
AJ33
AF5 AD10
AP21 AM21 AH21 AK21
AN16 AM14 AH15 AG16
AF22 AF16
AP14
AL15 AM11 AN10
AK10 AK11 AF37
AD1 AE27 AE28
AF9 AF10
DMITXP0 DMITXP1 DMITXP2 DMITXP3
SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK4 SM_CK5
SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CK4# SM_CK5#
SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3
SM_CS0# SM_CS1# SM_CS2# SM_CS3#
SM_OCDCOMP0 SM_OCDCOMP1
SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3
SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT
ALVISO
DMIDDR MUXING
It's point to point, 55ohm trace, keep as
CFG/RSVDPMLCKNC
BM_BUSY#
EXT_TS0# EXT_TS1#
THRMTRIP#
DREF_CLKN
DREF_CLKP DREF_SSCLKN DREF_SSCLKP
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8
CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27
PWROK
RSTIN#
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8
NC9 NC10 NC11
3
+VCCP
12
R126 10K-0402
CFG0
G16
SELPSB1_CLK
H13
SELPSB2_CLK
G14
CFG3
F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25
J23 J21 H22 F5 AD30 AE29
A24 A23 C37 D37
AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37
CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
PM_EXTTS#0 PM_EXTTS#1
PLTRST#_R DOT96#
DOT96 DREFSSCLK# DREFSSCLK
TP_NC1 TP_NC2 TP_NC3 TP_NC4 TP_NC5 TP_NC6 TP_NC7 TP_NC8 TP_NC9 TP_NC10 TP_NC11SMDDR_VREF_R1
T18 T20 T26 T12 T13 T31 T5 T19 T2 T17 T25 T3 T33 T32 T29 T21 T22 T14
1 2
R168 100/F
4
CFG6
Low=DDR2 High=DDR1
SELPSB1_CLK 6,17 SELPSB2_CLK 6,17
Reserved for AV
PM_BMBUSY# 13
THERMTRIP# 5,12 IMVP_PWRGD 13,33 PLTRST# 12,13,20,31,32
DOT96# 17 DOT96 17 DREFSSCLK# 17 DREFSSCLK 17
T113
*PAD
T111
*PAD
T117
*PAD
T115
*PAD
T114
*PAD
T112
*PAD
T109
*PAD
T107
*PAD
T110
*PAD
T106
*PAD
T108
*PAD
12
R106 *2.21K/F_NC
INT_DDCCLK19 INT_DDCDAT19
INT_VGA_BLU31 INT_VGA_GRN31 INT_VGA_RED31
INT_VSYNC19
INT_HSYNC19
Low=DMIx2 High=DMIx4
CLK_MCH_3GPLL#17 CLK_MCH_3GPLL17
TV_Y/G24 TV_C/R24
4.99K/F R110
R122 255/F_4
INT_DISP_ON18
INT_TXLCLKOUT-18 INT_TXLCLKOUT+18
INT_TXLOUT0-18 INT_TXLOUT1-18 INT_TXLOUT2-18
INT_TXLOUT0+18 INT_TXLOUT1+18 INT_TXLOUT2+18
CFG5
INT_BLON18
I_EDIDCLK18 I_EDIDDATA18
5
12
R109 *2.21K/F_NC
T27 T28
T104
12
R99 150/F_4
1 2
R103 150/F_4
1 2
R96 150/F_4
1 2
R94 150/F_4
R81 39 R80 39
REFSET
INT_BLON INT_DISP_ON
R97 1. 5K/F T1
T23 T24
T6 T16 T30
T11 T15 T4
INT_TV_COMP INT_TV_Y/G INT_TV_C/R TV_REFSET
12
R93 150/F_4
INT_VGA_BLU INT_VGA_GRN INT_VGA_RED
12 12
INT_TXLCLKOUT­INT_TXLCLKOUT+
INT_TXLOUT0­INT_TXLOUT1­INT_TXLOUT2-
INT_TXLOUT0+ INT_TXLOUT1+ INT_TXLOUT2+
6
SDVOCTRL_DATA default is no SDOV
T10 T8
T9
AB29 AC29
H24 H25
A15 C16 A17
B15 B16 B17
E24 E23 E21 D21 C20 B20 A19 B19 H21 G21
E25 F25 C23 C22 F23 F22 F26 C33 C31 F28 F27
B30 B29 C25 C24
B34 B33 B32
A34 A33 B31
C29 D28 C27
C28 D27 C26
J18
J20
U33F
SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP
TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC
DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET
LBKLT_CTRL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL
LACLKN LACLKP LBCLKN LBCLKP
LADATAN0 LADATAN1 LADATAN2
LADATAP0 LADATAP1 LADATAP2
LBDATAN0 LBDATAN1 LBDATAN2
LBDATAP0 LBDATAP1 LBDATAP2
ALVISO
MISC
TV VGA LVDS
7
EXP_COMPI
EXP_ICOMPO
EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8
EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
PCI-EXPRESS GRAPHICS
EXP_TXN8
EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15
EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8
EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15
VCC3G_PCIE_R
D36 D34
E30 F34 G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34
D30 E34 F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34
E32 F36 G32 H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36
D32 E36 F32 G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36
8
VCC3G_PCIE
R104
1 2
24.9/F
short as possible. close Alviso.
+2_5VSUS
12
R189
80.6/F
M_RCOMPN M_RCOMPP
12
D D
R183
80.6/F
1
SMDDR_VREF_R
SMDDR_VREF_R1
2
1 2
R181 10K/F
1 2
C222 .1U/16V_6
1 2
R335 10K/F
1 2
C434 .1U/16V_6
1 2
R176 10K/F
1 2
C212 .1U/16V_6
1 2
R331 10K/F
1 2
C432 .1U/16V_6
3
+2_5VSUS
+2_5VRUN+2_5VSUS
R83 10K-0402
1 2
R82 10K-0402
1 2
PM_EXTTS#0
PM_EXTTS#1
System memory throttling using
Size Document Number Rev
Alviso (VGA, DMI)
4
5
6
Date: Sheet
PROJECT : ED2
Quanta Computer Inc.
7
C2A
of
838Friday, October 22, 2004
8
1
2
3
4
5
6
7
8
MD[0..63] SM_DQS[0..7] SDM[0..7]
RN73
A A
4P2R-S-10 RN89
4P2R-S-10
RN74 4P2R-S-10 RN90 4P2R-S-10
RN75 4P2R-S-10 RN91 4P2R-S-10
RN92 4P2R-S-10
RN76 4P2R-S-10
RN71 4P2R-S-10 RN87 4P2R-S-10
B B
RN88 4P2R-S-10
RN72 4P2R-S-10
RN65 4P2R-S-10
RN81 4P2R-S-10
RN66 4P2R-S-10
RN82 4P2R-S-10
RN67 4P2R-S-10 RN83 4P2R-S-10
RN68 4P2R-S-10
RN84 4P2R-S-10
C C
RN69 4P2R-S-10 RN85 4P2R-S-10
RN86 4P2R-S-10
RN70 4P2R-S-10
RN77 4P2R-S-10 RN93 4P2R-S-10
RN78 4P2R-S-10 RN94 4P2R-S-10
RN95 4P2R-S-10
RN79 4P2R-S-10
D D
RN80 4P2R-S-10 RN96 4P2R-S-10
MD31 R_MD31 MD26 R_MD26 MD30 MD27
MD25 R_MD25 MD24 R_MD24 MD28 R_MD28 MD29 R_MD29
MD18 R_MD18 MD22 R_MD22 MD23
MD21 MD20 MD16 MD17
MD35 R_MD35 MD34 R_MD34 MD39 R_MD39 MD38 R_MD38
MD36 MD37 MD33 MD32
MD59 MD58 MD62 MD63
MD56 MD60 MD61 MD57
MD51 R_MD51 MD50 R_MD50 MD55 R_MD55 MD54 R_MD54
MD48 MD49
MD52
MD47 R_MD47 MD46 R_MD46 MD42 R_MD42 MD43 R_MD43
MD44 MD45 MD40 MD41
MD14 R_MD14
MD13 MD9
MD12 R_MD12
MD6 MD3 MD2 MD7
MD5 R_MD5
1
2
1
4
3 3 1
1 3 1 3
1 3 1 3
3 1 3 1
1 3 1 3
3 1 1 3
3 1 3 1
3 1 1 3
1 3 1 3
3 1 3 1
1 3 1 3
3 1 3 1
1 3 1 3
1 3 1 3
3 1 1 3
1 3 1 3
R_MD30
4
R_MD27
2
2 4 2 4
R_MD19MD19
2 4 2
R_MD23
4
R_MD21
4
R_MD20
2
R_MD16
4
R_MD17
2
2 4 2 4
R_MD36
4
R_MD37
2
R_MD33
2
R_MD32
4
R_MD59
4
R_MD58
2
R_MD62
4
R_MD63
2
R_MD56
4
R_MD60
2
R_MD61
2
R_MD57
4
2 4 2 4
R_MD48
4
R_MD53MD53
2
R_MD49
4
R_MD52
2
2 4 2 4
R_MD44
4
R_MD45
2
R_MD40
4
R_MD41
2
R_MD10MD10
2
R_MD11MD11
4
R_MD15MD15
2 4
R_MD13
2
R_MD8MD8
4
R_MD9
2 4
R_MD6
4
R_MD3
2
R_MD2
2
R_MD7
4
R_MD1MD1
2
R_MD0MD0
4
R_MD4MD4
2 4
2
R_MD0 R_MD1 R_MD2 R_MD3 R_MD4 R_MD5 R_MD6 R_MD7 R_MD8 R_MD9 R_MD10 R_MD11 R_MD12 R_MD13 R_MD14 R_MD15 R_MD16 R_MD17 R_MD18 R_MD19 R_MD20 R_MD21 R_MD22 R_MD23 R_MD24 R_MD25 R_MD26 R_MD27 R_MD28 R_MD29 R_MD30 R_MD31 R_MD32 R_MD33 R_MD34 R_MD35 R_MD36 R_MD37 R_MD38 R_MD39 R_MD40 R_MD41 R_MD42 R_MD43 R_MD44 R_MD45 R_MD46 R_MD47 R_MD48 R_MD49 R_MD50 R_MD51 R_MD52 R_MD53 R_MD54 R_MD55 R_MD56 R_MD57 R_MD58 R_MD59 R_MD60 R_MD61 R_MD62 R_MD63
R_SDM0
1 2
R356 10_4
R_SDM1
1 2
R355 10_4
1 2
R354 10_4
1 2
R353 10_4
1 2
R352 10_4
1 2
R351 10_4
R_SDM6 R_SM_DQS6
1 2
R350 10_4
R_SDM7
1 2
R349 10_4
U33B
AG35
SADQ0
AH35
SADQ1
AL35
SADQ2
AL37
SADQ3
AH36
SADQ4
AJ35
SADQ5
AK37
SADQ6
AL34
SADQ7
AM36
SADQ8
AN35
SADQ9
AP32
SADQ10
AM31
SADQ11
AM34
SADQ12
AM35
SADQ13
AL32
SADQ14
AM32
SADQ15
AN31
SADQ16
AP31
SADQ17
AN28
SADQ18
AP28
SADQ19
AL30
SADQ20
AM30
SADQ21
AM28
SADQ22
AL28
SADQ23
AP27
SADQ24
AM27
SADQ25
AM23
SADQ26
AM22
SADQ27
AL23
SADQ28
AM24
SADQ29
AN22
SADQ30
AP22
SADQ31
AM9
SADQ32
AL9
SADQ33
AL6
SADQ34
AP7
SADQ35
AP11
SADQ36
AP10
SADQ37
AL7
SADQ38
AM7
SADQ39
AN5
SADQ40
AN6
SADQ41
AN3
SADQ42
AP3
SADQ43
AP6
SADQ44
AM6
SADQ45
AL4
SADQ46
AM3
SADQ47
AK2
SADQ48
AK3
SADQ49
AG2
SADQ50
AG1
SADQ51
AL3
SADQ52
AM2
SADQ53
AH3
SADQ54
AG3
SADQ55
AF3
SADQ56
AE3
SADQ57
AD6
SADQ58
AC4
SADQ59
AF2
SADQ60
AF1
SADQ61
AD4
SADQ62
AD5
SADQ63
ALVISO
SDM0 SM_DQS0 SDM1 SM_DQS1
SDM6 SM_DQS6 SDM7 R_SM_DQS7
3
MD[0..63] 15,16 SM_DQS[0..7] 15,16 SDM[0..7] 15,16
SA_BS0# SA_BS1# SA_BS2#
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7
SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8
SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13
DDR SYSTEM MEMORY A
SA_CAS# SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
R_SM_DQS0 R_SM_DQS1 R_SM_DQS2R_SDM2
R_SM_DQS3R_SDM3 R_SM_DQS4R_SDM4 R_SM_DQS5R_SDM5 SDM5
M_A_BA0
AK15
M_A_BA1
AK16 AL21
R_SDM0
AJ37
R_SDM1
AP35
R_SDM2
AL29
R_SDM3
AP24
R_SDM4
AP9
R_SDM5
AP4
R_SDM6
AJ2
R_SDM7
AD3
R_SM_DQS0
AK36
R_SM_DQS1
AP33
R_SM_DQS2
AN29
R_SM_DQS3
AP23
R_SM_DQS4
AM8
R_SM_DQS5
AM4
R_SM_DQS6
AJ1
R_SM_DQS7
AE5 AK35
AP34 AN30 AN23 AN8 AM5 AH1 AE4
M_A_MA0
AL17
M_A_MA1
AP17
M_A_MA2
AP18
M_A_MA3
AM17
M_A_MA4
AN18
M_A_MA5
AM18
M_A_MA6
AL19
M_A_MA7
AP20
M_A_MA8
AM19
M_A_MA9
AL20
M_A_MA10
AM16
M_A_MA11
AN20
M_A_MA12
AM20
M_A_MA13
AM15
M_A_SCASA#
AN15
M_A_SRASA#
AP16
SA_RCVENIN#
AF29
SA_RCVENOUT#
AF28
M_A_BMWEA#
AP15
1 2
R347 10_4
1 2
R346 10_4
1 2
R345 10_4
1 2
R344 10_4
1 2
R343 10_4
1 2
R342 10_4
1 2
R341 10_4
1 2
R340 10_4
4
SM_DQS2SDM2 SM_DQS3SDM3 SM_DQS4SDM4 SM_DQS5
SM_DQS7
M_A_BA0 15,16 M_A_BA1 15,16
M_A_MA[0..13] 15,16
M_A_SCASA# 15,16 M_A_SRASA# 15,16
T41 T38
M_A_BMWEA# 15,16
U33G
AE31
SBDQ0
AE32
SBDQ1
AG32
SBDQ2
AG36
SBDQ3
AE34
SBDQ4
AE33
SBDQ5
AF31
SBDQ6
AF30
SBDQ7
AH33
SBDQ8
AH32
SBDQ9
AK31
SBDQ10
AG30
SBDQ11
AG34
SBDQ12
AG33
SBDQ13
AH31
SBDQ14
AJ31
SBDQ15
AK30
SBDQ16
AJ30
SBDQ17
AH29
SBDQ18
AH28
SBDQ19
AK29
SBDQ20
AH30
SBDQ21
AH27
SBDQ22
AG28
SBDQ23
AF24
SBDQ24
AG23
SBDQ25
AJ22
SBDQ26
AK22
SBDQ27
AH24
SBDQ28
AH23
SBDQ29
AG22
SBDQ30
AJ21
SBDQ31
AG10
SBDQ32
AG9
SBDQ33
AG8
SBDQ34
AH8
SBDQ35
AH11
SBDQ36
AH10
SBDQ37
AJ9
SBDQ38
AK9
SBDQ39
AJ7
SBDQ40
AK6
SBDQ41
AJ4
SBDQ42
AH5
SBDQ43
AK8
SBDQ44
AJ8
SBDQ45
AJ5
SBDQ46
AK4
SBDQ47
AG5
SBDQ48
AG4
SBDQ49
AD8
SBDQ50
AD9
SBDQ51
AH4
SBDQ52
AG6
SBDQ53
AE8
SBDQ54
AD7
SBDQ55
AC5
SBDQ56
AB8
SBDQ57
AB6
SBDQ58
AA8
SBDQ59
AC8
SBDQ60
AC7
SBDQ61
AA4
SBDQ62
AA5
SBDQ63
ALVISO
5
6
SB_BS0# SB_BS1# SB_BS2#
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7
SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8
SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13
DDR SYSTEM MEMORY B
SB_CAS# SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
Size Document Number Rev
Alviso (DDR)
Date: Sheet of
7
M_B_BA0
AJ15 AG17 AG21
AF32 AK34 AK27 AK24 AJ10 AK5 AE7 AB7
AF34 AK32 AJ28 AK23 AM10 AH6 AF8 AB4
AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5
AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15
AH14 AK14 AF15 AF14 AH16
M_B_BA1
M_B_MA0 M_B_MA1 M_B_MA2 M_B_MA3 M_B_MA4 M_B_MA5 M_B_MA6 M_B_MA7 M_B_MA8 M_B_MA9 M_B_MA10 M_B_MA11 M_B_MA12 M_B_MA13
M_B_SCASA# M_B_SRASA# SB_RCVENIN# SB_RCVENOUT# M_B_BMWEA#
M_B_BA0 15,16 M_B_BA1 15,16
M_B_MA[0..13] 15,16
M_B_SCASA# 15,16 M_B_SRASA# 15,16
T39 T37
M_B_BMWEA# 15,16
PROJECT : ED2
Quanta Computer Inc.
938Friday, October 22, 2004
8
C2A
5
+VCCP
12
12
C162
C185
.1U/10V_4
.1U/10V_4
D D
+1_5VRUN
L23
12
BLM11A121S
C C
B B
L22 BLM11A121S
L44 BLM11A121S
L45 BLM11A121S
12
C125 .1U/10V_4
12
12
C123 .1U/10V_4
12
12
C195 .1U/10V_4
12
12
C196 .1U/10V_4
12
C189 .1U/10V_4
12
+
12
+
12
+
12
+
12
VCCA_DPLLA
C110 470U_2.5V
VCCA_DPLLB
C101 470U_2.5V
VCCA_HPLL
C204 470U_2.5V
VCCA_MPLL
C190 470U_2.5V
C186 10U_6.3V_8
12
C169 10U_6.3V_8
12
1.5A
R84
1 2
12
C91
3
.022U/16V_4
C114 .47U/10V_6
1 2
C120 .47U/10V_6
1 2
C431 .22U/6.3V_6
1 2
C153 .22U/6.3V_6
1 2
+2_5VRUN
+VCCP
+2_5VRUN
A A
D15
2 1
RB751V
+VCCP
12
C163
2.2U/6.3V
R77
10_4
5
L17
12
12
C182
4.7U/10V_8
BLM18PG181SN1
12
12
C126 .1U/10V_4
VCCA_CRTDAC
12
C90 .1U/10V_4
4
C164 10U_6.3V_8
VCCA_CRTDAC_R
0_4
1
C102
2
*22nF_3P_NC
+VCCP
VCCP_GMCH_CAP1
VCCP_GMCH_CAP2 VCCP_GMCH_CAP3
VCCP_GMCH_CAP4
4
T29 R29 N29
M29
K29 J29 V28
U28
T28
R28
P28 N28 M28
L28
K28
J28 H28 G28
V27 U27
T27 R27
P27 N27 M27
L27
K27
J27 H27
K26 H26
K25
J25
K24
K23
K22
K21 W20 U20
T20
K20
V19 U19
K19 W18
V18
T18
K18
K17 AC2
AC1
B23 C35 AA1 AA2
F19
E19 G19
H20
K13
J13
K12 W11
V11 U11
T11 R11
P11 N11 M11
L11
K11 W10
V10 U10
T10 R10
P10 N10 M10
K10
J10
Y9 W9 U9 R9
P9 N9 M9
L9
J9 N8 M8 N7 M7 N6 M6
A6 N5 M5 N4 M4 N3 M3 N2 M2
B2
V1 N1 M1 G1
VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48
VCCH_MPLL1 VCCH_MPLL0 VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL
VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC
VCC_SYNC VTT0
VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51
U33H ALVISO
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2
POWER
VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2
VCCA_3GPLL0 VCCA_3GPLL1 VCCA_3GPLL2
VCCA_TVBG VSSA_TVBG
VCCA_LVDS
VCCHV0 VCCHV1 VCCHV2
VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8
VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51 VCCSM52 VCCSM53 VCCSM54 VCCSM55 VCCSM56 VCCSM57 VCCSM58 VCCSM59 VCCSM60 VCCSM61 VCCSM62 VCCSM63 VCCSM64
VCCA_SM0 VCCA_SM1 VCCA_SM2 VCCA_SM3
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GBG VSSA_3GBG
3
3
F17 E17 D18 C18 F18 E18
H18 G18
D19 H17
B26 B25 A25
A35 B22
B21 A21
AM37 AH37 AP29 AD28 AD27 AC27 AP26 AN26 AM26 AL26 AK26 AJ26 AH26 AG26 AF26 AE26 AP25 AN25 AM25 AL25 AK25 AJ25 AH25 AG25 AF25 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AE17 AE16 AE15 AE14 AP13 AN13 AM13 AL13 AK13 AJ13 AH13 AG13 AF13 AE13 AP12 AN12 AM12 AL12 AK12 AJ12 AH12 AG12 AF12 AE12 AD11 AC11 AB11 AB10 AB9 AP8 AM1 AE1
B28 A28 A27
AF20 AP19 AF19 AF18
AE37 W37 U37 R37 N37 L37 J37
Y29 Y28 Y27
F37 G37
VCC_TVDACA_R VCC_TVDACB_R VCC_TVDACC_R
VCC_TVBG_R VSS_TVBG
VCCQ_TVDAC_R
V1.8_DDR_CAP6 V1.8_DDR_CAP3 V1.8_DDR_CAP4
VCC_DDRDLL
VCC3G_PCIE
VCCA_3GPLL
VCCA_3GBG VSSA_3GBG
12
C202 .1U/10V_4
12
C154
.01U/16V_4
12
C121 .1U/10V_4
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
Note: All VCCSM pins shorted internally.
Note: All VCCSM pins shorted internally.
C228 .1U/10V_4
1 2
C226 .1U/10V_4
1 2
C208 .1U/10V_4
1 2
12
C203 10U_6.3V_8
12
C122 .1U/10V_4
12
C112 10U_6.3V_8
C227 .1U/10V_4
1 2
C223 .1U/10V_4
1 2
C229 .1U/10V_4
1 2
+2_5VSUS
12
C201 10U_6.3V_8
12
C146 .1U/10V_4
+1_5VRUN
+2_5VRUN
+2_5VRUN
12
C230 10U_6.3V_8
12
C117
4.7U/10V_8
+2_5VRUN
2
VCC_TVDACB_RVCCD_TVDAC_R
VCC_TVDACC_R
VCC_TVBG_R
VSS_TVBG
VCCD_TVDAC_R
*22nF_3P_NC
VCCQ_TVDAC_R
*22nF_3P_NC
2
1
12
C106 .1U/10V_4
12
C118 .1U/10V_4
12
C109 .1U/10V_4
12
C96 .1U/10V_4
12
12
+
C165 220U_4V_L
L20 BLM18PG181SN1
L16 BLM18PG181SN1
L15 BLM18PG181SN1
L19 BLM18PG181SN1
L32 BLM18PG181SN1
L25 BLM18PG181SN1
+2_5VRUN
1
R90 0_4
1 2
1
3
C115
2
*22nF_3P_NC
R92 0_4
1 2
1
3
C116
2
*22nF_3P_NC
R91 0_4
1 2
1
3
C113
2
*22nF_3P_NC
R86 0_4
1 2
1
3
C105
2
*22nF_3P_NC
R79 0_4
1 2
3
C103
R85 0_4
1 2
3
C104
VCCA_3GPLL
12
1
.022U/16V_4
2
12
1
.022U/16V_4
2
VCC_DDRDLL
VCC3G_PCIE
12
C191 .1U/10V_4
VCCA_3GBG
VSSA_3GBG
Size Document Number Rev
Alviso (Power)
Date: Sheet
VCC_TVDACAVCC_TVDACA_R
12
C107
.022U/16V_4
VCC_TVDACB
12
C119
.022U/16V_4
VCC_TVDACC
12
C108
.022U/16V_4
VCC_TVBG
12
C97
.022U/16V_4
VCCD_TVDAC
12
C95
C94 .1U/10V_4
12
C93 .1U/10V_4
C231 100U/10V
C187 10U_6.3V_8
R165
0.5/F C205 10U_6.3V_8
C124 .1U/10V_4
L18 BLM18PG181SN1
12
C209 .1U/10V_4
VCC3G_PCIE
12
C148 10U_6.3V_8
VCCA_3GPLL_R
VCCQ_TVDAC
C92
12
+
12
1 2
12
12
PROJECT : ED2
Quanta Computer Inc.
12
12
12
12
R76 10_4
12
D14 RB751V
2 1
12
12
L28
12
BLM18PG181SN1
10 38Friday, October 22, 2004
+3VRUN
+3VRUN
+3VRUN
+3VRUN
+3VRUN
+1_5VRUN
+1_5VRUN
+1_5VRUN
+1_5VRUN
C2A
of
5
4
3
2
1
B36
D D
VSSALVDS
C C
D2
Y1
VSS271
VSS135
B24
D24
J2
G2
VSS269
VSS270
VSS133
VSS134
J24
F24
AN24
AL24
VSS267
VSS268
VSS131
VSS132
AJ24
AG24
VSS266
VSS130
E26
A26
VSS265
VSS129
E27
G27
J26
G26
VSS262
VSS263
VSS264
VSS126
VSS127
VSS128
W27
AA27
Y12
VSS_NCTF68
P2
L2
B27
VSS259
VSS260
VSS261
VSS123
VSS124
VSS125
AF27
AB27
AG27
AA13
Y13
AA12
VSS_NCTF65
VSS_NCTF66
VSS_NCTF67
AE2
AD2
V2
T2
VSS255
VSS256
VSS257
VSS258
VSS119
VSS120
VSS121
VSS122
E28
AJ27
AL27
AN27
P14
N14
M14
L14
VSS_NCTF61
VSS_NCTF62
VSS_NCTF63
VSS_NCTF64
AN2
AL2
AH2
VSS253
VSS254
VSS117
VSS118
W28
AB28
AA28
U14
T14
R14
VSS_NCTF59
VSS_NCTF60
AB3
AA3
C3
A3
VSS248
VSS249
VSS250
VSS251
VSS252
VSS112
VSS113
VSS114
VSS115
VSS116
E29
A29
D29
AC28
AA14
Y14
W14
V14
VSS_NCTF54
VSS_NCTF55
VSS_NCTF56
VSS_NCTF57
VSS_NCTF58
AJ3
AC3
VSS246
VSS247
VSS110
VSS111
F29
G29
L15
AB14
VSS_NCTF52
VSS_NCTF53
P4
L4
H4
C4
VSS242
VSS243
VSS244
VSS245
VSS106
VSS107
VSS108
VSS109
L29
P29
U29
H29
R15
P15
N15
M15
VSS_NCTF48
VSS_NCTF49
VSS_NCTF50
VSS_NCTF51
AF4
Y4
U4
VSS239
VSS240
VSS241
VSS103
VSS104
VSS105
V29
W29
AA29
V15
U15
T15
VSS_NCTF45
VSS_NCTF46
VSS_NCTF47
AL5
W5
E5
AN4
VSS235
VSS236
VSS237
VSS238
VSS99
VSS100
VSS101
VSS102
AJ29
AD29
AG29
AM29
AB15
AA15
Y15
W15
VSS_NCTF41
VSS_NCTF42
VSS_NCTF43
VSS_NCTF44
J6
B6
AP5
VSS232
VSS233
VSS234
VSS96
VSS97
VSS98
Y30
C30
AA30
N16
M16
L16
VSS_NCTF38
VSS_NCTF39
VSS_NCTF40
AA6
T6
L6
VSS228
VSS229
VSS230P6VSS231
VSS92
VSS93
VSS94
VSS95
AP30
AE30
AB30
AC30
U16
T16
R16
P16
VSS_NCTF34
VSS_NCTF35
VSS_NCTF36
VSS_NCTF37
AJ6
AE6
AC6
VSS225
VSS226
VSS227
VSS89
VSS90
VSS91
F31
E31
D31
Y16
W16
V16
VSS_NCTF31
VSS_NCTF32
VSS_NCTF33
AG7
AA7
V7
G7
VSS221
VSS222
VSS223
VSS224
VSS85
VSS86
VSS87
VSS88
J31
K31
H31
G31
Y17
R17
AB16
AA16
VSS_NCTF27
VSS_NCTF28
VSS_NCTF29
VSS_NCTF30
C8
AN7
AK7
VSS218
VSS219
VSS220
VSS82
VSS83
VSS84
L31
N31
M31
AA18
AB17
AA17
VSS_NCTF24
VSS_NCTF25
VSS_NCTF26
Y8
P8
L8
E8
VSS214
VSS215
VSS216
VSS217
U33E ALVISO
VSS78
VSS79
VSS80
VSS81
T31
P31
U31
R31
AA20
AB19
AA19
AB18
VSS_NCTF20
VSS_NCTF21
VSS_NCTF22
VSS_NCTF23
H9
A9
AL8
VSS211
VSS212
VSS213
VSS75
VSS76
VSS77
V31
W31
AD31
Y21
R21
AB20
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
AA9
V9
T9
K9
VSS207
VSS208
VSS209
VSS210
VSS
VSS71
VSS72
VSS73
VSS74
A32
C32
AL31
AG31
AA22
Y22
AB21
AA21
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
AH9
AE9
AC9
VSS205
VSS206
VSS69
VSS70
Y32
AB32
AA32
AA23
Y23
AB22
VSS_NCTF11
VSS_NCTF12
Y10
L10
D10
AN9
VSS200
VSS201
VSS202
VSS203
VSS204
VSS64
VSS65
VSS66
VSS67
VSS68
AJ32
AN32
AD32
AC32
AB24
AA24
Y24
AB23
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
F11
AA10
VSS198
VSS199
VSS62
VSS63
E33
D33
AA25
Y25
VSS_NCTF4
VSS_NCTF5
AF11
AA11
Y11
H11
VSS195
VSS196
VSS197
VSS59
VSS60
VSS61
J33
F33
H33
G33
AB26
AA26
Y26
AB25
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
AL11
AJ11
AG11
VSS191
VSS192
VSS193
VSS194
VSS55
VSS56
VSS57
VSS58
L33
K33
M33
VSS_NCTF0
B12
AN11
VSS190
VSS54
P33
N33
VSS189
VSS53
B14
A14
J12
D12
VSS185
VSS186
VSS187
VSS188
VSS49
VSS50
VSS51
VSS52
T33
V33
U33
R33
P12
N12
M12
L12
VTT_NCTF14
VTT_NCTF15
VTT_NCTF16
VTT_NCTF17
F14
W33
R12
AJ14
AG14
K14
J14
VSS181
VSS182
VSS183
VSS184
VSS45
VSS46
VSS47
VSS48
C34
AL33
AF33
AD33
W12
V12
U12
T12
VTT_NCTF10
VTT_NCTF11
VTT_NCTF12
VTT_NCTF13
AN14
AL14
VSS178
VSS179
VSS180
VSS42
VSS43
VSS44
AB34
AA34
M13
L13
VTT_NCTF7
VTT_NCTF8
VTT_NCTF9
D16
A16
K15
C15
VSS175
VSS176
VSS177
VSS39
VSS40
VSS41
AN34
AH34
AD34
AC34
T13
R13
P13
N13
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
AL16
K16
H16
VSS171
VSS172
VSS173
VSS174
VSS35
VSS36
VSS37
VSS38
E35
B35
D35
+VCCP
W13
V13
U13
VTT_NCTF0
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
G17
C17
VSS170
VSS34
F35
G35
AJ17
AF17
VSS168
VSS169
VSS32
VSS33
J35
H35
A18
AN17
VSS166
VSS167
VSS30
VSS31
L35
K35
B18
VSS164
VSS165
VSS28
VSS29
M35
AL18
U18
VSS163
VSS27
P35
N35
H19
C19
VSS161
VSS162
VSS25
VSS26
T35
R35
T19
J19
VSS159
VSS160
VSS23
VSS24
V35
U35
W19
VSS157
VSS158
VSS21
VSS22
W35
AN19
AG19
VSS156
VSS20
Y35
AE35
D20
A20
VSS154
VSS155
VSS18
VSS19
C36
AA36
E20
VSS152
VSS153
VSS16
VSS17
AB36
G20
F20
VSS151
VSS15
AD36
AC36
VSS150
VSS14
AK20
V20
VSS149
VSS13
AF36
AE36
C21
VSS147
VSS148
VSS11
VSS12
AJ36
AF21
F21
VSS145
VSS146
VSS9
VSS10
AL36
AN36
A22
AN21
VSS144
VSS8
E37
H37
VSS143
VSS7
E22
D22
VSS142
VSS6
K37
M37
J22
VSS140
VSS141
VSS4
VSS5
P37
AL22
AH22
VSS138
VSS139
VSS2
VSS3
T37
V37
AF23
H23
VSS137
VSS1
Y37
AG37
VSS136
VSS0
U33D
NCTF
W21
ALVISO
VCCSM_NCTF0
VCCSM_NCTF1
VCCSM_NCTF2
VCCSM_NCTF3
VCCSM_NCTF4
VCCSM_NCTF5
VCCSM_NCTF6
VCCSM_NCTF7
VCCSM_NCTF8
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
VCCSM_NCTF27
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
L22
N22
M22
L23
T22
V22
P22
R22
N23
U22
M23
W22
L24
T23
V23
P23
R23
N24
U23
M24
W23
L25
T24
V24
P24
R24
N25
U24
M25
W24
L26
W25
T26
V26
P26
U26
R26
N26
M26
W26
+VCCP
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AD25
AC25
+2_5VSUS
AC26
AD26
T25
V25
P25
U25
R25
B B
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
L21
L20
L19
L17
M17
L18
T17
V17
P17
U17
N17
W17
Y18
P18
N19
R18
N18
M19
M18
P20
Y19
P19
N20
R19
M20
T21
V21
P21
Y20
U21
N21
R20
M21
DDRI is 2.5V, DDRII is 1.8V.
A A
Size Document Number Rev
Alviso (VSS, NCTF0
5
4
3
2
Date: Sheet
PROJECT : ED2
Quanta Computer Inc.
11 38Friday, October 22, 2004
1
C2A
of
1
VCCRTC
R221
1 2
182K/F
R211
1M
A A
12
C253 .1U/10V_4
12
Item2
RTC
D20
R_3VRTC
1 3
+3VSUS
2 1
2 1
Q34 PMBS3904
2
12
BT1 BATCON
*RB500V_NC
D21
RB500V
R240 33_4
1 2
C282 18P
1 2
RTC_N01
+3VALW
Item3 Item4
R298
1K-0603
B B
RTC_N02
3.1V
C398 .1U/10V_4
AD[0..31]21,24,25
PME#21,24,25,31 PCLK_ICH17
C C
PLTRST#8,13,20,31,32
Try to remove 7SH32, if possible.
D D
1
RTC_RST#
JP5 *SHORT PAD
3.8V
+3VRUN
4
2
NMI5 A20M#5
FERR#5
IGNNE#5 INTR5
CPUINIT#5
RCIN#32
GATEA2032
C397
.1U/10V_4
R296
3K_6
R228 10K-0402
U34
7SH32
2
C396 1U/10V_6
R297
4.7K_6
R295 15K/F
1 2
PCIRST#2 1,24,25
CLKRUN#24,25,31,32
R204 10K-0402
+3VSUS
C439
5
2 1
PDD[0..15]20
PDCS1#20 PDCS3#20 PDA020 PDA120 PDA220 PDIOR#20 PDIOW#20 PIORDY20 IRQ1420 PDDREQ20 PDDACK#20
C233
12
15P
23
C232
12
15P
SM_INTRUDER#
FERR#
R199 56_4
1 2
RCIN# GATEA20
Item24 Delet R196
VCCRTC
+5VALW
12
12
.047U/10V_4
PLTRST#_1
3
CLK_32KX1
14
32.768KHZ W1
CLK_32KX2
PDD[0..15]
3
R205 10M_4
1 2
R_FERR#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PCIRST# PLTRST#_1
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
PDCS1# PDCS3# PDA0 PDA1 PDA2 PDIOR# PDIOW# PIORDY IRQ14 PDDREQ PDDACK#
AA2 AA3
AA5
AF25 AF23 AF24 AG26 AG24 AF27 AD23 AF22
AF19
AD14 AF15 AF14 AD12 AE14 AC11 AD11 AB11 AE13 AF13 AB12 AB13 AC13 AE15 AG15 AD13
AD16 AE17 AC16 AB17 AC17 AE16 AC14 AF16 AB16 AB14 AB15
Y1 Y2
E2 E5
C2
F5 F3 E9 F2
D6
E6
D3
A2 D2 D5 H3
B4
J5
K2
K5 D4
L6 G3 H4 H2 H5
B3 M6
B2
K6
K3
A5
L1
K4
P6 G6 R2 R5
4
U35A
RTCX1 RTCX2
RTCRST# INTRUDER#
INTVRMEN
NMI A20M# FERR# IGNNE# INTR INIT# RCIN# A20GATE
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PME# PCICLK PCIRST# PLTRST# CLKRUN#/GPIO32
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
DCS1# DCS3# DA0 DA1 DA2 DIOR# DIOW# IORDY IDEIRQ DDREQ DDACK#
ICH6-M
4
RTC
CPU
PCI
IDE
LAD0 LAD1/FB1 LAD2/FB2 LAD3/FB3
LDRQ0#
LDRQ1#/GPI41
LPC
LFRAME#
CPUPWRGD/GPO49
INIT3_3V#
THRMTRIP#
SMI#
STPCLK#
CPUSLP#
DPSLP#/TP[2]
DPRSLP#/TP[4]
C/BE0# C/BE1# C/BE2# C/BE3#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP# SERR#
PERR#
PLOCK#
REQ0# REQ1# REQ2# REQ3#
REQ4#/GPI40
REQ5#/GPI1 REQ6#/GPI0
GNT0# GNT1# GNT2#
GNT3# GNT4#/GPO48 GNT5#/GPO17 GNT6#/GPO16
PIRQA# PIRQB# PIRQC# PIRQD#
PIRQE#/GPI2
PIRQF#/GPI3 PIRQG#/GPI4 PIRQH#/GPI5
SATALED#
SATA0_RXN
SATA0_RXP SATA0_TXN SATA0_TXP
SATA2_RXN
SATA2_RXP SATA2_TXN
SATA
SATA2_TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2
ACZ_SDO
AC-97/
AZALIA
PAR
P2 N3 N5 N4 N6 P4 P3
AG25 AE22 AE23 AG27 AE26 AE27 AD27 AE24
J6 H6 G4 G2
J3 A3 J2 C3 J1 E1 G5 E3 C5
L5 B5 M5 B8 F7 E8 B7
C1 B6 F1 C8 E7 F6 D8
N2 L2 M1 L3 D9 C7 C6 M3
AC19 AE3
AD3 AG2 AF2
AD7 AC7 AF6 AG6
AC2 AC1
AG11 AF11
C10 B9 A10
F11 F10 B10 C9
5
5
LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LPC_DRQ0# LPC_DRQ1#
LFRAME#/FWH4
CPUPWRGD
THERMTRIP#_ICH
R_CPUSLP#
R208 *0_NC R200 0_4
C/BE0# C/BE1# C/BE2# C/BE3#
FRAME# IRDY# TRDY# DEVSEL# STOP# PAR SERR# PERR# PLOCK#
REQ0# REQ1# REQ2# REQ3# REQ4# REQ5# REQ6#
GNT0# GNT1# GNT2#
T70 T76 T61 T65
PIRQA# PIRQB# PIRQC# PIRQD# ICH_GPIO2
2 1
D18 BAS316
SATA_LED# SATA_RXN0_C
SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
CLK_PCIE_SATA# 17 CLK_PCIE_SATA 17
R207 24.9 /F
SATABIAS
1 2
Place within 500mils of ICH6 ball
R276 39_4 R275 39_4 R277 39_4
T60 T135
R274 39_4
*10P_4_NC
LAD0/FWH 0 31,32 LAD1/FWH 1 31,32 LAD2/FWH 2 31,32 LAD3/FWH 3 31,32 LPC_DRQ0# 31
LFRAME#/FWH4 31,32
CPUPWRGD 5
R201 56_4
1 2 1 2
Item1
12
C383
6
DPRSTP#
R197 56_4
C/BE0# 2 1,24,25 C/BE1# 2 1,24,25 C/BE2# 2 1,24,25 C/BE3# 2 1,24,25
FRAME# 21,24,25 IRDY# 21,24,25 TRDY# 21,24,25 DEVSEL# 21,24,25 STOP# 21,24,25 PAR 21,24,25 SERR# 21,24,25 PERR# 21,24,25 PLOCK# 21
REQ0# 25 REQ1# 21 REQ2# 24
GNT0# 25 GNT1# 21 GNT2# 24
PIRQA# 21,25 PIRQB# 24 PIRQC# 21 PIRQD# 21,24
M_SEN# 19,31
SATA_RXN0_C 20 SATA_RXP0_C 20
C380 *10P_4_NC
1 2
6
+VCCP
< 2"
1 2
AC_BITCLK 28 AC_SYNC 28 AC_RESET# 28
AC_SDOUT 28
R198 75/F_4
SERIRQ13,21,24,31,32
Item1
7
RCIN# SERIRQ IRDY# GATEA20
+3VRUN
+3VRUN
REQ0 : LAN REQ1 : 1394/CARDBUS
REQ2 : MINI PCI
GNT0 : LAN GNT1 : 1394/CARDBUS
GNT2 : MINI PCI
IRQ14
PIRQD# STOP# PIRQA# PIRQC#
THERMTRIP# 5,8 SMI# 5 STPCLK# 5 CPUSLP# 5,7 DPSLP# 5 DPRSTP# 5
+VCCP
+3VRUN
MB_ID0 MB_ID1 MB_ID2
2
REQ5# SERR# REQ4# REQ0#
PCI Pullups
RP13
6 7 8 9
10
8.2KX8
RP11
6 7 8 9
10
8.2KX8
Dothan A
Dothan B
Yonah Installed NC
RP12
6 7 8 9
10
8.2KX8
R273
*100K_4_NC
Board ID
+3VRUN
13
47K
Q30
10K
*DTA114YUA
5 4 3 2 1
5 4 3 2 1
R309 R308
Installed Installed
NC NC
R280
*100K_4_NC
R272 1K-0402
HDD LED
HDDLED# 20,24
Item58
C437 *3900P
SATA_TXN0_C
SATA_TXP0_C
AC_SDIN0 28
Size Document Number Rev
ICH6-M (CPU, PCI, IDE, SATA, AC97)
Date: Sheet
7
1 2
C438 *3900P
1 2
Distance between the ICH-6 M and cap on the "P" signal should be identical distance between the ICH-6 M and cap on the "N" signal for same pair.
SATA_RXN0 20
SATA_RXP0 20
PROJECT : ED2
Quanta Computer Inc.
12 38Friday, October 22, 2004
8
+3VRUN
+3VRUN
5 4 3 2 1
R279 1K-0402
8
REQ3# DEVSEL# PERR#
PIRQB# REQ2# TRDY# FRAME#
+3VRUN
+3VRUN
of
PLOCK# REQ6# REQ1# ICH_GPIO2
R237
*100K_4_NC
R236 1K-0402
C2A
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