Benq S41, QUANTA CH3 Schematics REV 1ASec.pdf
5
hexainf@hotmail.com
4
3
2
1
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : SGND1
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : SVCC
D D
LAYER 6 : IN3
PCI DEVICES IRQ ROUTING
IDSEL#
PCI8402 INT A/B/E#
AD25 REQ0# / GNT0#
InterruptsPCI DEVICE REQ# / GNT#
LAYER 7 : SGND2
LAYER 8 : BOT
CPU CORE SC452
PAG 38
CH3 BLOCK DIAGRAM
CPU
Merom
479P (uPGA)/35W
PAG 3,4
CPU THERMAL
SENSOR
PAG 5
CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK#
DREFCLK,DREFCLK#
DREFSSCLK,DREFSSCLK#
01
14.318MHz
CLOCK GEN
ICS9LPRS363AGLFT
64pinsTSSOP
PAG 2
VGACORE(1.025V)MAX1993
INT-VGACORE MAX8776
VCCP +1.5V AND GMCH
1.05V(TPS51124)
C C
SYSTEM POWER MAX8734
DDR II SMDDR_VTERM
1.8V/1.8VSUS(TPS51116)
SYSTEM CHARGER(MAX8724)
Voltage Rails
B B
VCC_CORE
VCCP
SMDDR_VTERM
VGACORE
VGA1.2
RVCC3
VCC1.25
VCC1.5
VCC1.8
VCC2.5
VCC3
VCC5
A A
1.8VSUS
3VSUS
5VSUS
3VPCU
5VPCU
15VPCU
PAG 39
PAG 40
PAG 41
PAG 42
PAG 43
PAG 45,46
DDRII-SODIMM1
DDRII-SODIMM2
SATA - HDD
PATA-
USB2.0 I/O Ports
Voltage Rails
ON S0~S2 Ctl Signal
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ON S3 ON S4 ON S5
X
X
X
X
X
X
5
VR_ON
MAINON
MAINON
MAINON
MAINON
XX
X
X
X
RVCCD
MAINON
MAINON
MAIND
MAINON
MAIND
MAIND
SUSON
SUSD
SUSD
8734LDO5
X
8734LDO5
X
5VPCU
X
PAG 12,13
PAG 12,13
PAG 33
CD-ROM
PAG 33
Bluetooth
Camera
Mini_PCI_E
Express Card
4
DDRII 533,667 MHz
DDRII 533,667 MHz
SATA0 150MB
(66/100/133)
PATA
0,1,2,3
X4
4
6
7
9
Keyboard
Touch Pad
PAG 29
USB2.0
NORTH BRIDGE
Crestline
Santa Rosa
PAG 5,6,7,8,9,10,11
SOUTH BRIDGE
PC87541
PAGE 37
FAN
3
DMI LINK
ICH-8M
PAG 20,21,22,23
LPC
BIOS
PAG 37PAG 30
PCI-Express 16X
PCI BUS / 33MHz
PCI-E
Azalia
ALC262
Audio Jack
PAG 35
Audio
Amplifier
SPEAKER
PAG 34,35
MODEM RJ 11
2
NVDIA NB8P
PAG 14,15,16,17,18,19,20
PCI8402
PAG 26~28
14 26
Mini PCI-E
Card
WLAN
PAG 31 PAG 32
MDC
PAG 34PAG 35
PAG 35PAG 35
Mini PCI-E
Card
Robson
PAG 31
Size Document Number Re v
BLOCK DIAGRAM
Date: Sheet
DDR3 X 4
PAG 18,19
LCD CON
PAG 25
CRT PORT
PAG 24
HDMI CON
PAG 36
NBSRCCLK, NBSRCCLK#
IEEE1394
PAG 26
Memory
CardReader
PAG 27
LAN
Marvell
PCIE-LAN
M8055
RJ45
PAG 32
Express
Card
PAG 28
PROJECT : CH3
Quanta Computer Inc.
146Tuesday, February 06, 2007
1
of
1A
1
2
3
4
5
6
7
8
VCC3
L16
1 2
BLM21PG600SN1D
C895
3.3N/50V
A A
Add 3.3N CAP for EMI suggestion
Nicole 12/11
VCC3
VCC3
Add 3.3N CAP for EMI suggestion
B B
Nicole 12/11
L17
1 2
BLM21PG600SN1D
L19
1 2
BLM21PG600SN1D
C896
3.3N/50V
PDAT_SMB13,22,28,31
PCLK_SMB13,22,28,31
12
C96
10U_0805
12
12
C101
10U_0805
C132
0.1U/10V
12
C97
10U_0805
Q6
2N7002E
3
Q5
2N7002E
3
12
12
C134
0.1U/10V
VCC3
VCC3
C159
0.1U/10V
12
C113
0.1U/10V
VDDA
R59
2
2
10K
1
1
12
C157
0.1U/10V
VDDCPU
VDDA
12
VDDCPU
R57
10K
CGDAT_SMB
CGCLK_SMB
C156
0.1U/10V
12
C154
0.1U/10V
CLKUSB_4822
CLK_3.3V
14M_ICH22
PM_STPCPU#22
PM_STPPCI#22
12
DREFCLK6
DREFCLK#6
C158
0.1U/10V
CK_PWG22
CLK_3.3V
12
12
CLKUSB_48
CLK_BSEL0
14M_ICH
VCC3
C133
C160
0.1U/10V
0.1U/10V
VCC3
R459
*10K/F
VCC3
R60 1K/F_4
R58 348_6
RP46 *I@4P2R-S-33
1
3
R460
*10K/F
R107 33_4
R106 2.2K/F_4
R95 10K/F_4
R461 10K/F_4
R462 33_4
2
4
(96MHz)
CPU Clock select
C C
D D
CPU_BSEL03
VCC3
BSEL2 BSEL1 BSEL0 CPU
0
0
0
0
0
*
0
1
1
0
1
011
1
1
1
1
1
FSAFSBFSC
0
1
0
1
0
0
1
R109 0
R108 *56
R105 *1K
SRC
266.66
100
133.33
100
100
200.00
166.66
100
333.33
100
100.00
100
400.00
100
200.00 100 33.33
2
CLK_BSEL0CPU_BSEL0
R110 0
PCI
REF
USB48DOT
33.33
14.318
33.33 14.318 48 96
33.33 14.318 48 96
33.33 14.318 48 96
33.33 14.318 48 96
33.33 14.318 48 96
33.33 14.318 48 96
14.318 48 96
96
Spread
%
0.5 Down
0.5 Down
0.5 Down
0.5 Down
0.5 Down
0.5 Down
0.5 Down
0.5 Down
3
MCH_BSEL0 6
R_PCLK_DEBUG
R_PCLK_541
Update for Robson CLKREQ#
nicole 9/20
R_PCLK_ICH
SELPCIEX0_LCD#
Pin64
PCIEXCLK
0
PEREQ#
1
*
PCIE_REQ1#
PCIE_REQ2#
Pin8
*
PCIE_L0
PCIE_L1
PCIE_L2PCIE_REQ3#
PCIE_L3
1.Level 1 Environment-related Substances Should NEVER be Used.
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
4
BG614318F84
XTL-5_3X3_2-3_8-1_2H
21
CLK_XIN
CLK_XOUT
CGCLK_SMB
CGDAT_SMB
CLK_BSEL1
CLK_BSEL2
96/100M
SRC Pair
CLK_XIN
Y3
14.318MHZ/20P
CLK_XOUT
58
57
62
63
54
55
12
16
61
60
1
7
11
56
21
28
42
50
47
45
10
14
15
34
37
2
6
13
29
53
59
46
internal bu ild-in 33ohm
damping resisteor
U19
X1
ICS9PR363DGLF
X2
CPU_STOP#
PCI/PCIEX_STOP#
SCLK
SDATA
FSA/USB_48MHZ
FSB/TEST_MODE
FSC/REF1/TEST_SEL
REF0
VDDPCI
VDDPC1
VDD48
VDDREF
VDDPCIEX
VDDPCIEX
VDDPCIEX
VDDCPU
VREF
VDDA
VTTPWR_GD/PD#
PCIET_L9/DOTT_96MHZ
PCIEC_L9/DOTC_96MHZL
*PWRSAVE#
GND
GND
GND
GND
GND
GND
GND
GNDA
VCC3
LATCH SELECT TABLE
Pin5 Pin9
*
CPUT_L0
CPUC_L0
CPUT_L1F
CPUC_L1F
CPUITPT_L2/PCIET_L8
CPUITPC_L2/PCIEC_L8
27FIX/LCD_SSCGT/PCIET_L0
27SS/LCD_SSCGC/PCIEC_L0
SATACLKT_L
SATACLKC_L
PCIET_L1
PCIEC_L1
PCIET_L2
PCIEC_L2
PCIET_L3
PCIEC_L3
PCIET_L4
PCIEC_L4
PCIET_L5
PCIEC_L5
PCIET_L6
PCIEC_L6
PEREQ1#/PCIET_L7
PEREQ2#/PCIEC_L7
*PEREQ3#
*PEREQ4#
**REQ_SEL/PCICLK0
PCICLK1
*SELPCIEX0_LCD#/PCICLK3
*SELLCD_27#/PCICLK_F5
0
0
PCICLK2
ITP_EN/PCICLK_F4
* Internal pull up to VDD
**Internal pull down to GND
PWRSAVE#
PCIE_REQ2#
PCIE_REQ3#
PCIE_REQ4#
0
1
1x
PN change from B version to D version
nicole 12/01
RHCLK_CPU
52
RHCLK_CPU#
51
RHCLK_MCH
49
RHCLK_MCH#
48
RSRC_RB
44
RSRC_RB#
43
R_DREFSSCLK
17
R_DREFSSCLK#
18
RSRC_SATA
26
RSRC_SATA#
27
R_CLK_PCIE_VGA
19
R_CLK_PCIE_VGA#
20
CLK_PCIE_NEW
22
CLK_PCIE_NEW#
23
RSRC_ICH
24
RSRC_ICH#
25
CLK_PCIE_MINI_
30
CLK_PCIE_MINI_#
31
RSRC_MCH
36
RSRC_MCH#
35
RSRC1_LAN
39
RSRC1_LAN#
38
41
40
32
33
R_PCLK_DEBUG
64
R_PCI_CLK_8402
3
4
SELPCIEX0_LCD#
5
R_PCLK_ICH PCLK_ICH
8
R_PCLK_541 PCLK_541
9
R71 *10K_4
R457 10K_4
R92 10K_4
R69 10K_4
RP1
RP2 4P2R-S-33
RP5 4P2R-S-33
RP45 *I@4P2R-S-33
RP42 4P2R-S-33
RP44 4P2R-S-33
RP40 4P2R-S-33
RP43 4P2R-S-33
RP41 4P2R-S-33
RP3 4P2R-S-33
RP4 4P2R-S-33
R_PCIE_REQ 2#
R_PCIE_REQ 3#
R_PCIE_REQ 4#
R68 475/F_4
R474 475/F_4
R65 475/F_4
R66 33_4
R475 33_4
R94 33_4
R103 33_4
VCC3
Pin17/18Pin14/15
PCIEX9
PCIEX9
DOT96
27MHz
LCD
PCIEX0
4
2
4
2
4
2
2
4
2
4
2
4
2
4
2
4
2
4
4
2
4
2
4P2R-S-33
3
1
3
1
3
1
1
3
1
3
1
3
1
3
1
3
1
3
3
1
3
1
PCLK_DEBUG
PCI_CLK_8402
14M_ICH
PCLK_DEBUG
CLKUSB_48
PCLK_541
PCLK_ICH
PCI_CLK_8402
REQ2#
REQ3#
REQ4#
C662 30P
C664 30P
CLK_3.3V
VDDCPU
VDDA
R_DREFCLK
R_DREFCLK#
PWRSAVE#
R67 10K_4
R96 10K_4 C115 15P
R476 10K_4
R477 *10K_4
0
1 CPUITP Pair
PCIE_L6
PCIE_L8
PCIE_L4
PCIE_L7PCIE_REQ4# PCIE_L5
Size Document Number Re v
CLOCK GENERATOR
5
6
Date: Sheet
7
PROJECT : CH3
Quanta Computer Inc.
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
CLK_MCH_BCLK 5
CLK_MCH_BCLK# 5
CLK_PCIE_MINI_RB 31
CLK_PCIE_MINI_RB# 31
DREFSSCLK 6
DREFSSCLK# 6
CLK_PCIE_SATA 20
CLK_PCIE_SATA# 20
CLK_PCIE_VGA 14
CLK_PCIE_VGA# 14
CLK_PCIE_NEW_C 28
CLK_PCIE_NEW_C# 28
CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21
CLK_PCIE_MINI_WLAN 31
CLK_PCIE_MINI_WLAN# 31
CLK_PCIE_3GPLL 6
CLK_PCIE_3GPLL# 6
CLK_PCIE_LAN 32
CLK_PCIE_LAN# 32
PCIE_REQ2# 31
PCIE_REQ3# 28
PCIE_REQ4# 6
PCI_CLK_8402 26
PCLK_ICH 21
PCLK_541 36
C657 15P
C689 15P
C192 15P
C193 15P
C688 15P
used for ROBSON
used for NEWCARD
used for GMCH
PCLK_DEBUG 31
246Tuesday, February 06, 2007
8
02
1A
of
14.318MHz
1
hexainf@hotmail.com
2
3
4
5
6
7
8
03
H_A#[3..16]5
A A
H_ADSTB#05
H_REQ#[0..4]5
H_A#[17..35]5
B B
H_ADSTB#15
H_A20M#20
H_FERR#20
H_IGNNE#20
H_STPCLK#20
H_INTR20
H_NMI20
H_SMI#20
C C
H_A#[3..16]
H_REQ#[0..4]
H_A#[17..35]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
ITP PU
ITP_DBRESET#
ITP_TMS
ITP_TDI
ITP_BPM#5
ITP_TCK
ITP_TRST#
R61 *54.9/F_4
R23 39/F_4 R468
R28 150/F_4
R26 54.9/F_4
R22 27/F
R24 680/F_4
12
VCCP
U17A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
DEFER#
CONTROL
RESET#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
XDP/ITP SIGNALS
ADS#
BNR#
BPRI#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
ITP_BPM#0
AD4
ITP_BPM#1
AD3
ITP_BPM#2
AD1
ITP_BPM#3
AC4
ITP_BPM#4
AC2
AC1
AC5
AA6
TDI
AB3
AB5
AB6
C20
ADDR GROUP 0 ADDR GROUP 1
THERMAL
THERMDA
THERMDC
H CLK
BCLK[0]
BCLK[1]
D21
A24
B25
C7
A22
A21
PROCHOT#
ICH
THERMTRIP#
RESERVED
ITP disable guidelines
R62 56
H_IERR#H_A#13
1 2
H_RESET#
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
R63 75
CPU_PROCHOT#CPU_PROCHOT#
H_THERMDA
H_THERMDC
PM_THRMTRIP#
12
H_ADS# 5
H_BNR# 5
H_BPRI# 5
H_DEFER# 5
H_DRDY# 5
H_DBSY# 5
H_BR0# 5
VCCP
H_INIT# 20
H_LOCK# 5
H_RESET# 5
H_RS#0 5
H_RS#1 5
H_RS#2 5
H_TRDY# 5
H_HIT# 5
H_HITM# 5
T5
T6
T7
T4
T2
T3
VCCP
H_THERMDA 30
H_THERMDC 30
PM_THRMTRIP# 6,20
CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2
Layout Note:
Place voltage
divider within
0.5" of GTLREF
pin
VCCP
R470
1K/F
1 2
R471
2K/F
1 2
R64 *1K/F
1 2
R472 *1K/F
1 2
C672 *0.1 U/1 0V
R466 *0
1 2
Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.
H_D#[0..63]5
H_DSTBN#05
H_DSTBP#05
H_DINV#05
H_D#[0..63]5
H_DSTBN#15
H_DSTBP#15
H_DINV#15
CPU_BSEL02
CPU_TEST1
CPU_TEST2
CPU_TEST4
12
CPU_TEST6
FSB
BCLK
533 001133
166
667
200
800
Signal Resistor Value Connect To Resistor Placement
150 ohm +/- 5%
D D
1
TDI
TMS
39 ohm +/- 1%
TRST#
500-680ohm +/- 5%
27 ohm +/- 1%
TCK
TDO
150 ohm +/- 5%
2
3
Within 2.0" of the ITPVTT
VTT
Within 2.0" of the ITP
GND
Within 2.0" of the ITP
GND
Within 2.0" of the ITP
VTT
Within 2.0" of the ITP
4
H_D#[0..63]
H_D#[0..63]
T152
T151
BSEL2 BSEL1 BSEL0
0
1
1
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
T13
T1
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
U17B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Merom Ball-out Rev 1a
CPU_TEST3
CPU_TEST5
DATA GRP 0
DATA GRP 1
MISC
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
DATA GRP 2DATA GRP 3
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
1
00
Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.
Size Document Number Rev
CPU
6
Date: Sheet
7
H_D#[0..63]
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#[0..63]
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.
COMP0
COMP1
COMP2
COMP3
R27
R25
27.4/F
54.9/F
1 2
1 2
PROJECT : CH3
Quanta Computer Inc.
H_D#[0..63] 5
H_DSTBN#2 5
H_DSTBP#2 5
H_DINV#2 5
H_D#[0..63] 5
H_DSTBN#3 5
H_DSTBP#3 5
H_DINV#3 5
H_DPRSTP# 6,20,37
H_DPSLP# 20
H_DPWR# 5
H_PWRGD 20
H_CPUSLP# 5
PM_PSI# 37
R469
54.9/F
27.4/F
1 2
1 2
346Tuesday, February 06, 2007
of
8
1A
1
2
3
4
5
6
7
8
ICCODE:
04
VCC_CORE
C635
10U/6.3V
C80
10U/6.3V
12
12
12
A A
VCC_CORE
12
C636
10U/6.3V
C58
10U/6.3V
12
C93
10U/6.3V
12
C74
10U/6.3V
12
C89
10U/6.3V
12
C650
10U/6.3V
12
C79
10U/6.3V
12
C65
10U/6.3V
8 inside cavity, north side, secondary layer.
VCC_CORE
12
B B
VCC_CORE
12
C643
10U/6.3V
C651
10U/6.3V
12
C640
10U/6.3V
12
C645
10U/6.3V
12
12
C648
10U/6.3V
C64
10U/6.3V
12
C638
10U/6.3V
12
C73
10U/6.3V
12
C646
10U/6.3V
12
C637
10U/6.3V
8 inside cavity, south side, secondary layer.
VCC_CORE
12
C91
10U/6.3V
12
C95
10U/6.3V
12
C57
10U/6.3V
12
C649
10U/6.3V
12
C639
10U/6.3V
12
C642
10U/6.3V
6 inside cavity, north side, primary layer.
VCC_CORE
C C
12
C66
10U/6.3V
12
C72
10U/6.3V
12
C78
10U/6.3V
12
10U/6.3V
C90
12
C94
10U/6.3V
12
C56
10U/6.3V
6 inside cavity, south side, primary layer.
VCC_CORE VCC_CORE
U17C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
.
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
VCCSENSE
VSSSENSE
Update to 10u *32pcs. OK
VCCP
C53
0.1U/10V
12
12
Layout out:
Place these inside socket cavity on North side secondary.
D D
1
C98
0.1U/10V
12
C54
0.1U/10V
C99
0.1U/10V
12
12
2
C55
0.1U/10V
12
C100
0.1U/10V
3
4
for Merom processors
recommended design
target is 44A
ICCP:
1before vccore stable
peak current is 4.5A
2.after vccore stable
VCCP
continue current is
2.5A
12
+
C75
330U/2.5V
ICCA 130mA
CPU_VID0 37
CPU_VID1 37
CPU_VID2 37
CPU_VID3 37
CPU_VID4 37
CPU_VID5 37
CPU_VID6 37
VCCSENSE 37
VSSSENSE 37
VCC_CORE
VCCSENSE
VSSSENSE
Route VCCSENSE and VSSSENSE
traces at 27.4ohms and
length matched to within 25
mil. Place PU and PD within
2 inch of CPU.
5
VCC1.5
12
C169
.01U/25V
Layout Note:
Place C105 near PIN
B26.
12
R43
100/F
12
R37
100/F
6
12
C176
10U/6.3V
U17D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Merom Ball-out Rev 1a
Size Document Number Rev
CPU
Date: Sheet
7
PROJECT : CH3
Quanta Computer Inc.
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
of
446Tuesday, February 06, 2007
8
1A
1
hexainf@hotmail.com
2
3
4
5
6
7
8
05
H_A#[3..35]
H_ADS# 3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR# 3
H_BPRI# 3
H_BR0# 3
H_DEFER# 3
H_DBSY# 3
CLK_MCH_BCLK 2
CLK_MCH_BCLK# 2
H_DPWR# 3
H_DRDY# 3
H_HIT# 3
H_HITM# 3
H_LOCK# 3
H_TRDY# 3
H_DINV#0 3
H_DINV#1 3
H_DINV#2 3
H_DINV#3 3
H_DSTBN#0 3
H_DSTBN#1 3
H_DSTBN#2 3
H_DSTBN#3 3
H_DSTBP#0 3
H_DSTBP#1 3
H_DSTBP#2 3
H_DSTBP#3 3
H_REQ#0 3
H_REQ#1 3
H_REQ#2 3
H_REQ#3 3
H_REQ#4 3
H_RS#0 3
H_RS#1 3
H_RS#2 3
H_A#[3..35] 3
M10
N12
W10
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AH8
AJ14
AE9
AE11
AH12
AH5
AE7
AE5
AH2
AH13
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
P13
K9
M2
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
Y3
AJ9
AJ5
AJ6
AJ7
AJ2
AJ3
B3
C2
W1
W2
B6
E5
B9
A9
U25A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
HOST
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
12
C209
0.1U/10V
H_D#[0..63]
H_RESET#3
H_CPUSLP#3
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_REF
H_D#[0..63]3
A A
VCCP
12
R118
221/F
H_SWING
12
R114
100/F
B B
VCCP
C191
0.1U/10V
1 2
impedance 55 ohm
12
12
R111
R116
54.9/F
54.9/F
H_SCOMP
H_SCOMP#
12
R113
24.9/F
C C
H_RCOMP
Layout Note:
H_RCOMP trace should be
10-mil wide with 15-mil
spacing.
VCCP
R134
1K/F
1 2
12
R127
2K/F
Layout Note:55ohm
Place the 0.1 uF
D D
1
2
decoupling capacitor
within 100 mils from
GMCH pins.
3
Size Document Number Rev
4
5
6
Date: Sheet
PROJECT : CH3
Quanta Computer Inc.
NB
7
546Tuesday, February 06, 2007
8
1A
of
1
A A
WW22 update
--- MA14 needs
to be routed if
customers are
planning on
using 2Gb
technology and
width=8 (by 8)
DIMMs
SA_MA1413
SB_MA1413
R207 1K/F_4
R196 1K/F_4
T35
T177
T30
T25
T27
T50
T40
T28
T31
T44
T64
R264 0
R255 0
R247 0
R177 100
R178 *0
R240 0
T183
T75
PM_THRMTRIP#_GMCH
PM_DPRSLPVR_GMCH
PM_EXTTS#0
PM_EXTTS#1
CRESTLINE
new pin
define
Layout Note:
B B
C C
D D
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.
MCH_BSEL02
VCCP
MCH_CFG_511
MCH_CFG_911
MCH_CFG_1211
MCH_CFG_1311
MCH_CFG_1611
MCH_CFG_1911
MCH_CFG_2011
PM_BMBUSY#22
H_DPRSTP#3,20,37
PM_EXTTS#013
PM_EXTTS#113
PWROK22
PLT_RST-R#14,21
PM_THRMTRIP#3,20
DPRSLPVR22,37
GMCH pwrok is 3.3v
tolerant
VCC3
R509 10K
1 2
R251 10K
1 2
1
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_BMBUSY#_R
ICH_DPRSTP#_R
PM_EXTTS#1_R
PLTRST_MCH#
2
2
U25B
P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
G41
L39
L36
J36
AW49
AV20
N20
G36
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
CRESTLINE_1p0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
SA-MA14
SB_MA14
RSVD34
RSVD35
RSVD36
LVDSA_DATA#_3
LVDSA_DATA_3
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
SM_RCOMP_VOH
12
C274
.01U/25V
SM_RCOMP_VOL
12
C301
.01U/25V
12
12
C268
2.2U/10V
C315
2.2U/10V
DDR MUXINGCLKDMI
CFGRSVD
PM
GRAPHICS VIDME
NC
MISC
3
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
TEST_1
TEST_2
1.8VSUS
12
R211
1K/F
12
R212
3.01K/F
12
R226
1K/F
3
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
SMRCOMPP
BL15
SMRCOMPN
BK14
SM_RCOMP_VOH
BK31
SM_RCOMP_VOL
BL31
SMDDR_VREF_MCH
AR49
R276 *10K/F
AW4
R269 *10K/F
B42
C42
H48
H47
K44
K45
DMI_TXN0
AN47
DMI_TXN1
AJ38
DMI_TXN2
AN42
DMI_TXN3
AN46
DMI_TXP0
AM47
DMI_TXP1
AJ39
DMI_TXP2
AN41
DMI_TXP3
AN45
DMI_RXN0
AJ46
DMI_RXN1
AJ41
DMI_RXN2
AM40
DMI_RXN3
AM44
DMI_RXP0
AJ47
DMI_RXP1
AJ42
DMI_RXP2
AM39
DMI_RXP3
AM43
E35
A39
C38
B39
DFGT_VR_EN
E36
update per design guide v1.1
9/29
AM49
AK50
AT43
AN49
AM50
MCH_CLVREF
H35
K36
G39
G40
A37
R32
R224
20K
1 2
MCH_CLVREF
C745
0.1U/10V
1 2
4
M_A_CLK0 13
M_A_CLK1 13
M_B_CLK0 13
M_B_CLK1 13
M_A_CLK0# 13
M_A_CLK1# 13
M_B_CLK0# 13
M_B_CLK1# 13
M_A_CKE0 12,13
M_A_CKE1 12,13
M_B_CKE0 12,13
M_B_CKE1 12,13
M_A_CS#0 12,13
M_A_CS#1 12,13
M_B_CS#0 12,13
M_B_CS#1 12,13
M_A_ODT0 12,13
M_A_ODT1 12,13
M_B_ODT0 12,13
M_B_ODT1 12,13
C375 0.1U/10V
C376 0.1U/10V
R270 0
DREFCLK 2
DREFCLK# 2
DREFSSCLK 2
DREFSSCLK# 2
CLK_PCIE_3GPLL 2
CLK_PCIE_3GPLL# 2
DMI_TXN[3:0] 21
DMI_TXP[3:0] 21
DMI_RXN[3:0] 21
DMI_RXP[3:0] 21
R203 E@0/I@1.3K
<check list & CRB>
For Calero : 255
For Cresstline:1.3K/F
For external VGA:0 ohm
GVR_VID0 39
GVR_VID1 39
GVR_VID2 39
GVR_VID3 39
T178
CL_CLK0 22
CL_DATA0 22
ECPWROK 17,22,36
CL_RST#0 22
T215
PCIE_REQ4# 2
MCH_ICH_SYNC# 22
R246
0
1 2
VCC1.25
12
R519
1K/F
12
R516
392/F
4
VCC3
EDIDCLK16,17,25
EDIDDATA16,17,25
DIGON17,25
<check list & CRB>
For Calero : 1.5K
For Cresstline:2.4K
SMDDR_VREF
1.8VSUS
VCC3
<FAE>
If no use can be NC
CRT_B16,24
CRT_G16,24
CRT_R16,24
CRTCLK16,24
CRTDAT16,24
HSYNC_COM16,24
VSYNC_COM16,24
In Crestline EDS Rev.1.0,
Render Standb y V oltage is not
finalized yet(TBD), 1.05V for
Graphic Voltage
range(VCC_AXG) is between
0.9975V(min.) and
1.1025V(max.). Vgfx max at
1.1025V @ 8A (estimated)
only reserve AT3/5 not support IAMT,
but design guide suggest to connection
these pin ,do not NC
CLKREQ# ( MCH drives CLK_REQ#
to control the PCI-E diff clk input
itself )
1.8VSUS
12
R152
20/F
SMRCOMPP
SMRCOMPN
R146
20/F
12
5
BLON17,25
R243 *I@10K
R258 *I@10K
R513 *I@0
R510 *I@0
R263 *I@0
R262 *I@2.4K
I&E Dis/Enable
setting
R237 **I@2.2K
R267 **I@2.2K
5
R261 *I@0
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
T74
LA_CLK#16
LA_CLK16
LA_DATAN016
LA_DATAN116
LA_DATAN216
LA_DATAP016
LA_DATAP116
LA_DATAP216
connect to GND <design guide>
nicole 10/19
TV_DCONSEL_0
TV_DCONSEL_1
R82 *I@0
R80 *I@0
R76 *I@0
R265 *I@0
R225 *I@0
R86 *I@30
R90 *I@30
<check list>
HSYNC/VSYNC serial R
place close to NB
<Design Guide V1.1 P195>
If no use DREFCLK PD and
DREFCLK# PU
I&E Dis/Enable setting
<design gui d e V 1 . 1 P195>
If no use DREFCLK PD
and DREFCLK# PU
<check list>
For E@
Connect to GND
CRT R/G/B
TV A/B/C
HSYNC/VSYNC
NB_B
NB_G
NB_R
DREFSSCLK
DREFSSCLK#
DREFCLK
DREFCLK#
R220 E@0/I@150
R200 E@0/I@150
R202 E@0/I@150
R223 E@0
R214 E@0
T72
J40
H39
E39
E40
C37
D35
K40
LVDS_IBG
L41
L43
N41
N40
D46
C45
D44
E42
G51
E51
F49
G50
E50
F48
G44
B47
B45
E44
A47
A45
E27
G27
K27
F27
J27
L27
M35
P33
H32
G32
K29
J29
F29
E29
DDCCLK
K33
DDCDATA
G35
HSYNC11
F33
CRTIREF
C32
VSYNC11
E33
R274 E@0
R272 E@0
R268 E@0
R266 E@0
<check list>
For I@
Connect to 150ohm
CRT R/G/B
TV A/B/C
Connect to 30ohm
HSYNC/VSYNC
HSYNC11
VSYNC11
6
U25C
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
TVA_DAC
TVB_DAC
TVC_DAC
TVA_RTN
TVB_RTN
TVC_RTN
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
CRESTLINE_1p0
VCCP
NB_B
NB_G
NB_R
6
VCCP
LVDS
TV VGA
PCI-EXPRESS GRAPHICS
7
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
VCC_PEG_R
<=0.5''
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
C_PEG_TXN0
C_PEG_TXN1
C_PEG_TXN2
C_PEG_TXN3
C_PEG_TXN4
C_PEG_TXN5
C_PEG_TXN6
C_PEG_TXN7
C_PEG_TXN8
C_PEG_TXN9
C_PEG_TXN10
C_PEG_TXN11
C_PEG_TXN12
C_PEG_TXN13
C_PEG_TXN14
C_PEG_TXN15
C_PEG_TXP0
C_PEG_TXP1
C_PEG_TXP2
C_PEG_TXP3
C_PEG_TXP4
C_PEG_TXP5
C_PEG_TXP6
C_PEG_TXP7
C_PEG_TXP8
C_PEG_TXP9
C_PEG_TXP10
C_PEG_TXP11
C_PEG_TXP12
C_PEG_TXP13
C_PEG_TXP14
C_PEG_TXP15
R277 2 4.9 /F
1 2
C714 E@.1U/10V
C718 E@.1U/10V
C721 E@.1U/10V
C725 E@.1U/10V
C728 E@.1U/10V
C730 E@.1U/10V
C734 E@.1U/10V
C737 E@.1U/10V
C739 E@.1U/10V
C747 E@.1U/10V
C750 E@.1U/10V
C756 E@.1U/10V
C761 E@.1U/10V
C763 E@.1U/10V
C767 E@.1U/10V
C769 E@.1U/10V
C710 E@.1U/10V
C715 E@.1U/10V
C720 E@.1U/10V
C724 E@.1U/10V
C727 E@.1U/10V
C729 E@.1U/10V
C731 E@.1U/10V
C735 E@.1U/10V
C738 E@.1U/10V
C741 E@.1U/10V
C749 E@.1U/10V
C751 E@.1U/10V
C758 E@.1U/10V
C762 E@.1U/10V
C766 E@.1U/10V
C768 E@.1U/10V
+VCC_PEG
8
06
PEG_RXN0 14
PEG_RXN1 14
PEG_RXN2 14
PEG_RXN3 14
PEG_RXN4 14
PEG_RXN5 14
PEG_RXN6 14
PEG_RXN7 14
PEG_RXN8 14
PEG_RXN9 14
PEG_RXN10 14
PEG_RXN11 14
PEG_RXN12 14
PEG_RXN13 14
PEG_RXN14 14
PEG_RXN15 14
PEG_RXP0 14
PEG_RXP1 14
PEG_RXP2 14
PEG_RXP3 14
PEG_RXP4 14
PEG_RXP5 14
PEG_RXP6 14
PEG_RXP7 14
PEG_RXP8 14
PEG_RXP9 14
PEG_RXP10 14
PEG_RXP11 14
PEG_RXP12 14
PEG_RXP13 14
PEG_RXP14 14
PEG_RXP15 14
PEG_TXN_C0 14
PEG_TXN_C1 14
PEG_TXN_C2 14
PEG_TXN_C3 14
PEG_TXN_C4 14
PEG_TXN_C5 14
PEG_TXN_C6 14
PEG_TXN_C7 14
PEG_TXN_C8 14
PEG_TXN_C9 14
PEG_TXN_C10 14
PEG_TXN_C11 14
PEG_TXN_C12 14
PEG_TXN_C13 14
PEG_TXN_C14 14
PEG_TXN_C15 14
PEG_TXP_C0 14
PEG_TXP_C1 14
PEG_TXP_C2 14
PEG_TXP_C3 14
PEG_TXP_C4 14
PEG_TXP_C5 14
PEG_TXP_C6 14
PEG_TXP_C7 14
PEG_TXP_C8 14
PEG_TXP_C9 14
PEG_TXP_C10 14
PEG_TXP_C11 14
PEG_TXP_C12 14
PEG_TXP_C13 14
PEG_TXP_C14 14
PEG_TXP_C15 14
I&E Dis/Enable setting
<check list>
SDVO/PCIE/LVDS not implement,
16 lanes NC
R259 E@0
R231 E@0
R514 E@0
R511 E@0
R257 E@0
R239 E@0
R242 E@0
R260 E@0
Per desigen guide V1.1 p195
nicole 10/20
Size Document Number Rev
Date: Sheet
NB
7
DDCCLK
DDCDATA
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
TV_DCONSEL_0
TV_DCONSEL_1
PROJECT : CH3
Quanta Computer Inc.
646Tuesday, February 06, 2007
of
8
1A
1
hexainf@hotmail.com
2
3
4
5
6
7
8
07
M_A_DQ[63:0]13 M_B_DQ[63:0]13
A A
B B
C C
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BG10
AW9
AM8
AN10
AM9
AN11
BD8
AY9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AT9
AN9
U25D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
SA_WE#
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BE18
AY20
BA19
M_A_DQM0
M_A_DQM1
M_A_DQM2
M_A_DQM3
M_A_DQM4
M_A_DQM5
M_A_DQM6
M_A_DQM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP_SA_RCVEN#
M_A_BS#0 12,13
M_A_BS#1 12,13
M_A_BS#2 12,13
M_A_CAS# 12,13
M_A_DQM[0..7] 13
M_A_DQS[7:0] 13
M_A_DQS#[7:0] 13
M_A_A[13:0] 12,13
M_A_RAS# 12,13
T21
M_A_WE# 12,13
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK10
BL9
BK5
BL5
BK9
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
U25E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
M_B_DQM0
M_B_DQM1
M_B_DQM2
M_B_DQM3
M_B_DQM4
M_B_DQM5
M_B_DQM6
M_B_DQM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
TP_SB_RCVEN#
M_B_BS#0 12,13
M_B_BS#1 12,13
M_B_BS#2 12,13
M_B_CAS# 12,13
M_B_DQM[0..7] 13
M_B_DQS[7:0] 13
M_B_DQS#[7:0] 13
M_B_A[13:0] 12,13
M_B_RAS# 12,13
T19
M_B_WE# 12,13
D D
Size Document Number Rev
NB
1
2
3
4
5
6
Date: Sheet
PROJECT : CH3
Quanta Computer Inc.
7
746Tuesday, February 06, 2007
8
1A
of
INT: 1.6A
EXT:1.3A
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
W13
W14
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
5
R30
R20
T14
Y12
5
U25G
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
CRESTLINE_1p0
VCC CORE
POWER
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC GFX NCTF
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCCP
D D
IVCCSM supply
current 1
channel 1.615A 2
channel 3.318A
C C
B B
A A
1.8VSUS
+VGFX_CORE
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
4
Ivcc_AXG Graphics core supply
current 7.7A
12
+
C694
*I@330U/6.3V
Layout Note:
Inside GMCH cavity for VCC_AXG.
12
C237
*I@0.1U/10V
GMCH 1.05V
VCC Core
VCC_AXG
VCC_AXD
VTT
VCC_PEG
VCC_AXM
VCCR_RX_DMI
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
4
12
C210
0.1U/10V
Ivcc (External GFX 1.310 A,
integrate 1.572 A)
Layout Note:
370 mils from edge.
12
+
12
C231
*I@0.1U/10V
C705
*I@330U/6.3V
R187
E@0_0603
Layout Note:
370 mils from edge.
12
C222
*I@0.47U/10V
current(A)
( 1.3A for
1.573
external
GFX )
for integrated
7.7
Gfx
0.2
0.85
1.2
0.54
0.25
FSB VCCP
for PCIEG
for IAMT
function
DMI
12.313SUM
12
12
C212
0.1U/10V
C196
0.22U/10V
12
C220
*I@1U/10V
Remark
12
VCCP
12
+
+VGFX_CORE
C235
0.22U/10V
3
C507
220U/2.5V
12
C250
*I@10U/6.3V
Ivcc_AXM
Controller
supply
current
540mA
12
C327
0.47U/10V
3
VCCP
VCC3
R125 10
1 2
12
Layout Note:
Inside GMCH cavity.
12
12
C278
22U/4V
C227
*I@22U/4V
C276
0.22U/10V
for IAMT power if not
support need to
connection to S0 power
12
C316
0.1U/10V
12
C674
22U/4V
Layout Note:
Place close to GMCH edge.
12
12
C349
C388
1U/10V
1U/10V
+VCC_GMCH_L
12
C273
0.22U/10V
A test check
when use
external VGA can
remove or not..
andrew
Layout Note:
Inside GMCH
cavity.
12
C322
0.1U/10V
12
C321
0.22U/10V
2
D5
21
CH751H-40HPT
12
C333
0.1U/10V
12
C279
0.1U/10V
12
C303
0.22U/10V
1.8VSUS
12
C293
0.1U/10V
Layout Note:
Place C293 where LVDS
and DDR2 taps.
2
1
U25F
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
VCC_NCTF_3
AC33
VCC_NCTF_4
AC35
VCC_NCTF_5
AC36
VCC_NCTF_6
AD35
VCC_NCTF_7
AD36
VCC_NCTF_8
AF33
VCC_NCTF_9
AF36
VCC_NCTF_10
AH33
VCC_NCTF_11
AH35
VCC_NCTF_12
AH36
VCC_NCTF_13
AH37
VCC_NCTF_14
AJ33
VCC_NCTF_15
AJ35
VCC_NCTF_16
AK33
VCC_NCTF_17
AK35
VCC_NCTF_18
AK36
VCC_NCTF_19
AK37
VCC_NCTF_20
AD33
VCC_NCTF_21
AJ36
VCC_NCTF_22
AM35
VCC_NCTF_23
AL33
VCC_NCTF_24
AL35
VCC_NCTF_25
AA33
VCC_NCTF_26
AA35
VCC_NCTF_27
AA36
VCC_NCTF_28
AP35
VCC_NCTF_29
AP36
VCC_NCTF_30
AR35
VCC_NCTF_31
AR36
VCC_NCTF_32
Y32
VCC_NCTF_33
Y33
VCC_NCTF_34
Y35
VCC_NCTF_35
Y36
VCC_NCTF_36
Y37
VCC_NCTF_37
T30
VCC_NCTF_38
T34
VCC_NCTF_39
T35
VCC_NCTF_40
U29
VCC_NCTF_41
U31
VCC_NCTF_42
U32
VCC_NCTF_43
U33
VCC_NCTF_44
U35
VCC_NCTF_45
U36
VCC_NCTF_46
V32
VCC_NCTF_47
V33
VCC_NCTF_48
V36
VCC_NCTF_49
V37
VCC_NCTF_50
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
12
+
C733
330U/6.3V
Size Document Number Rev
Date: Sheet
VCC NCTF
POWER
12
Layout Note:
Place on the edge.
NB
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS NCTF
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
VCC AXM NCTF
1.8VSUS
12
C263
C302
22U/4V
22U/4V
PROJECT : CH3
Quanta Computer Inc.
1
08
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
846Tuesday, February 06, 2007
VCCP
1A
of
5
hexainf@hotmail.com
I&E Dis/Enable setting
R160 *I@0
VCC3
<FAE>
INT VGA disable VCCSYNC
connect to GND
12
12
R195 *I@0.03/F
12
+
12
+
12
C240
*I@22N
12
C213
*I@22N
12
*I@22N
L20
1 2
*I@BLM18PG181SN1
12
80mA
+1.25V_VCCA_DPLLA
12
C400
C707
470U/4V
0.1U/10V
80mA
+1.25V_VCCA_DPLLB
12
C703
C243
470U/4V
0.1U/10V
R173 E@0
R481 E@0
R482 E@0C225
VCC1.5
FB_180ohm+-25%_
100mHz_1500mA_
0.09ohm DC
D D
VCC1.25
R642
0
L55
+1.25V_VCCA_HPLL
12
BLM11A121S
12
C164
L54
BLM11A121S
12
R473 0.5 /F
C174
22U/10V
VCC3
22nF & 0.1uF for
VCC_TVDACA:C_R should be
placed with in 250 mils
from Crestline.
22U/10V
+1.25V_VCCA _MPLL
L21
1 2
*I@BLM18PG181SN1
+VCCA_MPLL_L
C C
B B
A A
1 2
12
50mA
12
C671
0.1U/10V
400mA
VCC1.25
0.1Caps should be
placed 200 mils
12
with in its pins.
C676
0.1U/10V
+3V_TV_DAC
12
C217
*I@10U
Update all 22nF CAP to 2pin
nicole 12/01
VCC3
Add the 100uF CAP for BenQ requirement.
SG Tie 061010
+3V_TV_DAC
L38
10uH/100MA
10uH+-20%_100mA
L22
10uH/100MA
12
C233
*I@.1U
12
C691
*I@.1U
12
C692
*I@.1U
+3V_VCCSYNC
C232
*I@.1U
C680
100U/6.3V_3528
12
40mA
L30
1 2
*I@BLM18PG181SN1
C292
*I@.1U
40mA
40mA
4
+
12
R147
E@0
C334
0.1U/10V
3
30mA
80mA
R216
E@0
+3V_VCCA_CRT_DAC
R126
E@0
Update this net name
nicole 9/25
+1.8VSUS_VCC _TX_LVDS
+VCC_TVBG
12
12
C207
C182
*I@.1U
*I@22N
12
C314
*I@22N
10mA
12
12
C252
22U/4V
200mA
C270
1U/10V
R507 E@0
100mA
640mA
12
12
C269
1U/10V
R197 E@0
R205 *I@0
12
C679
0.1U/10V
+1.8V_VCCD_LVDS
C310
*I@1U
L59
1 2
BLM21PG221SN1D
Add for BenQ request
nicole 10/23
+1.25V_VCCD_PEG_PLL
C228
22U/4V
12
C754
0.1U/10V
VCC3
12
C311
0.1U/10V
VCC1.25
R151 0
12
VCC1.25
C757
+
100U/6.3V
VCC1.5
C245
4.7U/6.3V
1 2
12
C262
22U/4V
60mA
+VCCA_MPLL_L
250mA
120mA
12
C324
22N
12
12
C347
C350
*I@22N
*I@.1U
1.8VSUS
R219 *I@0
R254
E@0
VCC1.25
CRT/TV Disable/Enable guideline
External VGA with E@part,Internal VGA with I@ part
Enable
3.3V
1.5V
1.5V
3.3V
3.3V
Disable
GND VCCA_TVC_DAC
GND
GND VCCA_DAC_BG
GND
GND
POWER
D TV/CRTLVDS
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
+1.25V_VCCA_HPLL
+1.25V_VCCA _MPLL
C696
*I@1000P
100mA
+1.25V_VCCA_SM
12
C255
1U/10V
12
C253
0.1U/10V
+1.5V_VCCD_CRT
+VCCQ_TVDAC
+VCCA_MPLL_L
+1.25V_VCCD_PEG_PLL
Ball
VCCA_CRT_DAC
VCCD_CRT
U25H
J32
VCCSYNC
A33
VCCA_CRT_DAC_1
B33
VCCA_CRT_DAC_2
A30
VCCA_DAC_BG
B32
VSSA_DAC_BG
B49
VCCA_DPLLA
H49
VCCA_DPLLB
AL2
VCCA_HPLL
AM2
VCCA_MPLL
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
U51
VCCA_PEG_PLL
AW18
VCCA_SM_1
AV19
VCCA_SM_2
AU19
VCCA_SM_3
AU18
VCCA_SM_4
AU17
VCCA_SM_5
AT22
VCCA_SM_7
AT21
VCCA_SM_8
AT19
VCCA_SM_9
AT18
VCCA_SM_10
AT17
VCCA_SM_11
AR17
VCCA_SM_NCTF_1
AR16
VCCA_SM_NCTF_2
BC29
VCCA_SM_CK_1
BB29
VCCA_SM_CK_2
C25
VCCA_TVA_DAC_1
B25
VCCA_TVA_DAC_2
C27
VCCA_TVB_DAC_1
B27
VCCA_TVB_DAC_2
B28
VCCA_TVC_DAC_1
A28
VCCA_TVC_DAC_2
M32
VCCD_CRT
L29
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41
VCCD_LVDS_1
H42
VCCD_LVDS_2
150mA
+VTTLF1
+VTTLF2
C329
*I@10U
100mA
R236
E@0
+
C759
220U
+VTTLF3
+1.25V_VCCD_PEG_PLL
12
R517
1/F/0603
12
C753
10U/6.3V
12
C755
0.1U/10V
CRTPLLA PEGA SMTV
A CK A LVDS
12
C673
0.47U/10V
Ball
VCCD_TVDAC
VSS_DAC_BG
VCCSYNC
AXD
VCC_AXD_NCTF
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
PEG
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
CRESTLINE_1p0
12
C683
0.47U/10V
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_DMI
VCC_HV_1
VCC_HV_2
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VTTLF1
VTTLF2
VTTLF3
VTTLF
Enable
3.3V
1.5V
3.3VVCCD_QDAC
GNDVCCA_TVA_DAC
3.3VVCCA_TVB_DAC
12
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
C678
0.47U/10V
Disable
+3V_VCC_HV
+VCC_RXR_DMI
+VTTLF1
+VTTLF2
+VTTLF3
GND
1.5V
GND
GND
GND
12
C202
2.2U/6.3V
Place on the edge.
12
C259
0.47U/6.3V
Place on the edge.
+1.25V_AXD
12
C242
1U/10V
+1.25V_VCC_AXF
+1.25V_VCC_DMI
+1.25V_VCC_DMI
+1.8VSUS_VCC_SM_CK
200mA
+1.8VSUS_VCC _TX_LVDS
100mA
12
C360
0.1U/10V
2
LVDS Disable/Enable guideline
External VGA with E@part,Internal VGA with I@ part
12
C300
4.7U/10V
12
C675
4.7U/10V
1 2
12
C246
22U/10V
12
R506
E@0
+VCC_PEG
12
+
C746
220U/4V
12
+
C760
220U/4V
12
Signal
VCCD_LVDS
VCCA_LVDS
VCC_TX_LVDS
Ivcc_VTT FSB
supply
current
0.85A
VCCP
12
+
C677
220U/4V
520mA
L23 0
Place caps close
to VCC_AXD.
100mA
R518 0
C742
0.1U/10V
+1.8VSUS_VCC _TX_LVDS
100mA
12
C695
*I@1000P
L61
12
91nH/1.5A
91uH+-20%_1.5A
12
C743
10U/6.3V
L35
12
91nH/1.5A
91uH+-20%_1.5A
12
C483
10U/6.3V
+1.8VSUS_VCC_SM_CK
12
C711
C287
22U/10V
0.1U/10V
If SDVO Disable
LVDS Disable
GND
GND
GND
VCC1.25
VCC1.25
L56 *I@1UH
12
12
1uH+-20%_300mA
+
C698
*I@220U
I&E Dis/Enable setting
VCCP
Ivcc_PEG
supply current
1.25A
VCCP
Ivcc_RX_DMI
supply current
260mA
L57 1uH/30 0mA
12
1uH+-20%_300mA
R221
1/F/0603
+VCC_SM_CK_L
12
C297
10U/6.3V
12
If LVDS
enable
1.8V
1.8V
1.8V
1.8VSUS
D8
CH751H-40HPT_NC
+3V_VCC_HV
R244 0
500mA
+1.25V_VCC_AXF
12
C699
1U/10V
Place caps close
to VCC_AXF
VCC1.25
1.8VSUS
VCCP
21
12
12
R273
10
VCC3
R508
0
C701
10U/6.3V
1
09
40 mil
Size Document Number Rev
5
4
3
2
Date: Sheet
PROJECT : CH3
Quanta Computer Inc.
NB
1
946Tuesday, Fe b r u ary 06, 2007
1A
of
5
4
3
2
1
U25I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
D D
C C
B B
A A
5
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
AL1
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CRESTLINE_1p0
VSS
4
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
3
U25J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRESTLINE_1p0
VSS
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
1
10
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10 46Tuesday, February 06, 2007
1A
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
Size Document Number Rev
NB
2
Date: Sheet
PROJECT : CH3
Quanta Computer Inc.
Strap table
hexainf@hotmail.com
5
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin
Pin Name Strap description
D D
CFG[2:0]
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
CFG[11:10]
C C
CFG[13:12]
CFG[15:14]
CFG16
CFG[18:17]
SDVO_CTRLDATA
CFG19
CFG20
B B
DMI X2 Select
MCH_CFG_5 Low = DMIX2
MCH_CFG_56
High = IDMIX4(D efault)
R155
*4.02K/F
FSB Dynamic ODT
MCH_CFG_16 Low = OD T Dis able
A A
MCH_CFG_166
High = ODT Enable(D efault)
R156
*4.02K/F
5
FSB Frequency Select
Reserved
DMI X2 Select
Reserved
CPU Strap
Low power PCI Express
PCI Express Graphics Lane Reversal
Reserved
XOR/ALLZ
Reserved
FSB Dynamic ODT
Reserved
SDVO Present
DMI Lane Reversal
SDVO/PCIe concurrent
DMI Lane Reversal
MCH_CFG_19 Lo w = No rm a l operation(D efault)
MCH_CFG_196
SDVO/PCIE Concurrent operation
MCH_CFG_20
MCH_CFG_206
4
High = Reverse Lane
VCC3
R172
*4.02K/F
Low = Only SDVO or PCIE X1 is
operational(Default)
High = SDVO andPCIE X1 are operating
simultaneously via the PEG port
VCC3
R245
*4.02K/F
4
3
2
Configuration
010 = FSB 800MHz
011 = FSB 667MHz
0 = DMI X2
1 = DMI X4(Default)
0 = Reserved
1 = Mobile CPU(Default)
0 = Normal mode
1 = Low Power mode
0 = Reverse Lanes
1 = Normal operation(Default)
00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = No SDVO Card present(Default)
1 = SDVO Card Present
0 = Normal operation(Default)
1 = Reverse Lanes
0 = Only SDVO or PCIE x1 is operation(Default)
1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
XOR /ALLz /Clock Un-gating
MCH_CFG_12MCH_CFG_13 Configuration
0
0
1
1
MCH_CFG_126
MCH_CFG_136
0
1
0
1
Clock gating disable
XOR Mode Enable
ALL-z Mode Enable
Normal operation(Default)
R190
*4.02K/F
3
R157
*4.02K/F
PCI Express Graphics
MCH_CFG_9 Low = Reverse Lane
High = Normal operation(Default)
MCH_CFG_96
2
1
11
SDVO Present
Strap define at External
DVI control page
R174
*4.02K/F
Size Document Number Re v
NB
Date: Sheet
PROJECT : CH3
Quanta Computer Inc.
11 46Tuesday, February 06, 2007
1
of
1A
1
2
3
4
5
6
7
8
DDRII DUAL CHANNEL A,B
A A
M_B_A[13..0]
M_B_A[13..0] 7,13
12
DDRII A CHANNEL
M_A_A[13..0]
SMDDR_VTERM
SMDDR_VTERM
C126
C179
C188
.1U/10V
B B
M_A_ODT06,13
M_A_CKE16,13
M_A_BS#07,13
M_A_RAS#7,13
M_A_BS#17,13
C C
M_A_WE#7,13
M_A_CAS#7,13
.1U/10V
C161
.1U/10V
M_A_ODT0
M_A_A13
M_A_A8
M_A_A5
M_A_A3
M_A_A1
M_A_CKE1
M_A_A11
M_A_A10
M_A_BS#0
M_A_A7
M_A_A6
M_A_A2
M_A_A4
M_A_BS#1
M_A_A9
M_A_A12
C120
.1U/10V
.1U/10V
RP7 56X2
RP23 56X2
RP19 56X2
RP28 56X2
RP14 56X2
RP25 56X2
RP20 56X2
RP15 56X2
RP27 56X2
RP10 56X2
C128
.1U/10V
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
C152
.1U/10V
M_A_A[13..0] 7,13
C138
.1U/10V
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
C137
.1U/10V
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C117
.1U/10V
C136
.1U/10V
C123
.1U/10V
C111
.1U/10V
SMDDR_VTERM
C206
.1U/10V
DDRII B CHANNEL
C189
.1U/10V
C142
.1U/10V
C216
.1U/10V
C139
.1U/10V
C127
.1U/10V
C121
.1U/10V
C194
.1U/10V
C129
.1U/10V
C178
.1U/10V
C165
.1U/10V
C124
.1U/10V
C223
.1U/10V
Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM
RP17 56X2
M_B_BS#17,13
M_B_BS#27,13
M_B_CKE06,13
M_B_RAS#7,13
M_B_CS#06,13
M_B_BS#07,13
M_B_CAS#7,13
M_B_WE#7,13
M_B_A0
M_B_A5
M_B_A1
M_B_A8
M_B_A3
M_B_A4
M_B_A2
M_B_A12
M_B_A9
M_B_A7
M_B_A6
M_B_A10
1
3
RP21 56X2
1
3
RP24 56X2
1
3
RP18 56X2
1
3
RP26 56X2
1
3
RP22 56X2
1
3
RP31 56X2
1
3
RP13 56X2
1
3
RP12 56X2
1
3
RP16 56X2
1
3
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
RP11 56X2
M_A_CS#06,13
M_B_ODT06,13
M_B_ODT16,13
M_B_CS#16,13
M_A_CS#16,13
M_A_ODT16,13
M_B_CKE16,13
M_A_CKE06,13
M_A_BS#27,13
D D
1
2
3
4
5
M_A_A0
M_B_A13
M_ODT3
M_ODT1
M_B_A11
6
1
3
RP9 56X2
1
3
RP8 56X2
1
3
RP6 56X2
1
3
RP29 56X2
1
3
RP30 56X2
1
3
Size Document Number R ev
Date: Sheet
DDR2
2
4
2
4
2
4
2
4
2
4
2
4
SMDDR_VTERM
PROJECT : CH3
Quanta Computer Inc.
7
1A
of
12 46Tuesday, February 06, 2007
8
5
hexainf@hotmail.com
SMDDR_VREF_DIMM
1.8VSUS
CN17
1
VREF
3
M_A_DQ6
M_A_DQ5
M_A_DQS#0
M_A_DQS0
D D
M_A_CKE06,12
C C
M_A_BS#27,12
M_A_BS#07,12
M_A_WE#7,12
M_A_CAS#7,12
M_A_CS#16,12
M_A_ODT16,12
B B
R47 0
VCC3
M_A_DQ2
M_A_DQ3
M_A_DQ12
M_A_DQ8
M_A_DQS#1
M_A_DQS1
M_A_DQ11
M_A_DQ15
M_A_DQ20
M_A_DQS#2
M_A_DQS2
M_A_DQ23
M_A_DQ19
M_A_DQ24
M_A_DQ25
M_A_DQM3
M_A_DQ26
M_A_DQ27
M_A_A12
M_A_A9
M_A_A8
M_A_A5
M_A_A3
M_A_A1
M_A_A10
M_A_DQ36
M_A_DQS#4
M_A_DQS4
M_A_DQ39
M_A_DQ34
M_A_DQ40
M_A_DQ41
M_A_DQM5
M_A_DQ42
M_A_DQ46
M_A_DQ53
M_A_DQ49
M_A_DQS#6
M_A_DQS6
M_A_DQ50
M_A_DQ56
M_A_DQ60
M_A_DQM7
M_A_DQ62
PDAT_SMB
PCLK_SMB
VCC3_SPD
CLOCKA 0,1 CLOCKB 0,1
A A
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
DDR2_SODIMM
CKEA 0,1 CKEB 0,1
2
VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
PC4800 DDR2 SDRAM
SO-DIMM (200P)
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
H 4.0 H 8.0
M_A_DQ4
4
M_A_DQ0
6
8
M_A_DQM0
10
12
M_A_DQ7
14
M_A_DQ1
16
18
M_A_DQ13
20
M_A_DQ9
22
24
M_A_DQM1
26
28
30
32
34
M_A_DQ14
36
M_A_DQ10
38
40
42
M_A_DQ21M_A_DQ17
44
M_A_DQ16
46
48
50
M_A_DQM2
52
54
M_A_DQ18
56
M_A_DQ22
58
60
M_A_DQ29
62
M_A_DQ28
64
66
M_A_DQS#3
68
M_A_DQS3
70
72
M_A_DQ30
74
M_A_DQ31
76
78
80
82
84
86
88
M_A_A11
90
M_A_A7
92
M_A_A6
94
96
M_A_A4
98
M_A_A2
100
M_A_A0
102
104
106
108
110
112
114
M_A_A13
116
118
120
122
M_A_DQ32
124
M_A_DQ33M_A_DQ37
126
128
M_A_DQM4
130
132
M_A_DQ35
134
M_A_DQ38
136
138
M_A_DQ44
140
M_A_DQ45
142
144
M_A_DQS#5
146
M_A_DQS5
148
150
M_A_DQ43
152
M_A_DQ47
154
156
M_A_DQ48
158
M_A_DQ52
160
162
164
166
168
M_A_DQM6
170
172
M_A_DQ54
174
M_A_DQ55M_A_DQ51
176
178
M_A_DQ61
180
M_A_DQ57
182
184
M_A_DQS#7
186
M_A_DQS7
188
190
M_A_DQ58M_A_DQ59
192
M_A_DQ63
194
196
R41 10K
198
R35 10K
200
SO-DIMM0 SPD Address is 0xA0
SO-DIMM0 TS Address is 0x30
4
M_A_CLK0 6
M_A_CLK0# 6
PM_EXTTS#0 6
M_A_CKE1 6,12
SA_MA14 6
M_A_BS#1 7,12
M_A_RAS# 7,12
M_A_CS#0 6,12
M_A_ODT0 6,12
M_A_CLK1 6
M_A_CLK1# 6
M_A_DQ[0..63] 7
M_A_DQS[0..7] 7
M_A_DQS#[0..7] 7
M_A_A[0..13] 7,12
M_B_CKE06,12
M_B_BS#27,12
M_B_BS#07,12
M_B_WE#7,12
M_B_CAS#7,12
M_B_CS#16,12
M_B_ODT16,12
PDAT_SMB2,22,28,31
PCLK_SMB2,22,28,31
M_B_DQ0
M_B_DQ5
M_B_DQS#0
M_B_DQS0
M_B_DQ7
M_B_DQ3
M_B_DQ9
M_B_DQ8
M_B_DQS#1
M_B_DQS1
M_B_DQ11
M_B_DQ10
M_B_DQ20
M_B_DQ17
M_B_DQS#2
M_B_DQS2
M_B_DQ22
M_B_DQ23
M_B_DQ29
M_B_DQ28
M_B_DQM3
M_B_DQ26
M_B_DQ27
M_B_A12
M_B_A9
M_B_A8
M_B_A5
M_B_A3
M_B_A1
M_B_A10
M_B_DQ37
M_B_DQ38
M_B_DQS#4
M_B_DQS4
M_B_DQ34
M_B_DQ35
M_B_DQ40
M_B_DQ41
M_B_DQM5
M_B_DQ46
M_B_DQ43
M_B_DQ53
M_B_DQ49
M_B_DQS#6
M_B_DQS6
M_B_DQ51
M_B_DQ54
M_B_DQ56
M_B_DQ61
M_B_DQM7
M_B_DQ59
M_B_DQ62
PDAT_SMB
PCLK_SMB
VCC3_SPD
3
SMDDR_VREF_DIMM
CN18
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
2-1734073-2
VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
PC4800 DDR2 SDRAM
SO-DIMM (200P)
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
1.8VSUS1.8VSUS 1.8VSUS
2
M_B_DQ4
4
M_B_DQ1
6
8
M_B_DQM0
10
12
M_B_DQ2
14
M_B_DQ6
16
18
M_B_DQ12
20
M_B_DQ13
22
24
M_B_DQM1
26
28
30
32
34
M_B_DQ14
36
M_B_DQ15
38
40
42
M_B_DQ16
44
M_B_DQ21
46
48
50
M_B_DQM2
52
54
M_B_DQ18
56
M_B_DQ19
58
60
M_B_DQ24
62
M_B_DQ25
64
66
M_B_DQS#3
68
M_B_DQS3
70
72
M_B_DQ31
74
M_B_DQ30
76
78
80
82
84
86
88
M_B_A11
90
M_B_A7
92
M_B_A6
94
96
M_B_A4
98
M_B_A2
100
M_B_A0
102
104
106
108
110
112
114
M_B_A13
116
118
120
122
M_B_DQ36
124
M_B_DQ32
126
128
M_B_DQM4
130
132
M_B_DQ39
134
M_B_DQ33
136
138
M_B_DQ44
140
M_B_DQ45
142
144
M_B_DQS#5
146
M_B_DQS5
148
150
M_B_DQ42
152
M_B_DQ47
154
156
M_B_DQ52
158
M_B_DQ48
160
162
164
166
168
M_B_DQM6
170
172
M_B_DQ55
174
M_B_DQ50
176
178
M_B_DQ60
180
M_B_DQ57
182
184
M_B_DQS#7
186
M_B_DQS7
188
190
M_B_DQ63
192
M_B_DQ58
194
196
R39 10K
198
R44 10K
200
VCC3_SPD
SO-DIMM1 SPD Address is 0xA4
SO-DIMM1 TS Address is 0x34
M_B_CLK0 6
M_B_CLK0# 6
PM_EXTTS#1 6
M_B_CKE1 6,12
SB_MA14 6
M_B_BS#1 7,12
M_B_RAS# 7,12
M_B_CS#0 6,12
M_B_ODT0 6,12
M_B_CLK1 6
M_B_CLK1# 6
2
M_B_DQM[0..7 ] 7M_A_DQM[0..7] 7
M_B_DQ[0..63] 7
M_B_DQS[0..7] 7
M_B_DQS#[0..7] 7
M_B_A[0..13] 7,12
1.8VSUS
SMDDR_VREF_DIMM
1.8VSUS
C130
2.2U/6.3V
SMDDR_VREF_DIMM
C307 470P/50V
SMDDR_VREF_DIMM
1 2
R256
R235 *10K/F
*10K/F
Place these Caps near So-Dimm2.
C201
2.2U/6.3V
C373
.1U/10V
C147
2.2U/6.3V
C392
2.2U/6.3V
C172
2.2U/6.3V
C198
2.2U/6.3V
VCC3
C46
2.2U/6.3V
C131
2.2U/6.3V
C140
.1U/10V
C49
.1U/10V
Place these Caps near So-Dimm1.
C190
2.2U/6.3V
C361
2.2U/6.3V
C162
2.2U/6.3V
VCC3
C200
2.2U/6.3V
C45
2.2U/6.3V
C180
.1U/10V
C48
.1U/10V
C382
.1U/10V
C175
2.2U/6.3V
1
13
R248 0
C153
.1U/10V
SO-DIMM BYPASS PLACEMENT :
Place these Caps near So-Dimm2
No Vias Between the Trace of PIN to CAP.
C145
.1U/10V
SO-DIMM BYPASS PLACEMENT :
Place these Caps near So-Dimm1.
No Vias Between the Trace of PIN to CAP.
1.8VSUS
C146
.1U/10V
C141
.1U/10V
SMDDR_VREF
C181
C167
.1U/10V
.1U/10V
C149
.1U/10V
C166
.1U/10V
C187
.1U/10V
C199
.1U/10V
Size Doc ument Number Rev
DDR2
5
4
3
2
Date: Sheet
PROJECT : CH3
Quanta Computer Inc.
of
13 46Tuesday, February 06, 2007
1
1A
U27F
AA12
GND_0
AA2
GND_1
AA21
GND_2
AA31
GND_3
AB27
GND_4
AB6
GND_5
AC10
GND_6
AC23
GND_7
AC29
GND_8
AC4
GND_9
AD16
GND_10
AD17
GND_11
AD2
AD31
AE17
AE27
AF11
AF26
AF29
AG10
AG11
AG14
AG15
AG19
AG2
AG22
AG31
AG8
AH24
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ26
AJ29
AK28
AK31
AL11
AL14
AL19
AL22
AL25
AM13
AM16
AM17
AM20
AM23
AM26
AM29
AE6
AF4
AF7
AJ4
AJ7
AK2
AL3
AL6
AL9
B12
B15
B18
B21
B24
B27
B3
B30
B6
B9
C2
C31
D10
D13
D16
D17
D20
D23
D26
D29
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
E@U_GPU_G3
D D
C C
B B
A A
5
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
5
D4
D7
F11
F14
F19
F2
F22
F25
F31
F8
G26
G29
G4
G7
H27
H6
J16
J17
J2
J31
K10
K23
K29
K4
L27
L6
M12
M2
M31
N15
N18
N29
N4
P15
P18
P27
P6
R13
R14
R15
R18
R19
R2
R20
R31
T16
T17
T24
T29
T4
U16
U17
U24
U29
U8
V13
V14
V15
V18
V19
V2
V20
V31
W15
W18
W27
W6
Y15
Y18
Y29
Y4
AL10
AM10
AG13
PLT_RST-R#6,21
PLT_RST-R#
PEG_RXP06
PEG_RXN06
PEG_RXP16
PEG_RXN16
PEG_RXP26
PEG_RXN26
PEG_RXP36
PEG_RXN36
PEG_RXP46
PEG_RXN46
PEG_RXP56
PEG_RXN56
PEG_RXP66
PEG_RXN66
PEG_RXP76
PEG_RXN76
PEG_RXP86
PEG_RXN86
PEG_RXP96
PEG_RXN96
PEG_RXP106
PEG_RXN106
PEG_RXP116
PEG_RXN116
PEG_RXP126
PEG_RXN126
PEG_RXP136
PEG_RXN136
PEG_RXP146
PEG_RXN146
PEG_RXP156
PEG_RXN156
PEG_TXP_C06
PEG_TXN_C06
PEG_TXP_C16
PEG_TXN_C16
PEG_TXP_C26
PEG_TXN_C26
PEG_TXP_C36
PEG_TXN_C36
PEG_TXP_C46
PEG_TXN_C46
PEG_TXP_C56
PEG_TXN_C56
PEG_TXP_C66
PEG_TXN_C66
PEG_TXP_C76
PEG_TXN_C76
PEG_TXP_C86
PEG_TXN_C86
PEG_TXP_C96
PEG_TXN_C96
PEG_TXP_C106
PEG_TXN_C106
PEG_TXP_C116
PEG_TXN_C116
PEG_TXP_C126
PEG_TXN_C126
PEG_TXP_C136
PEG_TXN_C136
PEG_TXP_C146
PEG_TXN_C146
PEG_TXP_C156
PEG_TXN_C156
CLK_PCIE_VGA2
CLK_PCIE_VGA#2
R230 E@0
del 10K pull_down resistor per FAE
nicole 10/9
4
T70
T181
T179
C_PEG_RXP0PEG_RXP0
C_PEG_RXP1
C_PEG_RXP2PEG_RXP2
C_PEG_RXP3PEG_RXP3
C_PEG_RXN3PEG_RXN3
C_PEG_RXP4
C_PEG_RXP5PEG_RXP5
C_PEG_RXN5PEG_RXN5
C_PEG_RXP6
C_PEG_RXN6PEG_RXN6
C_PEG_RXP7PEG_RXP7
C_PEG_RXN7PEG_RXN7
C_PEG_RXP8
C_PEG_RXN8
C_PEG_RXP9
C_PEG_RXN9
C_PEG_RXP10PEG_RXP10
C_PEG_RXN10
C_PEG_RXP11
C_PEG_RXN11PEG_RXN11
C_PEG_RXP13PEG_RXP13
C_PEG_RXN13PEG_RXN13
C_PEG_RXP14
C_PEG_RXP15
C_PEG_RXN15
VGA_RFU0
VGA_RFU1
PEX_TSTCK
PEX_TSTCK#
C342 E@.1U/10V
PEG_RXN0 C_PEG_RXN0
C351 E@.1U/10V
PEG_RXP1
C368 E@.1U/10V
PEG_RXN1 C_PEG_RXN1
C357 E@.1U/10V
C369 E@.1U/10V
PEG_RXN2 C_PEG_RXN2
C381 E@.1U/10V
C386 E@.1U/10V
C396 E@.1U/10V C380 E@.1U/10V
PEG_RXP4
C403 E@.1U/10V
PEG_RXN4 C_PEG_RXN4
C398 E@.1U/10V C364 E@.47U/10V
C415 E@.1U/10V
C405 E@.1U/10V
PEG_RXP6
C425 E@.1U/10V
C418 E@.1U/10V
C435 E@.1U/10V
C427 E@.1U/10V
PEG_RXP8
C437 E@.1U/10V
PEG_RXN8
C444 E@.1U/10V
PEG_RXP9
C446 E@.1U/10V
PEG_RXN9
C451 E@.1U/10V
C455 E@.1U/10V
PEG_RXN10
C453 E@.1U/10V
PEG_RXP11
C457 E@.1U/10V
C461 E@.1U/10V
PEG_RXP12 C_PEG_RXP12
C465 E@.1U/10V
PEG_RXN12 C_PEG_RXN12
C475 E@.1U/10V
C478 E@.1U/10V
C482 E@.1U/10V
PEG_RXP14
C487 E@.1U/10V
PEG_RXN14 C_PEG_RXN14
C484 E@.1U/10V
PEG_RXP15
C496 E@.1U/10V
PEG_RXN15
C488 E@.1U/10V
PEG_TXP_C0
PEG_TXN_C0
PEG_TXP_C1
PEG_TXN_C1
PEG_TXP_C2
PEG_TXN_C2
PEG_TXP_C3
PEG_TXN_C3
PEG_TXP_C4
PEG_TXN_C4
PEG_TXP_C5
PEG_TXN_C5
PEG_TXP_C6
PEG_TXN_C6
PEG_TXP_C7
PEG_TXN_C7
PEG_TXP_C8
PEG_TXN_C8
PEG_TXP_C9
PEG_TXN_C9
PEG_TXP_C10
PEG_TXN_C10
PEG_TXP_C11
PEG_TXN_C11
PEG_TXP_C12
PEG_TXN_C12
PEG_TXP_C13
PEG_TXN_C13
PEG_TXP_C14
PEG_TXN_C14
PEG_TXP_C15
PEG_TXN_C15
CLK_PCIE_VGA
CLK_PCIE_VGA#
VGA_RST#
4
AJ15
PEX_TX0
AK15
PEX_TX0#
AH16
PEX_TX1
AG16
PEX_TX1#
AG17
PEX_TX2
AH17
PEX_TX2#
AG18
PEX_TX3
AH18
PEX_TX3#
AK18
PEX_TX4
AJ18
PEX_TX4#
AJ19
PEX_TX5
AH19
PEX_TX5#
AG20
PEX_TX6
AH20
PEX_TX6#
AG21
PEX_TX7
AH21
PEX_TX7#
AK21
PEX_TX8
AJ21
PEX_TX8#
AJ22
PEX_TX9
AH22
PEX_TX9#
AG23
PEX_TX10
AH23
PEX_TX10#
AK24
PEX_TX11
AJ24
PEX_TX11#
AJ25
PEX_TX12
AH25
PEX_TX12#
AH26
PEX_TX13
AG26
PEX_TX13#
AK27
PEX_TX14
AJ27
PEX_TX14#
AJ28
PEX_TX15
AH27
PEX_TX15#
AK13
PEX_RX0
AK14
PEX_RX0#
AM14
PEX_RX1
AM15
PEX_RX1#
AL15
PEX_RX2
AL16
PEX_RX2#
AK16
PEX_RX3
AK17
PEX_RX3#
AL17
PEX_RX4
AL18
PEX_RX4#
AM18
PEX_RX5
AM19
PEX_RX5#
AK19
PEX_RX6
AK20
PEX_RX6#
AL20
PEX_RX7
AL21
PEX_RX7#
AM21
PEX_RX8
AM22
PEX_RX8#
AK22
PEX_RX9
AK23
PEX_RX9#
AL23
PEX_RX10
AL24
PEX_RX10#
AM24
PEX_RX11
AM25
PEX_RX11#
AK25
PEX_RX12
AK26
PEX_RX12#
AL26
PEX_RX13
AL27
PEX_RX13#
AM27
PEX_RX14
AM28
PEX_RX14#
AL28
PEX_RX15
AL29
PEX_RX15#
AH14
PEX_REFCLK
AJ14
PEX_REFCLK#
AH15
PEX_RST#
AG12
RFU0
AH13
RFU1
AM12
PEX_TSTCLK_OUT
AM11
PEX_TSTCLK_OUT#
E@U_GPU_G3
U27A
3
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3
VDD_LP_4
VDD_LP_5
VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_12
AD23
C372 E@.1U/10V
AF23
C434 E@.1U/10V
AF24
C416 E@1U/6.3V
AF25
C438 E@1U/6.3V
AG24
C428 E@4.7U/10V
AG25
AC16
AC17
AC21
C420 E@.1U/10V
AC22
C417 E@0.47U/10V
AE18
AE21
C378 E@1U/6.3V
AE22
C397 E@1U/6.3V
AF12
C404 E@10U/4V
AF18
C374 E@.1U/10V
AF21
C441 E@.1U/10V
AF22
K16
K17
C358 E@.1U/10V
N13
C384 E@.1U/10V
N14
C389 E@.1U/10V
N16
C383 E@.1U/10V
N17
C366 E@.1U/10V
N19
C338 E@10U/4V
P13
C362 E@.1U/10V
P14
C370 E@1U/6.3V
P16
C390 E@.1U/10V
P17
C371 E@.1U/10V
P19
C402 E@.1U/10V
R16
C356 E@.1U/10V
R17
C363 E@10U/4V
T14
C385 E@.47U/10V
T15
C407 E@.47U/10V
T18
C411 E@.47U/10V
T19
C408 E@.47U/10V
U13
C346 E@1U/6.3V
U14
C337 E@1U/6.3V
U15
C410 E@.47U/10V
U18
C409 E@.47U/10V
U19
C323 E@.47U/10V
V16
C393 E@.47U/10V
V17
C406 E@.47U/10V
W13
C344 E@.47U/10V
W14
C348 E@10U/4V
W16
W17
W19
Y13
Y14
Y16
Y17
Y19
Y20
P20
T20
T23
U20
U23
W20
VDD_SENSE
N20
GND_SENSE
M21
AC11
AC12
C264 E@.1U/10V
AC24
C265 E@.1U/10V
AD24
C285 E@.1U/10V
AE11
C205 E@.47U/10V
AE12
C224 E@.47U/10V
H7
C288 E@.47U/10V
J7
C282 E@1U/10V
K7
L10
L7
L8
M10
15mil
PEX_PLLVDD
AF15
AE15
AE16
PCIE
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
VDD_SENSE
GND_SENSE
PEX_PLLAVDD
PEX_PLLDVDD
PEX_PLLGND
2
VGA1.2V
PLACE NEAR GPU
VGA1.2V
PLACE NEAR GPU
VGACORE_G73
PLACE NEAR GPU
T76
T78
VCC3
PLACE NEAR GPU
L31 E@10nH
C353 E@1U/6.3V
C355 E@.01U/16V
C352 E@.1U/10V
C339 E@4.7U/X5R
500mA
1500mA
19.81A
180mA
VGA1.2V
C387E@0.1U
20mA
E@CH501H
SPDIF_VGA
E@CH501H
1
G8X Total power consumption
1.NVDD CORE POWER 1.2 - 1.0
-- 11.01A
2.PCIE VGA1.2V -- 1.75A
3.FBVDDQ 1.8V ----- 3.12A
4.VDD I/O 3.3V ---- 0.49A
5.PLL 2.5V ---
power up sequence
I/O 3.3V
NVCORE
1.8VFBDDQ
1.2V
2.5V
VCC3
D7
D6
R169
*E@24.3K/F
C891 E@.01U
2 1
R185
*E@3.4K/F
2 1
R179
*E@76.8/F
no 76.8 in SAP, use 78.7 instead
for 3.3V swing
G73 use 0ohm, NB8P use 10nF
14
SPDIF 34
PLACE NEAR GPU
NV_PLLAVDD
NC_0
NC_1
NC_2
T13
AM8
AM9
B32
NV_PLLAVDD
L27 *E@10nH
R238 E@0
VGACORE_G73
G72M/G73M: STUFF L27
VGA1.2V
15mil
NB8X: STUFF R238
SPDIF_VGA
J6
SPDIF
Size Document Number Rev
VGA
3
2
Date: Sheet
PROJECT : CH3
Quanta Computer Inc.
of
14 46Tuesday, February 06, 2007
1
1A
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