BenQ D72 Service Manual

BenQ Rev 1.0

1

BenQ March (D72)/Amethyst

LT Mobile Phone

Service Manual

BenQ Inc.

Wireless Business Unit

Customer Service Dep.
Tel : [phone] ext 6687
E-Mail : [e-mail]

BenQ Rev 1.0

2

Contents

l Preface…………………………………………………..……………1
l Theory of Operation

1.GSM system Description…………………………………………7

2.Baseband function description…………………………………12

3.Radio Frequency function description ………………………..44

l Download

1.System requirements and setup ………………………………59

2.Function descriptions……………………………………………61

3.FAQ… ……………….……………….……………………………67

l Disassembly (Level1~Level2)………….………………………….69
l Troubleshooting

Level 1~level 2 repair………………………………………………73
Level 3~level 4 repair………………………………………………74
l Replacement parts

Exploded View (fig1~fig3)………………………………………….95
Spare parts list………………………………………………….…..98

l Service Manual Feedback Form……..…………………………….99

BenQ Rev 1.0

3

Preface

This service manual is for the customers who purchase of Acer

March handset . It has several main parts of our handset that include
hardware/software and simple disassembly/assembly procedure
introduction. If you don’t understand some of these sections or any
query about it please kindly use our service manual feedback form and
send it back to our Customer Service Department and we’ll response
your query as soon as possible.

Specifications

Table 1: Radio Frequency

Radio Frequency (900 MHz)

Frequency Range TX 880-915 MHz; RX 925-

960

MHz
Channel Spacing 200 KHz
Number of Channels 174 Carriers x 8 (TDMA)
Modulation GMSK
Duplex Spacing 45 MHz
Frequency Stability +/- 0.1 ppm (Uplink TX)
Power Output 33 dBM Class 4 (2 W peak)
Receiver Level < -102 dBm (Wireless)

Radio Frequency (1800 MHz)

Frequency Range TX 1710-1785 MHz; RX

1805-1880 MHz
Channel Spacing 200 KHz
Number of Channels 374 Carriers x 8 (TDMA)
Modulation GMSK
Duplex Spacing 95 MHz
Frequency Stability +/- 0.1 ppm (Uplink TX)
Power Output 30 dBM – 0 dBM
Receiver Level < -102 dBm (Wireless)

Operating Temperature Range -10 to +55 °C

BenQ Rev 1.0

4

Table 2: Voltage Operation

Voltage Operation

Li-ion Battery DC 3.3-4.2 V
Ni-MH Battery DC 3.3-4.2 V

Table 3: Power Consumption

Power Consumption

Working Current Average < 270 mAH
Standby Current 6 +/-0.2 mAH
Talking Time* 120 ~300 min (With Ni-

MH 550

mAH)

Standby Time* 50~120 hours (With Ni-

MH 550

mAH)

DTX / DTR Yes

Table 4: Appearance

Handset Appearance

Dimensions 106 x 40 x 16 mm
Volume 68 c.c.
Handset Weight 99 g

Table 5: Basic Services

Telephony (Speech)

Tele Service

Emergency Call

Delivery Report

Short Message Service MT/MO

Short Message Service

Cell Broadcast

Bearer Service

Data circuit duplex

asynchronous up to 14400

bit/sec

BenQ Rev 1.0

5

Scope of Manual

This manual is intended for use by experienced technicians
familiar with similar types of equipment. It is intended primarily to
support electrical and mechanical repairs. Repairs not covered in the
scope of this manual should be forwarded to Motorola’s regional
Cellular Subscriber Support Centers.

BenQ Rev 1.0

7

Theory of Operation

△ GSM System Description

General Cellular Concept

The cellular systems are used to provide radiotelephone service in
the frequency range 890-960 MHz. A cellular system provides higher
call handling capacity and system availability than would be possible
with conventional radiotelephone systems (those which require total
system area coverage on every operating channel) by dividing the
system coverage area into several adjoining sub-areas or cells.

Each cell contains a base station (cell site) which provides
transmitting and receiving facilities, for an allocated set of duplex
frequency pairs (channels). Since each cell is a relatively small area,
both the cell site and the radiotelephone that it supports can operate at
lower power levels than would be used in conventional systems.

Using this technique, radiation on a given channel is virtually
contained in the cell operating on that channel and, to some extent,
those cells directly adjacent to that cell.

Since the coverage area of a cell on a given channel is limited to a
small area (relative to the total system coverage area), a channel may
be reused in another cell outside the coverage area of the first. By this
means, several subscribers may operate within the same geographic
area, without interference with each other, on a single channel.

GSM Description

Unlike previous cellular systems, GSM uses digital radio
techniques. The GSM system has the following advantages over
previous analogue systems:
♦International Roaming - Due to international harmonization and

standardization, it will be possible to make and receive calls in any

BenQ Rev 1.0

8

country which supports a GSM system.

♦Digital Air Interface - The GSM phone will provide an entirely digital
link between the telephone and the base station, which is, in turn,
digitally linked into the switching subsystems and on into the PSTN.

♦ISDN Compatibility - ISDN is a digital communications standard that
many countries are committed to implementing. It is designed to carry
digital voice and data over existing copper telephone cables. The GSM
phone will be able to offer similar features to the ISDN telephone.

♦Security and Confidentiality – Telephone calls on analogue systems
can very easily be overheard by the use of a suitable radio receiver.

GSM offers vastly improved confidentiality because of the way in which
data is digitally encrypted and transmitted.

♦Better Call Quality - Co-channel interference, handover breaks, and
fading will be dealt with more effectively in the digital system. The call
quality is also enhanced by error correction, which reconstructs lost
information.

♦Efficiency - The GSM system will be able to use spectral resources
in a much more efficient way than previous analogue

Systems

In the figure below, the area bounded by bold lines represents the
total coverage area of a hypothetical system. This area is divided into
several cells, each containing a cell site (base station) operating on a
given set of channels which interfaces radiotele- phone subscribers to
the telephone switching system.

BenQ Rev 1.0

9

The radiotelephones themselves are capable of operation on any
channel in the system, allowing them to operate in any cell. Due to the
low power requirements for communications between radiotelephones
in a particular cell and the cell site, operating channels may be
repeated in cells which are outside the coverage area of each other.

For example, presume that cell A operates on channels arbitrarily
numbered 1 through 8, cell B operates on channels 9 through 16, cell C
operates on channels 17 through 24 and cell D operates on channels 1
through 8 (repeating the usage of those channels used by cell A). In
this system, subscribers in cell A and subscribers in cell D could
simultaneously operate on channels 1 through 8.

The implementation of frequency re-use increases the call
handling capability of the system, without increasing the number of
available channels. When re-using identical frequencies in a small area,
co-channel interference can be a problem. The GSM system can
tolerate higher levels of co-channel interference than analogue systems,
by incorporating digital modulation, forward error correction and
equalization. This means that cells using identical frequencies can be

CELL A

CHANNELS

1-8

CELL B

CHANNELS

9-16

CELL C

CHANNELS

17-24

CELL D

CHANNELS

1-8

CELL F

CHANNELS

17-24

CELL E

CHANNELS

9-16

Figure 2: Hypothetical

BenQ Rev 1.0

10

physically closer, than similar cells in analogue systems. Therefore the
advantage of frequency re-use can be further enhanced in a GSM
system, allowing greater traffic handling in high use areas.

By incorporating Time Division Multiple Access (TDMA) several
calls can share the same carrier. The carrier is divided into a
continuous stream of TDMA frames, each frame is split into eight time
slots. When a connection is required the system allocates the
subscriber a dedicated time slot within each TDMA frame. User data
(speech/data) for transmission is digitized and sectioned into blocks.
The user data blocks are sent as information bursts in the allocated
time slot of each TDMA frame.

The data blocks are modulated onto the carrier using Gaussian
Minimum Shift Keying (GMSK), a very efficient method of
phase modulation.

Each time an information burst is transmitted, it may be transmitted
on a different frequency. This process is known as frequency hopping.
Frequency hopping reduces the effects of fading, and enhances the
security and confidentiality of the link. A GSM radiotelephone is only
required to transmit for one burst in each frame, and not continually,
thus enabling the unit to be more power efficient.

Each radiotelephone must be able to move from one cell to
another, with minimal inconvenience to the user. The mobile itself
carries out signal strength measurements on adjacent cells, and the
quality of the traffic channel is measured by both the mobile and the
base station. The handover criteria can thus be much more accurately
determined, and the handover made before the channel quality
deteriorates to the point that the subscriber notices.

When a radiotelephone is well within a cell, the signal strength
measured will be high. As the radiotelephone moves towards the edge
of the cell, the signal strength and quality measurement decreases.

Signal information provides an indication of the subscriber’s

BenQ Rev 1.0

11

distance from the base station. As the radiotelephone moves from cell
to cell, its control is handed from one base station to another in the new
cell.

This change is handled by the radiotele-phone and base stations,
and is completely transparent to the user.

Service Area

The area within which calls can be placed and received is defined
by the system operators. (Because this is a radio system, there is no
exact boundary that can be drawn on a map.) If the telephone is
outside a coverage area, the (no service) indicator will illuminate and
calls will be unable to be placed or received. If this happens during a
conversation, the call will be lost. There may also besmall areas within
a particular service area where communications may be lost.

The radiotelephone’s identity information is held by its local GSM
system in its Home Location Register (HLR) and Visitor Location
Register (VLR). The VLR contains identity information on all local active
radiotelephones. Should you roam to another area, system or country
the radiotelephones identity information is sent to the VLR in the new
system. The new system will then check the radiotelephones details
with your home system for authenticity. If everything is in order it will be
possible to initiate and receive calls whilst in the new area.

BenQ Rev 1.0

12

△ Baseband function Descriptions

1. Introduction:

March(T191) utilizes TI’s chipsets (Ulysse and Nausica) as
base-band solution. Base-band is composed with two potions:
Logic and Analog/Codec. Ulysse is a GSM digital base-band logic
solution included microprocessor, DSP, and peripherals. Nausica is
a combination of analog/codec solution and power management
which contain base-band codec, voice-band codec, several voltage
regulators and SIM level shifter etc. In addition, 56D66 integrates
with other features such as LED backlight, LCD display, vibration,
buzzer and charging etc. The following sections will present the
operation theory with circuitry and descriptions respectively.

2. Block Diagram

2.1 Ulysse (Hercules)

JAMES WANG, WEN-SHIH LIU PAGE 1 OF 2

DUAL BAND AMETHYST

BASEBAND BLOCK DIAGRAM REV 1.0

DUAL BAND AMETHYST

SRAM
1Mbit

G5
A2
B5
A1
B2

Flash

Memory

32Mbit

D7
B4
B3
D8

ARM7

RTC

PWT
PWL

UART

I2C

SPI

MEM.
INTF.

GPIO

ACT

TSP

SIM

JTAG

RIF

Voice-

band
INTF

DAI

DSP

2M

SRAM

E10
A11

B6
C2

B1
D2

D3
F4

C4

K11

J1
J3
M6
A7

C7
C8
A8

P6
M9
N8
L8

P7
K8
K7

C6
E6
E9
B11
D11
B12
B13
H10

D14
E14
D13

J14
J13
K14

G1
H1
H3
H2

F12
F13
F14
G13

G11
H12
H13
H11

D8
D9
B9
A9

NROMCS1
FDP
RNW
NFOE

NRAMCS
NBLE
NBHE

MCUEN
MCUDO
MCUDI

IO3DATA_HP_SEL
IO13ACCIN

IO0VIBRATOR
IO1BATID_DET

SCL
SDA
NRSTOUT

TXD0
RXD0

BU
BL

RTCINT

H3
D7
G3
G14
H14

VR1 VR2 VR2B VR3

RX_ON
TX_ON

DCS_T/R

GSM_T/R

BS2

PC

BS1

LE

DATA

CLK

TSPEN0

S_CLK

S_IO

S_RST

TCK
TMS
TDO

TDI

BFSR

BDR

BFSX

BDX

VCLKRX

VDX
VDR

VFSRX

DAI_RST

DAI_CLK

DAI_DI

DAI_DO

TO / FROM

OMEGA

{

TO / FROM

OMEGA

{

JTAG

TO / FROM

OMEGA

{

DAI INTF

{

DATA BUS

DATA BUS

ADDRESS BUS

VR2

DATA BUS

ADDRESS BUS

VR2

}

TO / FROM ULYSSE

LCM

CONT.

4
5
6

7 , 8

1

2 , 3

VR2
VLCD

C34

}

TO EARPHONE JACK

BQ3

BUZZER

U7 BQ2

LCM BACKLIGHT

KEYPAD BACKLIGHT

BQ4 M

U15 BATID

EXTIRQ
EXTFIQ
NRESET

13MHZ

13MOUT

FROM

OMEGA

FROM U61

KEYPAD

POWER

FROM OMEGA

ULYSSE

U1

VIBRATOR

X1 32.768KHZ

E11
D6

TCXOEN

ON_OFF

{

{
{

TO RF BLOCK

TO RF BLOCK

{

TO / FROM

OMEGA

ROW0~ROW3

COL0~COL4

ADDRESS BUS

VBAT

VBATBB

VBAT

U5

U6

TO OMEGA

TO U84,U90

FROM OMEGA

TO OMEGA

TO OMEGA

U9

3
4
2

1

R72

EARPHONE JACK

TXDO

AUXI

IO3DATA_HP_SEL

IO13ACCIN

RXDO

AUXOP

U8

U10

VR2BSW

VR2BSW

MIC

SPK

VR2BSWVR2B

{

U13

M1

BenQ Rev 1.0

13

2.2 Nausica (Omega)

IBIC
BUS

CONT.

C4
B3
B2
B4
B5
D4
A2
A1
B1

BSP

K5
J 5
H5
G5

SPI

BCI

ADC

VRPC

F5
K6
J 6

E3
E4
E5

B5
A5
E6
D6
C6

F7
F6
D7
D10

B10

BACKUP

VR1B

2.0V@50mA

VR2B

2.9V@50mA

VR2

2.9V@120mA
VR1

1.8V@120mA
VR3

2.9V@80mA

VREG

B/B
U/L

C9

C10

D8
D9

B/B
D/L

E7
E8
E9

E10

AFC
APC

TSP

VOICE

D/L

VOICE

U/L

USP

SIM REG.

3/5V

SHIFTER

F8
F9
J 4

K4
H8

H9
J 9
K9
J 8
K8
H7

H6
G6
G7
K7

K3
D2

G9

J3
C3

C1

D1

E1

H1

H10

F1
A4

TXIP
TXIN
TXQP
TXQN
RXIP
RXIN
RXQP
RXQN

AFC

RAMP

SMADA
TPENQ

AUXOP
MICBIAS

MICIN
MICIP
AUXI

VCLKRX
VDR
VDSRX
VDX

S_CLK
S_RST
S_IO
CLK
RST
I/O
VSIM

C8

BDX

BFSX

BDR

BFSR

MCUEN0

MCUDO

MCUDI

ICTL

VCHG

VBAT

BATID

TBAT

HWID

EXTFIQ

NRESET

RTCINT

ON_OFF

PWON

VCC1
VCC2
VCC3

VBACKUP

UPR

VR1B

VR2B

VR2

VR1

VR3

OSCAS
EXTIRQ

EARPHONE_IN

SIM

SOCKET

1
3
2
4

}

TO / FROM
ULYSSE

}

}

TO U61

}

FROM U61

TR1

ROW4

S19

EARN
EARP

SPEAKER

MICROPHONE

TO U85
TO U74

}

TO/FROM ULYSSE

{

TO / FROM

ULYSSE

{

TO / FROM

ULYSSE

{

FROM
BATBB

OMEGA

POWER JACK

BATTERY

CONNECTOR

U3

COIN LI-ION

BATTERY

TO / FROM
ULYSSE

1
2
3
4

4
3
2
1

ICTL

VCHG

MANTEST

FUSE

F1

+

_

U4

U14

FROM ULYSSE

C22

TO / FROM

ULYSSE

{

D1

S1

G2

D2

G1

S2

U17

U17

JAMES WANG, WEN-SHIH LIU PAGE 2 OF 2

DUAL BAND AMETHYST

BASEBAND BLOCK DIAGRAM REV 1.0

DUAL BAND AMETHYST

U18

U16

D1

D2

D1

D2

J 1

R21

R24

VR3

VBBATBB

3. Theory:

3.1 Ulysse

ULYSSE (HERCROM200) is a chip implementing the digital
base-band processor of a GSM mobile phone. This chip combines a
DSP M16L80 mega-module (LEAD2 CPU) with its program and data
memories, a Micro-Controller core with emulation facilities
(ARM7TDMIE) and an internal 2M-bit RAM memory, a clock squarer
cell, several compiled single-port or 2-ports RAM and 120K
equivalent CMOS gates.

Major functions of this chip are as follows:

3.1.1 Real Time Clock (RTC)

3.1.2 Pulse Width Tones (PWT)

The function of the PWT is to generate a modulated frequency
signal for the external buzzer.

3.1.3 Pulse Width Light (PWL)

This module allows the control of the backlight of LCD and keypad
by employing a 4096 bit random sequence.

BenQ Rev 1.0

14

3.1.4 MODEM-UART

3.1.5 I2C master serial interface (I2C)

In 56D66, we employ I2C bus to control LCD module.

I2C_SCL: programmed to the fast transmission mode (400KHz)
I2C_SDA: the serial bi-directional data of the LCM controller

3.1.6 General Purposes I/O (GPIO)

Ulysse provides 16 GPIOs configurable in read or write mode by
internal registers. In 56D66, we utilize 5 of them as follows:

IO0 : to control vibrator; ‘L’: idle, ‘H’: activate vibrator
IO1 : to identify legal NiMH battery
IO3 : to control phone jack configuration; ‘L’: data cable, ‘H’:

hands-free

IO8 : to support one-wire protocol for Li-Ion battery

IO13 : to detect accessory plug-in at phone jack; ‘H’: idle, ‘L’: plug-in

3.1.7 Serial Port Interface (SPI)

3.1.8 Memory Interface and internal Static RAM

A 2Mbit SRAM is embedded on the die and memory mapped on the
chip-select CS6 of the memory interface.

3.1.9 SIM Interface

3.1.10 JTAG

3.1.11 Time Serial Port (TSP)

3.1.12 TSP Parallel interface (ACT)

In 56D66, we employ 8 of them to control RF activity.

TSPACT1: Band selection 1 (BS1)
TSPACT2: Power control enable (PC)
TSPACT3: Band selection 2 (BS2)
TSPACT4: GSM TR switch on/off (GSM_TR)
TSPACT5: DCS TR switch on/off (DCS_TR)
TSPACT8: RX VCO on/off (RX_ON)
TSPACT9: TX VCO on/off (TX_ON)
TSPACT10: Latch enable (LE)

3.1.13 Radio Interface (RIF)

3.2 Nausica (Omega)

Together with a digital base-band device (Ulysse), OMEGA is part
of a TI DSP solution intended for digital cellular telephone applications
including GSM 900, DCS 1800 and PCS 1900 standards (dual band

BenQ Rev 1.0

15

capability).

It includes a complete set of base-band functions to perform the
interface and processing of voice signals, base-band in-phase (I) and
quadrature (Q) signals which support single-slot and multi-slot mode,
associated auxiliary RF control features, supply voltage regulation,
battery charging control and switch ON/OFF system analysis.

OMEGA interfaces with the digital base-band device through a set
of digital interfaces dedicated to the main functions of Ulysse, a
base-band serial port (BSP) and a voice-band serial port (VSP) to
communicate with the DSP core (LEAD), a micro-controller serial port
to communicate with the micro-controller core and a time serial port
(TSP) to communicate with the time processing unit (TPU) for real time
control.

OMEGA includes also on chip voltage reference, under voltage
detection and power-on reset circuits.

Major functions of this chip are as follows:

3.2.1 Baseband Codec (BBC)

3.2.2 Automatic Frequency control (AFC)

3.2.3 Automatic Power Control (APC)

3.2.4 Time serial port (TSP)

3.2.5 Voice band Codec (VBC)

3.2.6 Micro-controller serial port (USP)

3.2.7 SIM card shifters (SIMS)

3.2.8 Voltage Regulation (VREG)

Linear-regulation performed by several low dropout (LDO) regulators
to supply analog and digital baseband circuits.
(1) LDO R1 generates the supply voltage (2.5V, 1.8V, 1.4V and 1.2V)

for the digital core of Ulysse. In 56D66, it is programmed to 1.8V.
This regulator takes power from the battery voltage and it has a
backup through BBS system.

(2) LDO R1B generates the supply voltage 2.0V for the digital core of

OMEGA. It is supplied by the battery.

(3) LDO R2B generates the supply voltage 2.9V for the digital I/O’s of

Ulysse and Omega. It is supplied from battery voltage and has a
backup through BBS system.

BenQ Rev 1.0

16

(4) LDO R2 generates the supply voltages 2.9V for Ulysse memory

interfaces I/O’s. It has a backup through BBS system.

(5) LDO R3 generates the supply voltage 2.9V for the analog

functions of OMEGA.

The backup battery switch (BBS) generates at its output an
uninterrupted power rail (UPR) of which purpose is to supply
continuously the minimum necessary circuitry of the power-control
functions either from the main battery of from the backup battery

3.2.9 Baseband Serial Port (BSP)

3.2.10 Battery charger Interface (BCI)

3.2.11 Monitoring ADC (MADC)

3.2.12 Reference Voltage / Power on Control (VRPC)

3.2.13 Internal bus and interrupt controller (IBIC)

3.3 Power Supply circuit

BGND

BGND

VR3

BGND

BGND

BGND

VR2B

BGND

BGND

BGND

VR2

VBATBB

VR1VR1B

TPL16

1

U1

ULYSSE_uBGA179

B2
C2
C3
B1
C1
D3
D2
D1
F5
E4
E2
E3
E1
F4
F3
F2
F1
G5
G4
G2
G3
G1
H1
H3
H2
H4
H5
J1
J2
J3
J4
K1
K3
K2
K4
J5
L1
L2
L3
M1
N1
M3
M2

N2

P2N3P3L4M4N4P4K5L5N5P5M5K6M6P6N6L6K7L7P7N7M7M8N8P8L8K8L9N9P9M9K9M10

P10

N10

L10

K10

P11

N11

M11

L11

P12

N12

P13

N13

M13

M12

N14

M14

L12

L13

L14

K11

K13

K12

K14

J11

J12

J13

J14

H10

H11

H13

H12

H14

G14

J10

G12

G13

G11

G10

F14

F13

F12

F11

E14

E12

E13

E11

F10

D14

D13

D12

C14

B14

C12

C13

B13

A13

B12

A12

D11

C11

B11

A11

E10

D10

B10

A10

C10E9C9A9B9D9E8D8A8B8C8C7B7A7D7E7D6B6A6C6E6C5A5B5D5E5A4B4C4D4A3B3A2

P1

A14

P14

GND
BU/PWT
VDDS2
LT/PWL
SDO/INT10n
RX_MODEM
TX_MODEM
SD_IRDA/CLKOUT_DSP
DSR_MODEM/LPG
RTS_MODEM/TOUT
CTS_MODEM/XF
SCLK/INT1n
RX_IRDA
nSCS0/SCL
RXIR_IRDA/X_A1
TX_IRDA
TXIR_IRDA/X_A4
nSCS1/X_A2
nEMU1
nEMU0
nRESPWRON
TCK
TMS
TDO
TDI
nBSCAN
EN_LMM_PWR/X_IOSTRB
IO0/TPU_WAIT
GND
IO1/TPU_IDLE
ADD0
ADD1
VDDS1
ADD2
ADD3
VDD
ADD4
ADD5
ADD6
ADD7
ADD8
ADD9
ADD10

ADD11

ADD12

ADD13

GNDLMM

ADD14

IO2/IRQ4

ADD15

ADD16

ADD17

ADD18

ADD19

ADD20

VDDLMM

ADD21/CK16X_IRDA

IO3/SIM_RnW

nCS0

GND

VDDS1

nBHE/IO14

nCS1

nCS2

GNDLMM

nCS3

CS4/ADD22

RnW

VDD

nFOE/X_A3

nBLE/IO15

nFWE/X_A0

VDDS1

DATA0

FDP/nIACK

DATA1

GND

DATA2

DATA3

GND

DATA4

DATA5

GNDARM

DATA6

DATA7

VDDARM

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

GND

DATA15

CLK13M_OUT/START_BIT

nRESET_OUT/IO7

TSPACT11/MCLK

VDDS2

SIM_RST

SIM_CD/MAS0

SIM_PWCTRL/IO5

SIM_IO

SIM_CLK

TSPACT10/nWAIT

VFSRX

VDR

VDX

GNDA1

CLKTCXO

VDDS1

VDDA1

BDX

VCLKRX

BCLKX/IO6

BFSX

BDR

BFSR

BCLKR/ARMCLK

TSPCLKX

GND

EXT_IRQ

TCXOEN

VDD

TSPDO

TSPEN0

TSPEN1

TSPDI/IO4

TSPEN2

TSPEN3/nSCS2

TSPACT0

TSPACT1

VDD

TSPACT2

GND

TSPACT3

CLK32K_OUT

GNDA2

OSC32K_OUT

OSC32K_IN

VDDS2

TSPACT4

RFEN/NOPC

GND

TSPACT5

IDDQ

MCSI_TXD/IO9

MCSI_RXD/IO10

MCSI_CLK/IO11

TSPACT6/nCS6

MCSI_FSYNCH/IO12

MCUDI

VDDLMM

MCUDO

MCUEN0

MCUEN1/IO8

MCUEN2/IO13

EXT_FIQ

TSPACT7/CLKX_SPI

ON_OFF

IT_WAKEUP/INT4n

KBC0/NFIQ

TSPACT8/nMREQ

TSPACT9/MAS1

GNDLMM

KBC1/NIRQ

KBC2/XDI_00

KBC3/XDI_01

KBC4/XDI_02

KBR0/XDI_03

KBR1/XDI_04

SDI/SDA

KBR2/XDI_05

VDDLMM

KBR3/XDI_06

KBR4/XDI_07

GND

VDDS2

VDDS1

C21 10UF

C26

0.1UF

C250.1UF

C19 2.2UF

C1710UF

C20 10UF

R22

0

R15

0

U3

OMEGA

B2B1C2C3C1D2D1D3E1E2E3E4E5F1F2F3F4G4G1G2G3H1H2J1K1

J2

K2

J3

H3

K3

J4

K4

H4

K5

J5

H5

G5

F5

K6

J6

H6

G6

G7

K7

J7

H7

K8

J8

K9

K10

A10

B10C9D8D9D10D7E7E8E9

E10F6F7F8F9

F10G8G10G9H10H8H9

J10

J9

A1

A2

B3

A3

C4

B4

A4

D4

D5

C5

B5

A5

E6

D6

C6

B6

A6

C7

A7

B7

A8

C8

B8

A9

B9

C10

SIO3

VS1

GRND2

UPR

VR1BOUT

VCC2

VR2BOUT

VR2SEL

VR2OUT

VR2IN

ICTL

VCHG

VBAT

OSCAS

TESTRESETZ

REFGND

VREF

BGTR1

IBIAS

BGTR3

BGTR2

VR1OUT

BGTR4

FDBK

GRND1

BGTR5

SWITCH

VBACKUP

COMP

VCC1

TDR

TEN

INT2

BDX

BFSX

BDR

BFSR

UEN

UDR

UDX

VCK

VDX

VFS

VDR

AGNDA1

AUXI

MICIP

MICIN

MICBIAS

BUZZOP

RPWON

PWON

BULIP

BULQP

BULQM

ONNOFF

RTC_ALARM

BDLIP

BDLIM

BDLQP

BDLQM

RESPWRONZ

INT1

AFC

APC

DAC

AUXGND

GRND3

VCC3

VR3OUT

EARN

EARP

AUXON

AUXOP

VS2

SVDD

SRST3

VAUX

SCLK3

SCLK5

CK13M

SIO5

SRST5

LCDSYNC

ADIN1

ADIN2

ADIN3

ADIN4/TSCXP

ADIN5/TSCYP

TSCXM

TSCYM

TDO

TDI

TCK

TMS

TEST1

TEST2

TEST3

TEST4

BULIM

R54

0

+-V

U4A

Back-up Battery

2 1

R160R17

0

C15 2.2UF

2.9V@80mA
Omega/Ulysse Analog part

1.8V@120mA

Ulysse Core

2.9V@120mA

Memory

2.9V@50mA

Peripherals

(From Main Battery)

2.0V@50mA

Omega Core

The phone is mainly supplied from the main battery (VBAT)
which is divided into two routes: VBAT is for RF block, vibrator and
buzzer; VBATBB is for baseband block.

The input power (VBATBB) to Nausica is divided into 4 blocks:

BenQ Rev 1.0

17

VCC1: to provide power for DC/DC and regulator R1 (VR1)
VCC2: to provide power for regulator R1B (VR1B), R2B (VR2B) and

charger pump
VCC3: to provide power for regulator R3 (VR3)
VR2IN: to provide power for regulator R2 (VR2)

NAUSICA provides five low drop-out voltage regulators.
R1 (VR1): 1.8V@50mA; to supply ULYSSE digital core, RTC,

32KHz and the internal SRAM

R2 (VR2): 2.9V@120mA; to supply 13MHz clock, external memory

devices and LCD display

R2B (VR2B): 2.9V@50mA; to supply peripheral devices, I/O to

NAUSICA
R1B (VR1B): 2.0V@50mA; to supply the digital part of NAUSICA
R3 (VR3): 2.9V@80mA; to supply analog part of NAUSICA.
Among these 5 LDOs, only R1, R2 and R2B are support with

back-up mode.

The power of Ulysse is supplied by these LDOs:
VDD: supplied by VR1 and used for core logic
VDDS1: supplied by VR2 and used for I/Os to memory devices
VDDS2: supplied by VR2B and used for I/Os to Omega and
peripherals

VDDLMM: supplied by VR1 and used for Lead MegaModule (DSP)
VDDARM: supplied by VR1 and used for ARM

BenQ Rev 1.0

18

3.4 System power on/off Sequence

3.4.1 Power on

There are three conditions that system can power on.

-On button pushed: A falling edge is detected on PWON pin and the

debouncing time is greater than 30ms.

-Set Alarm: A rising edge is detected on RTC_ALARM (RTCINT)

-Charger plugged: VCHG > VBAT + 0.4V is detected

When these conditions occur in the power on state, the

hardware power on sequence starts:

1. Enable local oscillator OSCAS (~ 100KHz)

2. Enable band-gap (VREF and IREF)

3. Check if Main Battery voltage is greater than 3.2V

4. Enable charge pump (VAUX ~ 5.8V)

5. Enable LDO regulators (R1, R1B, R2, R2B and R3)

6. Set ON_OFF pin to ‘H’.

7. NRESET pin is set from ‘L’ to ‘H’

8. 13MHz clock oscillator is enabled (Ulysse’s task)

3.4.2 Power off in normal mode

When system is powered off in normal mode by long pressing

power-on key, the power off sequence will be executed:

1. Start watchdog timer during 150us and disable DC/DC

2. Set ON_OFF pin to ‘L’

3. Disable all the regulators

4. Disable the band-gap

5. Disable the local oscillator OSCAS

3.4.3 Power off in emergency mode

When the main battery voltage is detected lower than 2.7V, the

following sequence is executed:

1. Set INT1 (FIQ) to ‘L’

2. Start watchdog timer during 150us and disable DC/DC

3. Set ON_OFF pin to ‘L’

4. Disable all the regulators

5. Disable the band-gap

6. Disable the local oscillator OSCAS

BenQ Rev 1.0

19

3.5 Memory circuit

DATA BUS

U5

FLASH

U6

SRAM

ULYSSE

CE#

CE1

NROMCS1

NRAMCS

OE#

NFOE

ADDRESS BUS

RP#

WE#

FDP

RNW

OE
HB
LB

NBHE
NBLE

VCCQ

VCC

VCC
VCC
CE2

VR2

VR2

Description

Flash (U5) is a 32Mbit device, supported by VR2 and booted from
top. The total 32Mbits are divided into two sections: 24Mbits is used
for software program code and 8Mbits is used for EEPROM data. The
access time of Flash is 100ns.
SRAM (U6) is a 1Mbit device, supported by VR2. The access time of
SRAM is 70ns.

BenQ Rev 1.0

20

3.6 Display circuit

VR2

BGND

NRSTOUT

I2C_SDA

I2C_SCL

R27

1K

C33

1UF(0603)

C32

C(0603)

J2

LCD

1

2

3

4

5

6

7

8

9

10

VLCD

VSS

VSS

SCL

SDA

/RES

VDD2,3

VDD1

X

X

C50

39PF

C51

39PF

C34

1UF(0805 Z5U 16V)

2.9V

400KHz

7.6V

From U1/Ulysse

Description

Display circuit is composed of a 98*64 resolution LCD module and
a display supply voltage bypass capacitor C34. The power of LCDM is
supplied from VR2. It is controlled by U1 via I2C bus: SCL and SDA.
The data rate of I2C is programmed to 400KHz. NRESTOUT is low
active to reset all LCD registers. The LCD Module is adopted with
COG (chip on glass) type, and default display supply voltage VLCD at
normal temperature is 7.6V. R27 is used for ESD protection and C50,
C51 are used for radiation suppression.

BenQ Rev 1.0

21

3.7 Vibrator circuit

BGND

VBAT

IO0VIBRATOR

R49

15

R46

1K

A

-

+

M1
LA4-432

12

BQ4

UMT4401

2

1

3

D14

DAN222

2

1

3

3.6V

94mA

1.2V

From U1/Ulysse

Description

To enable vibration, Ulysse sets IO0VIBRATOR to ‘H’ to activate
the motor. R46 and R49 are used to make BQ4 working in saturation
area. D14 is used to feedback EMF. Under the condition of VBAT =

3.6V, the average voltage across the motor is about 1.2V and drain
current is around 94mA.

BenQ Rev 1.0

22

3.8 Buzzer circuit

VBAT

BGND

BGNDBGND

BU

BUZZOP

C59
8PF

D14
DAN222

2

1

3

U13

BUZZER

3

4

R48
0

R45

1K

BQ3

UMT4401

2

1

3

T10

TVS

1 2

. .

D16

DAN222(N.M.)

2

1

3

R71

0

3.6V

78mA

1.3V

From U1/Ulysse

(PWT)

(Not In Use)

Description

To alert the buzzer, Ulysse applies PWT (Pulse Width Tone) signal
at BU to drive the buzzer. R45 and R48 are used to make BQ3
working in saturation mode. D14 is used to feedback EMF. Under
the condition of VBAT = 3.6V, the average current is 78mA and terminal
voltage of buzzer is about 1.3V.

BenQ Rev 1.0

23

3.9 LED circuit

BGND

VBATBB

BGND

BGND

BL

BQ2

UMT4403

2

1
3

D8
19-21

D7
19-21

D9
19-21

D5
19-21D619-21

R34

2K

D10
19-21

R35

24 (0805)

U7

UMH10N(SOT363)

1 6

2

3 4

5

D11
19-21

D12
19-21

D3
22-21

D13
22-21

D4
22-21

R40

39 (0805)

3.6V

From U1/Ulysse

3.35V

60mA37mA

1.9V

(PWL)

Description

56D66 employs three LEDs for LCD module backlight and eight
LEDs for keypad backlight. To light up the LEDs, Ulysse applies PWL
(Pulse Width Light) at BL to drive LEDs. U7 is used as an inverter to
enable BQ2. Under the default condition (VBAT=3.6V), the average
current of one LCD backlight LED is about 12mA and of one keypad
backlight LED is about 7.5mA. In 56D66, all the LEDs are yellow-green
color and forward voltage is 1.9V

BenQ Rev 1.0

24

3.10 Audio circuit
Uplink:

MICIP

MICIN

BGND

MICBIAS

BGND

BGND

C43

4.7UF(0805)

R43

1K

C44 1UF(0603)

X2

Microphone

1
2
3

1
2
3

C54
47PF

R44

4.3K

C42

0.1UF

C45 1UF(0603)

R47

4.3K

U14

EMIF01-10005W5

1
2

34

5

I1

GND

I2O2

O1

R50 0

C53
47PF

R51 0

2.5V

From U3/Omega

To U3/Omega
To U3/Omega

Downlink:

EARN

EARP

BGND BGND

BGND

C39

100PF

BL2 0

BL3 0

R74

10

LS1

SPEAKER_0

C41
150PF

U12

EMIF01-10005W5 (N.M.)

1
2

3 4

5

I1
GND

I2 O2

O1

C40
150PF

R73

10

T4

TVS

1 2

. .

T3

TVS

1 2

. .

From U3/Omega
From U3/Omega

Description
The audio circuit is divided into two parts, uplink and downlink.

For uplink path, the analog voice signals are fed into NAUSICA
from the microphone differential input and then transmitted to Ulysse
DSP via the voice-band series port (VSP). After being modulated, the
signals go through the uplink I/Q path to the RF transceiver and
transmitted from the antenna.

The microphone circuit is biased from Nausica MICBIAS (2.5V).
The bias circuit R43, R44, R47 mainly provides the optimal operation
point for the microphone signals, MICP and MICN.
For downlink path, the signals received from the antenna are
down-converted to I/Q signals and then transmitted to Ulysse DSP.
After being demodulated, the signals are fed to NAUSICA via
voice-band interface and then amplified to drive the receiver.

BenQ Rev 1.0

25

3.11 Charging circuit

BGND

BGND

BGND

VBATBB

VBAT

VR3

BGND

BGND

BGND

BGND

BGND

BGND

BGND

BGND

BGND

CHARGERIN

TBAT

VCHG

BATID_NIMH

IO8ONEWIRE

ICTL

G1

S2 G2

D2S1D1

U17
FDC6506P

1 6

3 4

52

C28

C

C31

0.1UF

G1

S2

G2

D2

S1

D1

U18
FDG6303N

1 6

3 4

52

R70 0

R66

3.9M

R67
200K

C48

4.7UF(0805)

R68 0

D15

RB520S-30

1 2

G1

S2

G2

D2

S1

D1

U16FDG6303N

1 6

3 4

52

R65
43K (1%)

R63

470K

R62

470K (1%)

R60

6.2K

F1

FUSE(1A 0603)

C49
1K

T1

TVS

12

..

T5

TVS

12

..

J1

Power Jack

1
2
3
4

V+
SW
SW

GND

J5

0

1
2
3

C56

10UF(0805)

R24

0.2(1%) 0805

D1

CRS03

1 2

C30
100PF

R25
47K

JP1

BATTERY CONN

4
3
2
1

C29

10UF(0805)

C47

0.1UF

C57

1000PF

C55

0.1UF

R64
100K

C58

1000PF

Trigger Charging Circuit

Charger Over-voltage Protection Circuit

Main Charging Route

To U3/Omega To U3/Omega

Description

The charging circuit of 56D66 is composed of charger over-voltage
protection circuit, 3-sec trigger charging circuit and main charging
circuit that are controlled by Omega (U3). 56D66’s charging devices
are standard linear 3.6V/600mA charger and switching VPA (cigarette
charger) with 6V/400mA output.

The group of R62, R65, R63 R64, R70, C47 and U16 compose the
charger over-voltage protection circuit. The cut-off voltage is 8V.
While the charger voltage is over 8V, the circuit will turn off U17 by
latching U17.G1 to stop charging.

The group of D15, R66, C48, R67 and U18 compose the 3-sec
trigger charging circuit. At the very beginning of charging, the circuit will
force to turn on U17 to full charger the battery which can prevent from
long charging wake-up for deep discharge battery. After around 3
seconds, software will take over the charging task by controlling ICTL.

BenQ Rev 1.0

26

F1 is a 1A fuse to assure charging current under limit.

The normal charging operation theory is that Omega monitors
charger voltage via VCHG pin to decide whether charger plug in or out,
and control power P-MOSFET (U17) via ICTL pin. If phone enters into
charging mode, Ulysse will follow the charging algorithm to control
charging circuit and monitor charging current by detecting the terminal
voltage of R24 (0.2 ohm). Omega control procedure is classified into
two parts according to whether battery voltage is higher than 3.2V.
Omega will execute trickle charge with 20mA to charge battery via
VCHG pin if battery voltage is lower than 3.2V. On the other hand, the
phone will proceed normal charging task following by the charging
algorithm.

BenQ Rev 1.0

27

3.12 Earphone jack circuit

IO3DATA_HP_SEL

VR3

IO13ACCIN

AUXI

EARPHONE_INRXD0

MICBIAS

TXD0

AUXOP

BGND

BGND

BGND

BGND

BGND

VR3

VR2B_SW

BGND

BGND

VR2B_SW

BGND

T9

TVS

1 2

. .

T8

T

1 2

. .

R76

0

U8

NC7SB3157

1

3

2

4

5

6

B1

B0

GndAVcc

S

BL1

BEAD(0603)

R36
10K

T2

TVS

1 2

. .

C37

4.7UF(0805)

R72
1K

J3

Audio Jack

12
3
4 5

GNDSW
SPK
MIC MIC

R37
2K

R38

1K

R41

2K

U9

EMIF01-10005W5

1
2

3 4

5

I1
GND

I2 O2

O1

U10

NC7SB3157

1

3

2

4

5

6

B1

B0

GndAVcc

S

C38

1UF(0603)

BL4

22

J4

0

1
2
3

TP33

1

R32
100K

L: Download
H: Earpiece
active

Plug-In

2.9V

2.9V

V= 1.0 ~ 2.4 => Hands-free
V= 2.6 ~ 2.8 => Data Cable

(To U3/Omega)

2.9V

(Not In Use)

For Data Cable

For Hands-Free

(From U1/Ulysse)

Description

The earphone Jack circuit is used either for the headset or the data
service. The IO13ACCIN will be pulled to low level when headset or
data cable is plugged in. Here, U8 and U10 are used as the switch
between headset using or data service using which is controlled by the
IO3DATA_HP_SEL. When IO13ACCIN is detected as low level,
IO3DATA_HP_SEL is switched from low to high level to identify whether
the headset or the data cable is plug-in by reading the voltage at
EARPHONE_IN. If the voltage at EARPHONE_IN is in the range of

1.0V to 2.4V, the phone recognizes headset is plugged in and
IO3DATA_HP_SEL stays at high to keep U8 and U10 as auxiliary audio
path. If the voltage at EARPHONE_IN is in the range of 2.6V to 2.8V,
the phone identifies data cable plugged in and IO IO3DATA_HP_SEL
switches back to low to keep U8 and U10 as data service path.

BenQ Rev 1.0

28

3.13 Rader circuit

OMEGA

SCLK5

SIO5

SRST5

SVDD

RST

CLK

VCC/VPP

GND

I/OSIO3

SCLK3

SRST3

SIM_IO

SIM_CLK

SIM_RST

ULYSSE

SIM

SOCKET

Description

The SIM follows the GSM and ISO specifications and works in 3
volts or in 5 volts with a minimum external logic.

SIM_IO(I/O): Data
SIM_RST(O): Reset signal
SIM_CLK(O): Clock (1.6MHz/3.2MHz)

The SIM card digital interface insures the translation of logic levels
between ULYSSE and SIM card. There is a level shifter embedded in
Omega to support 5V SIM card.

BenQ Rev 1.0

29

3.14 Keyboard circuit

BGND

ROW2

COL2

COL3

COL1

ROW4

ROW3ROW0

COL4

ROW1

COL0

PWON

S1
KSW

[3]

S7
KSW

[4]

S2
KSW

[2]

S16
KSW

[#]

S10
KSW

[7]

S3
KSW

[1]

S9

KSW

[8]

S6
KSW

[5]

S5
KSW

[6]

S4
KSW

[Down]

D2

RB520S-30

1 2

S13
KSW

[0]

S15
KSW

[menu]

S19

KSW

[NO]
[PWR]

S14
KSW

[*]

S8
KSW

[SEL]

S17
KSW

[Send]

S12
KSW

[9]

S18
KSW

[QUIT]

S11
KSW

[Up]

To U3/Omega

Description

1. The keypad is made of a 5 Column x 4 Row matrixes.

2. The keypad matrix is as follows:

Function Key

COL0 COL1 COL2 COL3 COL4 RO

W0 ROW1 ROW2

ROW3

3 S1 0 0
2 S2 0 0
1 S3 0 0

DOWN S4 0 0

6 S5 0 0
5 S6 0 0
4 S7 0 0

SEL S8 0 0

8 S9 0 0
7 S10 0 0

UP S11 0 0

9 S12 0 0
0 S13 0 0

* S14 0 0

MENU S15 0 0

# S16 0 0

SEND S17 0 0

QUIT S18 0 0

NO/PWR S19

Reference Drawing:

BenQ Rev 1.0

31

56D72 Side 1 Layout

U2

RN4

RN2

RN1

RN3

D2

R1

R26

C1

C2

R56

R52

R59

R58

R57

RN5 RN6

C13

R14

U7

BQ2 U14

C35

R34

C54

C53

C44

C45

C55

T1

R51

R50

R44

C43

C48 U18

D15

D1

R24

C29 C56

R66

R67

R25

C36

C42

TR1

R43

R47

R19

C4

C5

R5 R8

R7

R9

C7

R6

R28 R29 R13

R15

R17

R18

R16

C9

R21

C24 R20

C25

C18

C6

R77

C22

R4

R23

C46

C23

C8

C19 C20

C21

C17

C15

R41

R22

C12

C11

C26

R54

C37

R37

R38

U8

U10

C38

R33

R36

R32

U9

JP1

R11

C3

R2

J1

X2

U6

U5

U1

U3

X1

RF

BLOCK

D14

T10

J3

T8

T9 T2

R72

R76

C27

R3

C16

U15

BenQ Rev 1.0

32

56D72 Side 2 Layout

LCD Module

D5

D7

D9

D11

D6

D8

D10

D12

D3

D4

D13

C57

T3

C34

T4

BL2

BL3 R74

C41

R73

C39

C40

R40

R35

C50

C51

C33R27

BQ3

BQ4

R48

R45

R71

R49

R46

C31

C30

T5

R60

F1

R75

R68

U17

R64

R70

R65

R63

R62

C49

C47

U16

U4

R61C10

R80

C58