Belson BSA-3800R Service Manual

BSA-3800R Service Manual
. Introduction of the Function
BSA-3800R is Digital recorder & player, it is the representative product in DVR series of Wanlida. It can recorder the signal of video tape recorder or of vidicon or of TV to be DVD disc. It supports recording DVD+R/RW discs. It composites two groups of video input, one group of S-video, TV signal etc. Real time clock set , it can support recording programs by presenting time, channel, times of channel and quality level. For example, one DVD+R/W disc of 4.7G will cost 1 hour, 2hours, 3 hours and 4 hours differently with different recording quality level. BSA-3800R composites video, S-video, RCA video output, 5.1 CH, Optical, Coaxial audio output. Built-in all range of TV frequency Tuner.
. Schematic Diagram
BSA-3800R adopts NEC recorder chip ND-1100A, based on ATAPI jack. The
whole system based on ES7010, ES6128 decoder chip, input origin signal and TV signal then transfer to digital signal by SAA7114 decoder. The digital signal will be recorder DVD signal after dealing by ES7010 encoder. The following is the schematic diagram of mainboard:
TV
S
Video
V i d e o output
128M SDRAM
128M SDRAM128M SDRAM
Data Buffer LVT244B
Data Buffer
LVT244B
LVT244B
Video 1
2
Output
signal
Tuner
video
V i d e o d e c o d e r SAA7114
A u d i o ADCWM8739
WM8739
64M SDRAM
64M SDRAM64M SDRAM
64M SDRAM
64M SDRAM64M SDRAM
Panel control signal and others
Video 1
A u d i o s w i t c h CD4052
Video
2
TV
signal
Audio output
ES6128
ES6128
EPROM
EPROM
CPLD
CPLD
ISP2064VE
ISP2064VE
16M FLASH
16M FLASH
D V D + R / R W
recorder chip
I/O LVTH273
ES7010
ES7010
Data
Video
ou tp u
input
t
In/ out
Audio
input
buffer
Figure 1 BSA-3800R mainboard schematic diagram
Send one group of Video 1, or Video 2, or S-video , or TV video signal to SAA7114 video decoder. SAA7114 is apply to the control aspect of video graphic array. It has six groups of separated inputs. After interior software controlled and chosen the original signal, video AD will be transferred to digital signal and output from 81-94 pin. The digital video signal will be sent to ES7010 and ES6128 through the data buffer LVT244B. When it enter into the outside source, digital video signal will be directly outputted the video signal by ES6128 decoder. This way is called “direct signal”, it will shorten the time of transferring between signal output and video output, and it can avoid the complicated step of encoding and decoding to make the switch speed of TV
channel be faster. When it recording, the digital video signal will be recorded into DVD+R/RW disc by ES7010 decoder, and then the decoded signal will be sent to ES6128 decoder to output video signal. Three groups of audio signal will be chosen one group to output at 3 and 13 pins through 4 groups multi output CD4052. The chosen audio signal will be transferred into digital audio signal by stereo audio ADC that integrated with WM8739. The digital audio signal will be sent to ES7010 decoder. ES7010 is a MPEG2 audio&video encoding chip. The main frequency of ES70101 is 27MHz. In ES7010, there are one unit of video decoding&decoding transfer, digital audio signal dealer, one CPU with 32 bits, one video input/output unit and one system control unit. Depending on the function, it can use SDRAM. of 8M or 16M. The
following is the ES7010 interior diagram
control
S e r i a l
interface
jack unit
Reset signal
GPIO GPIO
data
Serial interface control
Saved data
Time clock
signal
Audio input
S D R A M
input unit
SDRAM
PLL
PLL
in pu
t
V i d e o
input unit
Audio digital
signal dealer
output
V i d e o
o u t p u t
Interior CPU
Video encoding/
视频/
Encoding transfer
System control unit
data
Main CPU j ack
CPU
unit
CPU
Figure
2ES7010 interior diagram
ES6128 exchange data with ES7010 by ISPLSI 2064. ISP LSI2064 is a logic equipment that can programme with high density. It including 64 registers, 32 universal I/O jacks,4 special inputs, 3 special time clock inputs. It is integrated with input bus unit, output bus unit and system bus unit. The main function of ISP LSI2064 is controlling the input and output of separated I/O data by software. In whole system, it is used for controlling and harmonize the data transfer among ES7010, ES6128 and recording chip. When it loading a disc, the signal of chip communicating with ES6128. When it recording a disc, ISP LSI 2064 controlling the communication among ES7010, ES6128 and recording chip.
I/0 5
Big module
Input bus unit
Output circuit assemble
B7 B6 B5 B4
I/0 0 I/0 1 I/0 2 I/0 3
I/0 7
I/0 6
I/0 4
TDO/IN0 TDO/IN1
BSCAN
In pu t b u s unit
O u t p u t c i r c u i t assemble
A0
A1
A2
A3
Mutual circuit assemble
A4 A5 A6
Output circuit assemble
I/O 11
I/O 10
I/O 9
I/O 8
Input bus unit
I/O 12I/O13I/O 15I/O14
Figure 3ISPLSI 2064 interior diagram
B3
B2
B1
B0
A7
CLK0CLK1CLK2
O u t p u t c i r c u i t
In p ut
assemble
b u s unit
I/0 23 I/0 22 I/0 21 I/0 20
I/0 19 I/0 18 I/0 17 I/0 16
GOE0/IN3 TMS/IN 2
ES6128 is a integration with single chip and MPEG video decoder. It composites progressive video decoding function to make the picture more clear and more real. The main frequency of it is 27MHz. ES6128 can deal the audio data signal and can encode TV signal, it including 4 video DACs and supports Marovision anti-copy function. At the same time, is has DVD system induct function, system control function and manage function. It based on double CPU that is programmable multiplayer, including 32 bits RISC, 64 bits DSP (digital signal processor). The double processor can be connected through two separated data bus. Every processor has its own direct memorizer DMA and outside memorizer jacks. When the system is encoding and decoding, double processor can execute the system command and data dealing. It not only supports parallel ATAPI chip ports but also supports serial ATAPI chip ports, this will makes the audio/video data signal input be possible. The standard I2S audio data will be input to DACs and output to ADCs. High speed EPROM, SDRAM command
access, audio/video data buffer. It supports DVDSVCD, VCD1.1VCD2.0Karaoke CDMP3. Following is the interior diagram of ES6128:
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