AUO P650HVN02.5 Specification
P650HVN02.5 Product Specification
Rev. 0.0
Model Name: P650HVN02.5
Issue Date: 2013/03/28
(＊＊＊＊)Preliminary Specifications
()Final Specifications
Customer Signature Date AUO Date
Approved By
_________________________________
Note
Reviewed By PM Director
Paley Fang
____________________________________
Reviewed By RD Director
Eugene CC Chen
____________________________________
Reviewed By Project Leader
Dalon Tseng
____________________________________
Prepared By PM
Antonio Kuo
____________________________________
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 1 / 32
P650HVN02.5 Product Specification
Rev. 0.0
Contents
Record of Revision .................................................................................................................. 3
1. General Description .......................................................................................................... 4
2. Absolute Maximum Ratings ............................................................................................. 5
3. Electrical Specification ........................................................................................................ 6
3.1.1 Electrical Characteristics ........................................................................................ 6
3.1.2 AC Characteristics ................................................................................................... 6
3.3 Signal Timing Specification ..................................................................................... 13
3.4 Signal Timing Waveforms ........................................................................................ 14
3.5 Color Input Data Reference...................................................................................... 15
3.6 Power Sequence ....................................................................................................... 16
3.7 Backlight Specification............................................................................................. 17
3.7.1 Electrical specification .................................................................................. 17
3.7.2 Input Pin Assignment ..................................................................................... 18
4. Optical Specification.......................................................................................................... 20
5. Mechanical Characteristics ............................................................................................... 23
5.1 Placement suggestions:........................................................................................... 23
Front View................................................................................................................. 24
Back View ................................................................................................................. 25
6. Reliability Test Items.......................................................................................................... 26
7. International Standard ....................................................................................................... 27
8. Packing ............................................................................................................................... 28
8-1 DEFINITION OF LABEL: ........................................................................................... 28
8-2 PACKING METHODS: ............................................................................................... 29
8-3 Pallet and Shipment Information ............................................................................. 30
9. PRECAUTIONS ................................................................................................................... 31
9-1 MOUNTING PRECAUTIONS ..................................................................................... 31
9-2 OPERATING PRECAUTIONS.................................................................................... 31
9-3 ELECTROSTATIC DISCHARGE CONTROL ............................................................. 32
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE ................................................ 32
9-5 STORAGE .................................................................................................................. 32
9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM............................................ 32
9-7 OPERATING CONDITION in PID APPLICATION...................................................... 32
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 2 / 32
Record of Revision
P650HVN02.5 Product Specification
Rev. 0.0
Version
0.0 2013/03/28
Date Page Description
First release
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 3 / 32
P650HVN02.5 Product Specification
Rev. 0.0
1. General Description
This specification applies to the 64.5 inch Color TFT-LCD Module P650HVN02.5. This LCD module has a TFT
active matrix type liquid crystal panel 1920 x 1080 pixels, and diagonal size of 64.5 inch. This module supports
1920 x 1080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each
dot.
The P650HVN02.5 has been designed to apply the 10-bit 2 channel LVDS interface method. It is intended to
support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very
important.
* General Information
Items Specification Unit Note
Active Screen Size 64.53 inch
Display Area 1428.48 (H) x 803.52 (V) mm
Outline Dimension 1508.0(H) x 878.0(V) x 12.8(D) mm
Driver Element a-Si TFT active matrix
Display Colors 10 bit, 1.07B Colors
Number of Pixels 1920 x 1080 Pixel
Pixel Pitch 0.744 mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Surface Treatment Anti-Glare, 3H Haze 11%
Display Orientation Portrait/Landscape Enable
Note:
[1] Please refer to 5.1 Placement Suggestions.
[1]
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 4 / 32
P650HVN02.5 Product Specification
2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 4 [Volt] Note 1
Operating Temperature TOP 0 +50 [oC] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
Storage Temperature TST -20 +60 [oC] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
Panel Surface Temperature PST 65 [oC] Note 3
Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.℃
Rev. 0.0
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures
greater than 40 , the wet℃ bulb temperature must not exceed 39 .℃
Note 3: Surface temperature is measured at 50℃ Dry condition
℃
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 5 / 32
P650HVN02.5 Product Specification
Rev. 0.0
3. Electrical Specification
The P650HVN02.5 requires two power inputs. One is employed to power the LCD electronics and to drive the
TFT array and liquid crystal. The second is employed for LED driver.
3.1.1 Electrical Characteristics
Parameter Symbol
LCD
Power Supply Input Voltage VDD 10.8 12 13.2 VDC
Power Supply Input Current IDD --
Power Consumption PC -- 6.96 13.2 Watt 1
Inrush Current I
Permissible Ripple of Power Supply Input
Voltage
(for input power=12V)
Input Differential Voltage
Differential Input High Threshold
LVDS
Interface
Voltage
Differential Input Low Threshold
Voltage
Input Common Mode Voltage
RUSH
VRP -- -- VDD * 5%
∣
V
∣
ID
VTH +100 -- +300 mVDC 4
V
TL
V
ICM
Min. Typ. Max
- -- 7.5 A 2
200 400 600 mVDC 4
-300 -- -100 mV
1.1
Value
0.58 1.1
1.25
1.4
Unit Note
A 1
mV
V
pk-pk
DC
DC
3
4
4
CMOS
Input High Threshold Voltage
Interface
Input Low Threshold Voltage
Backlight Power Consumption PBL -- 206.4 216.1 W
Life Time(MTTF) 50,000
VIH
2.7 -- 3.3 VDC
(High)
VIL
0 -- 0.6 VDC
(Low)
-- -- -- 6, 7
3.1.2 AC Characteristics
Value
--
--
--
--
Fclk
+3%
200
0.4
0.5
Unit Note
MHz
KHz
ns
10
LVDS
Interface
Parameter Symbol
Input Channel Pair Skew Margin t
Receiver Clock : Spread Spectrum
Modulation range
Receiver Clock : Spread Spectrum
Modulation frequency
Receiver Data Input Margin
Fclk = 85 MHz
Fclk = 65 MHz
SKEW (CP)
Fclk_ss
Fss
tRMG
Min. Typ. Max
-500 -- +500 ps 8
Fclk
-3%
30
-0.4
-0.5
5
9
9
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 6 / 32
s
µ
Note :
P650HVN02.5 Product Specification
Rev. 0.0
1. T V
= 12.0V, Fv = 60Hz, Fclk= Max freq. , 25 ℃, Test Pattern : White Pattern
DD
>> refer to “Section:3.3 Signal Timing Specification, Typical timing”
2. Measurement condition : Rising time = 400us
GND
GND
GNDGND
10%
400
400
400400
3. Test Condition:
(1) The measure point of V
is in LCM side after connecting the System Board and LCM.
RP
(2) Under Max. Input current spec. condition.
4. V
= 1.25V
ICM
L V D S -
V
IC M
L V D S +
90%
VVVV
DD
DD
DDDD
V
T H
|VID|
V
T L
G N D
|VID|
0 V
|VID|
5. The measure points of V
6. The relative humidity must not exceed 80% non-condensing at temperatures of 40 or less. At
temperatures greater than 40 , the wet bulb temperature must not exceed 39 . When operat
temperatures, the brightness of LED will drop and the life time of LED will be reduced.
7. The lifetime (MTTF) is defined as the time which luminance of LED is 50% compared to its original value.
[Operating condition: Continuous operating at Ta = 25±2℃]
8.
Input Channel Pair Skew Margin
and V
IH
are in LCM side after connecting the System Board and LCM.
IL
℃ ℃
℃
img at low
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 7 / 32
P650HVN02.5 Product Specification
Note: x = 0, 1, 2, 3, 4
9. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures
1111////FFFF
SS
SS
SSSS
Fclk
Fclk____ss
FclkFclk
ss((((max
max))))
ssss
maxmax
Rev. 0.0
Fclk
Fclk
FclkFclk
Fclk
Fclk____ss
FclkFclk
ss((((min
min))))
ssss
minmin
10. Receiver Data Input Margin
Parameter Symbol
Min Type Max
Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz
Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns
Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns
Input Data Position2 tRIP6 2T/7-|tRMG|
Input Data Position3 tRIP5 3T/7-|tRMG|
Input Data Position4 tRIP4 4T/7-|tRMG|
Input Data Position5 tRIP3 5T/7-|tRMG|
Input Data Position6 tRIP2 6T/7-|tRMG|
Rating
Unit
2T/7 2T/7+|tRMG| ns
3T/7 3T/7+|tRMG| ns
4T/7 4T/7+|tRMG| ns
5T/7 5T/7+|tRMG| ns
6T/7 6T/7+|tRMG| ns
Note
T=1/Fclk
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 8 / 32
LVDS-Rx
Input Data
LVDS-Rx
Input Clock
tRIP2
tRIP3
tRIP4
tRIP5
tRIP6
tRIP0
tRIP1
P650HVN02.5 Product Specification
Rev. 0.0
Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6Rx2Rx3
VVVV
=
= 0000VVVV
= =
diff
diff
diff diff
1/Fclk=T
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 9 / 32
3.2 Interface Connections
LCD connector : FI-RE51S-HF (Manufactured by JAE);
Mating connector: FI- RE51S-HL (Manufactured by JAE)
P650HVN02.5 Product Specification
Rev. 0.0
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Symbol Description PIN
Reserve AUO Internal Use Only 26
Reserve AUO Internal Use Only 27
Reserve AUO Internal Use Only 28
Reserve AUO Internal Use Only 29
Open/High(3.3V) for 10bit,
BITSEL
Low(GND) for 8bit
Reserve AUO Internal Use Only 31
Open/High(3.3V) for NS,
LVDS_SEL
Low(GND) for JEIDA
Reserve AUO Internal Use Only 33
Reserve AUO Internal Use Only 34
Reserve AUO Internal Use Only 35
GND Ground 36
CH1_0-
CH1_0+
CH1_1-
LVDS Channel 1, Signal 0- 37
LVDS Channel 1, Signal 0+ 38
LVDS Channel 1, Signal 1- 39
30
32
Symbol Description
GND Ground
GND Ground
CH2_0-
CH2_0+
CH2_1-
CH2_1+
CH2_2-
CH2_2+
LVDS Channel 2, Signal 0-
LVDS Channel 2, Signal 0+
LVDS Channel 2, Signal 1-
LVDS Channel 2, Signal 1+
LVDS Channel 2, Signal 2-
LVDS Channel 2, Signal 2+
GND Ground
CH2_CLK-
CH2_CLK+
LVDS Channel 2, Clock -
LVDS Channel 2, Clock +
GND Ground
CH2_3-
CH2_3+
LVDS Channel 2, Signal 3-
LVDS Channel 2, Signal 3+
15
16
17
18
19
20
21
22
23
24
25
CH1_1+
CH1_2-
CH1_2+
LVDS Channel 1, Signal 1+ 40
LVDS Channel 1, Signal 2- 41
LVDS Channel 1, Signal 2+ 42
GND Ground 43
CH1_CLK-
CH1_CLK+
LVDS Channel 1, Clock - 44
LVDS Channel 1, Clock + 45
GND Ground 46
CH1_3-
CH1_3+
CH1_4-
CH1_4+
LVDS Channel 1, Signal 3- 47
LVDS Channel 1, Signal 3+ 48
LVDS Channel 1, Signal 4- 49
LVDS Channel 1, Signal 4+ 50
51
CH2_4-
CH2_4+
LVDS Channel 2, Signal 4-
LVDS Channel 2, Signal 4+
GND Ground
GND Ground
GND Ground
GND Ground
GND Ground
Reserve AUO Internal Use Only
VDD Power Supply, +12V DC Regulated
VDD Power Supply, +12V DC Regulated
VDD Power Supply, +12V DC Regulated
VDD Power Supply, +12V DC Regulated
Note 1: All GND (ground) pins should be connected together and should also be connected to the LCD’s
metal frame.
Note 2: All VDD (power input) pins should be connected together.
Note 3: All Reserved pins should be open without voltage input.
© Copyright AU Optronics Corp. 2013 All Rights Reserved. Page 10 / 32
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