AUO P645HVN02.2 Specification

P645HVN02.2 Product Specification

Rev. 5.0

Model Name: P650HVN02.2

Issue Date : 2012/4/12

( )Preliminary Specifications

(＊＊＊＊)Final Specifications

Customer Signature Date AUO Date

Approved By

_________________________________

Note

Approval By PM Director

Michael Goan

____________________________________

Reviewed By RD Director

Eugene Chen

____________________________________

Reviewed By Project Leader

Alex HM Chen

____________________________________

Prepared By PM

Antonio Kuo

____________________________________

P645HVN02.2 Product Specification

Rev. 5.0

Contents

No

CONTENTS

RECORD OF REVISIONS

1 GENERAL DESCRIPTION

2 ABSOLUTE MAXIMUM RATINGS

3 ELECTRICAL SPECIFICATION

3-1 ELECTRIACL CHARACTERISTICS

3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATION

3-4 SIGNAL TIMING WAVEFORM

3-5 COLOR INPUT DATA REFERENCE

3-6 POWER SEQUENCE

3-7 BACKLIGHT SPECIFICATION

4 OPTICAL SPECIFICATION

5 MECHANICAL CHARACTERISTICS

6 RELIABILITY TEST ITEMS

7 INTERNATIONAL STANDARD

7-1 SAFETY

7-2 EMC

8 PACKING

8-1 DEFINITION OF LABEL

8-2 PACKING METHODS

8-3 PALLET AND SHIPMENT INFORMATION

9 PRECAUTION

9-1 MOUNTING PRECAUTIONS

9-2 OPERATING PRECAUTIONS

9-3 ELECTROSTATIC DISCHARGE CONTROL

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

9-5 STORAGE

9-6 HANDLING PRECAUTIONS FOR PROTECT FILM

Record of Revision

P645HVN02.2 Product Specification

Rev. 5.0

Version

1.0 2011/12/19

2.0 2012/1/4 6

6 Note1,3,5

11 Time Table (modified in red color)

15 3.8.1 Electrical specification & Note

16

17

18 Response Time: 5.5ms => 8ms

3.0 2012/1/13

26 Carton Label: Part No. 97.65P02.XXX=>97.65P02.200

4.0 2012/2/7 22 Add Front bezel to cell: 2.6 Max.

24 Item 5, 6

26 Qty: 6 => 4

Date Page Description

First release

IDD: Typ 1.56=>0.58 Max:1.93=>1.11

PC: Typ 18.72=>6.96 Max:23.16=>13.2

PBL: Typ 209.6=>208.8 Max:229.6=>224.9

modified in red color

18 Rx: 0.640=> 0.630 Gx:0.310=>0.320 By: 0.050=>0.040

27,28 All

5.0 2012/4/12

23 Mark user holes “H” on Back View Drawing

P645HVN02.2 Product Specification

Rev. 5.0

1. General Description

This specification applies to the 64.5 inch Color TFT-LCD Module P650HVN02.2. This LCD module has a TFT

active matrix type liquid crystal panel 1920 x 1080 pixels, and diagonal size of 64.5 inch. This module supports

1920 x 1080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical

stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each

dot.

The P650HVN02.2 has been designed to apply the 10-bit 2 channel LVDS interface method. It is intended to

support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very

important.

* General Information

Items Specification Unit Note

Active Screen Size 64.53 inch

Display Area 1428.48 (H) x 803.52 (V) mm

Outline Dimension 1508.0(H) x 878.0(V) x 12.8(D) mm

Driver Element a-Si TFT active matrix

Display Colors 10 bit, 1.07B Colors

Number of Pixels 1920 x 1080 Pixel

Pixel Pitch 0.744 mm

Pixel Arrangement RGB vertical stripe

Display Operation Mode Normally Black

Surface Treatment Anti-Glare, 3H Haze 2%

P645HVN02.2 Product Specification

2. Absolute Maximum Ratings

The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit

Item Symbol Min Max Unit Conditions

Logic/LCD Drive Voltage VDD -0.3 14 [Volt] Note 1

Input Voltage of Signal Vin -0.3 4 [Volt] Note 1

Operating Temperature TOP 0 +50 [oC] Note 2

Operating Humidity HOP 10 90 [%RH] Note 2

Storage Temperature TST -20 +60 [oC] Note 2

Storage Humidity HST 10 90 [%RH] Note 2

Panel Surface Temperature PST - 65 [oC] Note 3

Note 1: Duration:50 msec.

Note 2 : Maximum Wet-Bulb should be 39 and No condensation.℃

Rev. 5.0

The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures

greater than 40 , the wet bulb temperature must not exceed 39 .

Note 3: Surface temperature is measured at 50℃ Dry condition

℃ ℃

℃

s

µ

P645HVN02.2 Product Specification

Rev. 5.0

3. Electrical Specification

The P650HVN02.2 requires two power inputs. One is employed to power the LCD electronics and to drive the TFT

array and liquid crystal. The second input for BLU is to LED driver.

3.1 Electrical Characteristics

3.1.1: DC Characteristics

Parameter Symbol

Min. Typ. Max

LCD

Power Supply Input Voltage VDD 10.8 12.0 13.2 VDC 1

Power Supply Input Current IDD --

Power Consumption PC --

Inrush Current I

Input Differential Voltage

LVDS

Interface

CMOS

Interface

Differential Input High Threshold Voltage VTH +100 -- +300 4 4

Differential Input Low Threshold Voltage VTL -300 -- -100 4 4

Input Common Mode Voltage V

Input High Threshold Voltage

Input Low Threshold Voltage

-- -- 7.5 A 3

RUSH

∣

V

∣

ID

1.10 1.25 1.40 VDC 4

ICM

VIH

(High)

VIL

(Low)

200 400 600 mVDC 4

2.7 -- 3.3 VDC --

0 -- 0.6 VDC --

Value

0.58

6.96

Unit Note

1.1

13.2

A 2

Watt 2

Backlight Power Consumption PBL -- 208.8

Life Time 30,000

Note :

1. Test Condition:

(1) V (2) Fv = Type Timing, 60Hz (3) Fclk= Max freq. (4) Temperature = 25 ℃ (5) Typ. Input current : White Pattern

2. Measurement condition : Rising time = 400us

= 12.0V

DD

Max. Input current: Heavy loading pattern defined by AUO

VVVV

DD

DDDD

GND

GNDGND

10%

400

400400

90%

-- Hours

224.9 Watt --

--

3. Test Condition:

(1) The measure point of V (2) Under Max. Input current spec. condition.

4. V

= 1.25V

ICM

L V D S -

V

L V D S +

IC M

G N D

0 V

P645HVN02.2 Product Specification

is in LCM side after connecting the System Board and LCM.

RP

V

T H

V

T L

|VID|

Rev. 5.0

|VID|

5. The measure points of V

and V

IH

are in LCM side after connecting the System Board and LCM

IL

3.1.2: AC Electrical Characteristics

Parameter Symbol

Input Channel Pair Skew Margin t

Receiver Clock : Spread Spectrum

LVDS Interface

Modulation range

Receiver Clock : Spread Spectrum Modulation frequency

Receiver Data Input Margin Fclk = 85 MHz Fclk = 65 MHz

1. Input Channel Pair Skew Margin

SKEW (CP)

Fclk_ss

Fss

tRMG

Value

Min. Typ. Max

-500 -- +500 ps 1

Fclk

-3%

30

-0.4

-0.5

--

Fclk

+3%

200

0.4

0.5

Unit Note

MHz

2

KHz

2

ns

3

Note: x = 0, 1, 2, 3, 4

P645HVN02.2 Product Specification

2. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures

1111////FFFF

SS

SSSS

Fclk

Fclk____ss

FclkFclk

3. Receiver Data Input Margin

ss((((max

ssss

Fclk

FclkFclk

Fclk

Fclk____ss

FclkFclk

ss((((min

ssss

max))))

maxmax

min))))

minmin

Rev. 5.0

Parameter Symbol

Min Type Max

Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz

Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns

Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns

Input Data Position2 tRIP6 2T/7-|tRMG|

Input Data Position3 tRIP5 3T/7-|tRMG|

Input Data Position4 tRIP4 4T/7-|tRMG|

Input Data Position5 tRIP3 5T/7-|tRMG|

Input Data Position6 tRIP2 6T/7-|tRMG|

Rating

Unit

2T/7 2T/7+|tRMG| ns

3T/7 3T/7+|tRMG| ns

4T/7 4T/7+|tRMG| ns

5T/7 5T/7+|tRMG| ns

6T/7 6T/7+|tRMG| ns

tRIP2

tRIP3

tRIP4

tRIP5

tRIP6

Note

T=1/Fclk

tRIP0

tRIP1 LVDS-Rx Input Data

Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6Rx2Rx3

LVDS-Rx

VVVV

=

= 0000VVVV

= =

diff

Input Clock

diff diff

1/Fclk=T

3.2 Interface Connections

LCD connector: FI-RE51S-HF (Manufactured by JAE)

Mating connector: FI-RE51S-HL (Manufactured by JAE)

P650HVN02.2 Product Specification

Rev.5.0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Symbol Description PIN

Reserve AUO Internal Use Only 26

Reserve AUO Internal Use Only 27

Reserve AUO Internal Use Only 28

Reserve AUO Internal Use Only 29

BITSEL

Reserve AUO Internal Use Only 31

LVDS_SEL

Reserve AUO Internal Use Only 33

Reserve AUO Internal Use Only 34

Reserve AUO Internal Use Only 35

GND Ground 36

CH1_0-

CH1_0+

CH1_1-

Open/High(3.3V) for 10bit,

Low(GND) for 8bit

Open/High(3.3V) for NS,

Low(GND) for JEIDA

LVDS Channel 1, Signal 0- 37

LVDS Channel 1, Signal 0+ 38

LVDS Channel 1, Signal 1- 39

30

32

Symbol Description

GND Ground

CH2_0-

CH2_0+

CH2_1-

CH2_1+

CH2_2-

CH2_2+

GND Ground

CH2_CLK-

CH2_CLK+

GND Ground

CH2_3-

CH2_3+

LVDS Channel 2, Signal 0-

LVDS Channel 2, Signal 0+

LVDS Channel 2, Signal 1-

LVDS Channel 2, Signal 1+

LVDS Channel 2, Signal 2-

LVDS Channel 2, Signal 2+

LVDS Channel 2, Clock -

LVDS Channel 2, Clock +

LVDS Channel 2, Signal 3-

LVDS Channel 2, Signal 3+

15

16

17

18

19

20

21

22

23

24

25

CH1_1+

CH1_2-

CH1_2+

GND Ground 43

CH1_CLK-

CH1_CLK+

GND Ground 46

CH1_3-

CH1_3+

CH1_4-

CH1_4+

LVDS Channel 1, Signal 1+ 40

LVDS Channel 1, Signal 2- 41

LVDS Channel 1, Signal 2+ 42

LVDS Channel 1, Clock - 44

LVDS Channel 1, Clock + 45

LVDS Channel 1, Signal 3- 47

LVDS Channel 1, Signal 3+ 48

LVDS Channel 1, Signal 4- 49

LVDS Channel 1, Signal 4+ 50

51

CH2_4-

CH2_4+

GND Ground

Reserve AUO Internal Use Only

VDD Power Supply, +12V DC Regulated

LVDS Channel 2, Signal 4-

LVDS Channel 2, Signal 4+

Note 1: All GND (ground) pins should be connected together and should also be

connected to the LCD’s metal frame.

Note 2: All VDD (power input) pins should be connected together.

Note 3: All Reserved pins should be open without voltage input.

LVDS Option = High/OpenNS

P re vio u s C yc le C ur r e nt C y c le N ex t C yc l e

P re vio u s C yc le C ur r e nt C y c le N ex t C yc l e P re vio u s C yc le C ur r e nt C y c le N ex t C yc l e

C lo c k

C lo c kC lo c k

C H x

C H x ____ 0000 ++++

C H xC H x C H x

C H x ____ 0000 ----

C H xC H x

C H x

C H x ____ 1111 ++++

C H xC H x C H x

C H x ____ 1111 ----

C H xC H x

C H x

C H x ____ 2222 ++++

C H xC H x C H x

C H x ____ 2222 ----

C H xC H x

D EBBBB 2222BBBB 3333 BBBB 4444BBBB 5555N A

D ED E

P650HVN02.2 Product Specification

RRRR 0000RRRR 5555 GGGG 0000GGGG 0000RRRR 0000RRRR 1111 RRRR 2222RRRR 3333RRRR 4444 RRRR 1111

GGGG 1111BBBB 0000 BBBB 1111BBBB 1111GGGG 1111GGGG 2222 GGGG 3333GGGG 4444GGGG 5555 GGGG 2222

N A D E

N AN A

N A BBBB 3333

N AN A

BBBB 2222N A

D ED E

Rev.5.0

C H x

C H x ____ 3333 ++++

C H xC H x C H x

C H x ____ 3333 ----

C H xC H x

C H x

C H x ____ 4444 ++++

C H xC H x C H x

C H x ____ 4444 ----

C H xC H x

N ARRRR 6666RRRR 7777 GGGG 6666GGGG 7777BBBB 6666 RRRR 7777

N AN A

N ARRRR 8888RRRR 9999 GGGG 8888GGGG 9999BBBB 8888 RRRR 9999

N AN A

Note: x = 1, 2, 3, 4…

LVDS Option = LowJEIDA

P re v io u s C y c le C ur r e nt C yc l e N e x t C yc le

P re v io u s C y c le C ur r e nt C yc l e N e x t C yc le P re v io u s C y c le C ur r e nt C yc l e N e x t C yc le

C lo c k

C lo c kC lo c k

C Hx

C Hx ____ 0000 ++++

C HxC Hx C Hx

C Hx ____ 0000 ----

C HxC Hx

C Hx

C Hx ____ 1111 ++++

C HxC Hx C Hx

C Hx ____ 1111 ----

C HxC Hx

RRRR 6666BBBB 7777 N A

RRRR 8888BBBB 9999 N A

N AN A

RRRR 4444RRRR 9999 GGGG 4444GGGG 4444RRRR 4444RRRR 5555 RRRR 6666RRRR 7777RRRR 8888 RRRR 5555

GGGG 5555BBBB 4444 BBBB 5555BBBB 5555GGGG 5555GGGG 6666 GGGG 7777GGGG 8888GGGG 9999 GGGG 6666

C Hx

C Hx ____ 2222 ++++

C HxC Hx C Hx

C Hx ____ 2222 ----

C HxC Hx

C Hx

C Hx ____ 3333 ++++

C HxC Hx C Hx

C Hx ____ 3333 ----

C HxC Hx

C Hx

C Hx ____ 4444 ++++

C HxC Hx C Hx

C Hx ____ 4444 ----

C HxC Hx

D EBBBB 6666BBBB 7777 BBBB 8888BBBB 9999N A

D ED E

N ARRRR 2222RRRR 3333 GGGG 2222GGGG 3333BBBB 2222 RRRR 3333

N AN A

N ARRRR 0000RRRR 1111 GGGG 0000GGGG 1111BBBB 0000 RRRR 1111

N AN A

N A D E

N AN A

N A BBBB 7777

N AN A

BBBB 6666N A

RRRR 2222BBBB 3333 N A

RRRR 0000BBBB 1111 N A

D ED E

N AN A

Note: x = 1, 2, 3, 4…

P650HVN02.2 Product Specification

Rev.5.0

3.3 Signal Timing Specification

This is the signal timing required at the input of the user connector. All of the interface signal timing should be

satisfied with the following specifications for its proper operation.

Timing Table (DE only Mode)

Signal Item Symbol Min. Typ. Max Unit

Period Tv 1096

Vertical Section

Horizontal Section

Clock Frequency Fclk=1/Tclk 50

Vertical Frequency Frequency Fv 47

Horizontal Frequency Frequency Fh 60

Notes:

(1) Display position is specific by the rise of DE signal only.

Horizontal display position is specified by the rising edge of 1st DCLK after the rise of 1st DE, is displayed on the

left edge of the screen.

(2) Vertical display position is specified by the rise of DE after a “Low” level period equivalent to eight times of

horizontal period. The 1st data corresponding to one horizontal line after the rise of 1st DE is displayed at the top

Active Tdisp (v) 1080

Blanking Tblk (v) 16

Period Th 1040

Active Tdisp (h) 960

Blanking Tblk (h) 80

1125

45

1100

140

74.25

60

67.5

1480

400

1328

368

82

63

73

Th

Tclk

MHz

Hz

KHz

line of screen.

(3) If a period of DE “High” is less than 1920 DCLK or less than 1080 lines, the rest of the screen displays black.

(4) The display position does not fit to the screen if a period of DE “High” and the effective data period do not

synchronize with each other.

3.4 Signal Timing Waveforms

P650HVN02.2 Product Specification

Rev.5.0

CH2

Pixel

M-6

Pixel

M-4

Pixel

M-2

Pixel

M

Invalid Data

Pixel

2

Pixel

4

Pixel

6

Pixel

8

Pixel

10

Pixel

12

CH1

Pixel

M-7

Pixel

M-5

Pixel

M-3

Pixel

M-1

Invalid Data

Pixel

1

Pixel

3

Pixel

5

Pixel

7

Pixel

9

Pixel

11

DE

Tdisp(h) Tblk(h)

CLK

RGB

Data

Line

N

Tclk

Invalid Data Invalid Data

Line

1

Line

2

Th

Line

3

Line

4

DE

Th

Tv

Tdisp(v)Tblk(v)

Pixel

M-4

Pixel

M-2

Pixel

M

Invalid Data

Pixel

2

Pixel

4

Pixel

M-5

Pixel

M-3

Pixel

M-1

Invalid Data

Pixel

1

Pixel

3

Line

N

N L in e

N L in eN L in e

M

M p

p

p i

i

x

x e

e

e l

l

Basic

P650HVN02.2 Product Specification

Rev.5.0

3.5 Color Input Data Reference

The brightness of each primary color (red, green and blue) is based on the 10 bit gray scale data input for the color;

the higher the binary input, the brighter the color. The table below provides a reference for color versus data input.

Color Data Reference

Input Color Data

Color

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Green(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

Blue(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Color

Cyan 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Magenta 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

RED(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED(001) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R

----

RED(1022) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

RED

MSB LSB

GREEN

BLUE

MSB LSB

GREEN(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GREEN(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

G

----

GREEN(1022) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

GREEN(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

BLUE(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

B

----

BLUE(1022) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0

BLUE(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

3.6 Power Sequence for LCD (TBD)

P650HVN02.2 Product Specification

Rev.5.0

Pow er Sup p ly For LCD

Pow er Sup p ly For LCD Pow er Sup p ly For LCD VD D

VD D (+

(+ 12

12 VVVV ))))

VD D VDD

(+(+

121 2

In ter fa c e Sig n a l

In ter fa c e Sig n a lIn ter fa c e Sig n a l ((((LV DS D a ta

LV DS D a ta &

LV DS D a ta LV DS D a ta

& C LK

CLK ))))

& &

CLKCLK

G ND

Back lig h t o n

Back lig h t o n ////o ff

Back lig h t o nBackl ig h t o n co n tro l sig n a l

co n tro l sig n a l

co n tro l sig n a lco n tro l sig n a l ((((VBLO N

VBLO N ))))

VBLO NVBLO N

off

offoff

GN D

CM O S In terface S ign a l

CM O S In terface S ign a lCM O S In terface S ign a l

G ND

Parameter

t1 0.4 --- 30 ms

10 %

90 %

t1

t2

Valid D ata

Valid D ataV a lid D ata

t3 t4

t8 t9

Values

Min. Type. Max.

90 %

10 %

t6

t5

10 %

t7

Unit

t2 0.1 --- 50 ms

t3 450 --- --- ms

t4 0*1 --- --- ms

t5 0 --- --- ms

t6 --- --- ---*2 ms

t7 500 --- --- ms

t8

10*3

--- 50 ms

t9 0 --- --- ms

Note: (1) t4=0 : concern for residual pattern before BLU turn off. (2) t6 : voltage of VDD must decay smoothly after power-off. (customer system decide this value) (3) When CMOS Interface signal is N.C. (no connection), opened in Transmitted end, t8 timing spec can be

negligible.

3.8 Backlight Specification

The backlight unit contains 8pcs LED lightbar

3.8.1 Electrical specification

Item Symbol Condition

P650HVN02.2 Product Specification

Rev.5.0

Spec

Unit Note

Min Typ Max

1

2

3

4

Input Voltage VDDB - 22.8

Input Current I

Input Power P

Inrush Current I

VDDB=24V

DDB

VDDB=24V

DDB

VDDB=24V

RUSH

8.7 9.37

208.8 224.9

13

ON 2 - 5.5 -

5 On/Off control voltage

6 On/Off control current

External PWM Duty ratio

7

8

(input duty ratio)

External PWM

Frequency

V

BLON

OFF

I

VDDB=24V

BLON

D_EPWM VDDB=24V

VDDB=24V

0 - 0.8

- - 1.5 mA -

0 - 100 % 4,5

F_EPWM VDDB=24V 110 180 240 Hz 4,5

HI Open Collector VDC 6

9

10

DET status signal DET

Lo

VDDB=24V

0 - 0.8 VDC 6

Input Impedance Rin VDDB=24V 300 Kohm

Note 1 : Dimming ratio= 100% (MAX)（Ta=25±5℃, Turn on for 45minutes）

24 25.2

VDC -

ADC

(rms)

W 1

ADC

(peak)

VDC

1

2

3

Note 2: MAX input current at all operating mode, measurement condition Rising time = 20ms (VDDB: 10%~90%)

Note 3: When BLU off ( VDDB = 24V , VBLON = 0V) , IDDB (max) = 0.1A

Note 4: Less than 5% dimming control is functional well and no backlight shutdown happened

Note 5: D_EPWM and F_EPWM are available only at 2D mode

Note 6: Normal : 0~0.8V ; Abnormal : Open collector

P650HVN02.2 Product Specification

3.8.2 Input Pin Assignment

14pin pin assignment

Connector: CI0114M1HR0-NH(CviLux) or equivalent

Pin NO. Symbol Pin Configuration (function)

1 VDDB Operating Voltage Supply, +24V DC regulated 2 VDDB Operating Voltage Supply, +24V DC regulated 3 VDDB Operating Voltage Supply, +24V DC regulated 4 VDDB Operating Voltage Supply, +24V DC regulated 5 VDDB Operating Voltage Supply, +24V DC regulated 6 BLGND Ground and Current Return 7 BLGND Ground and Current Return 8 BLGND Ground and Current Return 9 BLGND Ground and Current Return

10 BLGND Ground and Current Return

BLU status detection:

11 DET

12 VBLON

Normal : 0~0.8V ; Abnormal : Open collector

(Recommend Pull high R > 10K, VDD = 3.3V)

BL On-Off control

High/Open (2.0V~5.5V) for BL On,

Low (0~0.8V/GND) for BL off

Rev.5.0

13 NC NC

14 PDIM (*) External PWM (0%~100% Duty, open for 100%)

12pin pin assignment

Connector: CI0112M1HR0-NH(CviLux) or equivalent

Pin NO. Symbol Pin Configuration (function)

1 VDDB Operating Voltage Supply, +24V DC regulated 2 VDDB Operating Voltage Supply, +24V DC regulated 3 VDDB Operating Voltage Supply, +24V DC regulated 4 VDDB Operating Voltage Supply, +24V DC regulated 5 VDDB Operating Voltage Supply, +24V DC regulated 6 BLGND Ground and Current Return 7 BLGND Ground and Current Return 8 BLGND Ground and Current Return 9 BLGND Ground and Current Return

10 BLGND Ground and Current Return

11 NC

12 NC NC

NC

(Note*) If External PWM function is less than 5% dimming ratio. Judge condition as below:

(1) Backlight module must be lighted ON normally. (2) All protection function must work normally. (3) Uniformity and flicker could NOT be guaranteed

3.8.3 Power Sequence for Backlight

24V(typ.)

T3

Power Input for BLU

(VDDB)

Valid Dimming

Control Signal

(V_IPWM,V_EPWM)

90% 90%

10%

T1 T2

P650HVN02.2 Product Specification

10%

T7

T5

T4

T6

T7

Rev.5.0

BLU On/Off Enable

(VBLON)

Dip condition for LED Backlight

Power Input for BLU

(VDDB)

VDDB(typ.)*0.8

T8

Parameter

Min Typ Max

T1 20 - - ms *1

T2 500 - - ms

T3 250 - - ms

T4 0 - - ms

T5 1 - - ms

T6 - - ms

T7 500 - - ms

T8 - - 10 ms

Value

Units

Note: 1. T1 describes rising time of 0V to 24V and this parameter does not applied at restarting time. Even though T1 is over the specified value, there is no problem if I2t spec of fuse is satisfied.

P650HVN02.2 Product Specification

Rev.5.0

4. Optical Specification

Optical characteristics are determined after the unit has been ‘ON’ and stable for approximately 45 minutes in a

dark environment at 25°C. The values specified are at an approximate distance 50cm from the LCD surface at a

viewing angle of φ and θ equal to 0°.

Fig.1 presents additional information concerning the measurement equipment and method.

SR3 or equivalent

Parameter Symbol

Min. Typ. Max

Values

Unit Notes

Contrast Ratio(2D) CR 3200 4000 -- 1

Surface Luminance (White) L

Luminance Variation δ

280 360 -- cd/m2 2

WH

WHITE(9P)

-- -- 1.33 3

Response Time (G to G) Tγ -- 8 -- Ms 4

Color Gamut NTSC 72 %

Color Coordinates

Red RX 0.630

RY 0.330

Green GX 0.320

GY 0.620

Typ.-0.03

Typ.+0.03

Blue BX 0.150

BY 0.040

White WX 0.280

WY

0.290

Viewing Angle 5

x axis, right(φ=0°) θr -- 89 -- degree

x axis, left(φ=180°) θl -- 89 -- degree

y axis, up(φ=90°) θu -- 89 -- degree

y axis, down (φ=270°) θd -- 89 -- degree

x axis, left + right θ

100 degree

l +θr

6,7

Note:

1. Contrast Ratio (CR) is defined mathematically as:

2 3

7

P650HVN02.2 Product Specification

Rev.5.0

Surface Luminance of

Contrast Ratio=

Surface Luminance of

2. Surface luminance is luminance value at point 5 across the LCD surface 50cm from the surface with all pixels

displaying white. From more information see FIG 2.

3. The variation in surface luminance, δWHITE is defined (center of Screen) as:

L

on5

off5

δ

WHITE(9P)

= Maximum(L

on1

, L

on2

,…,L

)/ Minimum(L

on9

on1

, L

on2

,…L

on9

)

4. Response time Tγ is the average time required for display transition by switching the input signal for five

luminance ratio (0%,25%,50%,75%,100% brightness matrix) and is based on Fv=60Hz to optimize. From more

information see FIG 3.

Target Measured

Response Time

0% 25% 50% 75% 100%

0% 0% to 25% 0% to 50% 0% to 75% 0% to 100%

25% 25% to 0% 25% to 50% 25% to 75% 25% to 100%

Start

50% 50% to 0% 50% to 25%

75% 75% to 0% 75% to 25% 75% to 50%

50% to 75% 50% to 100%

75% to 100%

100% 100% to 0% 100% to 25% 100% to 50% 100% to 75%

5. Viewing angle is the angle at which the contrast ratio is greater than 10. The angles are determined for the

horizontal or x axis and the vertical or y axis with respect to the z axis which is normal to the LCD surface. For

more information see FIG4.

6. head in 0 degrees vertical angle from mid axis

FIG. 2 Luminance

V

H/2

H/6

1

H

V/2 V/6

FIG.3 Response Time

The response time is defined as the following figure and shall be measured by switching the input signal for “any level of grey(bright) “ and “any level of gray(dark)”.

P650HVN02.2 Product Specification

Any level of gray (Bright) Any level of gray (Dark) Any level of gray (Bright)

Rev.5.0

Photodetector

Output

FIG.4 Viewing Angle

0% , 2 5 % , 5 0% , 7 5 % , 100%

0% , 2 5 % , 5 0% , 75% , 100%

T

γγγγ

(F)

0% , 25 % , 5 0% , 7 5 % , 100%

90%

10%

Tim e

T

γγγγ

(R )

P650HVN02.2 Product Specification

Rev.5.0

5. Mechanical Characteristics

The contents provide general mechanical characteristics for the model P650HVN02.2. In addition the figures in the

next page are detailed mechanical drawing of the LCD.

Horizontal 1508.0mm

Outline Dimension

Bezel Opening

Active Display Area

Weight 32,000 g (Typ.)

Surface Treatment AG, 3H

Vertical 878.0mm

12.8mm

Depth

(thinnest)

Horizontal 1440.6 mm

Vertical 814.6 mm

Horizontal 1428.48 mm

Vertical 803.52 mm

Front View

P650HVN02.2 Product Specification

Rev.5.0

Back View

P650HVN02.2 Product Specification

Rev.5.0

6. Reliability Test Items

P650HVN02.2 Product Specification

Rev.5.0

1 High temperature storage test 3 60℃, 300hrs

2 Low temperature storage test 3 -20℃, 300hrs

3 High temperature operation test 3 50℃, 300hrs

4 Low temperature operation test 3 -5℃, 300hrs

5 Vibration test (With carton)

6 Drop test (With carton)

Test Item Q’ty Condition

Random wave (1.05G RMS, 10-200Hz)

1

(PKG)

10mins/ Per each X,Y,Z axes

Height: 25.4 cm

1

Direction: Only bottom flat twice

(ASTMD4169-I)

7. International Standard

7.1 Safety

(1) UL 60950-1, UL 60065; Standard for Safety of Information Technology Equipment Including

electrical Business Equipment.

(2) IEC 60950-1 : 2001, IEC 60065:2001 ; Standard for Safety of International Electrotechnical

Commission

(3) EN 60950 : 2001+A11, EN 60065:2002+A1:2006; European Committee for Electrotechnical

Standardization (CENELEC), EUROPEAN STANDARD for Safety of Information Technology

Equipment Including Electrical Business Equipment.

7.2 EMC

(1) ANSI C63.4 “Methods of Measurement of Radio-Noise Emissions from Low-Voltage Electrical and

Electrical Equipment in the Range of 9kHz to 40GHz. “American National standards Institute(ANSI),

P650HVN02.2 Product Specification

Rev.5.0

1992

(2) C.I.S.P.R “Limits and Methods of Measurement of Radio Interface Characteristics of Information

Technology Equipment.” International Special committee on Radio Interference.

(3) EN 55022 “Limits and Methods of Measurement of Radio Interface Characteristics of Information

Technology Equipment.” European Committee for Electrotechnical Standardization. (CENELEC),

1998

QTY

:4

Manufactured

XX/XX

MADE IN

X

XXXX

8. Packing

8-1 Definition of Label :

A. Panel Label:

*xxxxxxxxxxxx-xxxx*

P650HVN02.2 Product Specification

Rev.5.0

Panel Unique ID

AUO Internal Use

XXXXX Model NO: P650HVN02.2 XXXXXXX

AUO Internal Use

Week

Year

Green mark description

AU Optronics

Fab Location

AUO Internal Use

(1) For Pb Free Product, AUO will add for identification.

(2) For RoHs compatible products, AUO will add RoHS for identification.

Note: The green Mark will be present only when the green documents have been ready by AUO internal green

team. (definition of green design follows the AUO green design checklist.)

B. Carton Label:

P650HVN02.2

97.65P02.200

4

pcs Modules

1pcs Module/ESD Bag

Cushion top

Module

4

pcs / 1 carton

”

H ” Tape

Cushion down

Cushion set

8-2 Packing Methods:

P650HVN02.2 Product Specification

Rev.5.0

8-3 Pallet and Shipment Information

P650HVN02.2 Product Specification

Rev.5.0

Specification

Item

1 Packing Box 4pcs/box 1605(L)mm*375(W)mm*1025(H)mm 134

2 Pallet 1 1660(L)mm*1150(W)mm*138(H)mm 20

3 Boxes per Pallet 3 boxes/Pallet (By Air) ; 3 Boxes/Pallet (By Sea)

4 Panels per Pallet 12 pcs/pallet(By Air) ; 12 pcs/Pallet (By Sea)

after packing

Qty. Dimension Weight (kg)

12 (by Air) 1660(L)mm*1150(W)mm*1173(H)mm 422(by Air)

24 (by Sea) 1660(L)mm*1150(W)mm*2346(H)mm 844(by Sea) 40ft HQ

Packing

Remark

5 Pallet

9. PRECAUTIONS

Please pay attention to the followings when you use this TFT LCD module.

9-1 MOUNTING PRECAUTIONS

(1) You must mount a module using holes arranged in four corners or four sides.

(2) You should consider the mounting structure so that uneven force (ex. twisted stress) is not applied

to module. And the case on which a module is mounted should have sufficient strength so that

external force is not transmitted directly to the module.

(3) Please attach the surface transparent protective plate to the surface in order to protect the polarizer.

Transparent protective plate should have sufficient strength in order to the resist external force.

(4) You should adopt radiation structure to satisfy the temperature specification.

(5) Acetic acid type and chlorine type materials for the cover case are not desirable because the former

P650HVN02.2 Product Specification

Rev.5.0

generates corrosive gas of attacking the polarizer at high temperature and the latter cause circuit

broken by electro-chemical reaction.

(6) Do not touch, push or rub the exposed polarizer with glass, tweezers or anything harder than HB

pencil lead. And please do not rub with dust clothes with chemical treatment. Do not touch the

surface of polarizer for bare hand or greasy cloth. (Some cosmetics are detrimental to the polarizer.)

(7) When the surface becomes dusty, please wipe gently with absorbent cotton or other soft materials

like chamois soaks with petroleum benzene. Normal-hexane is recommended for cleaning the

adhesives used to attach front/ rear polarizer. Do not use acetone, toluene and alcohol because

they cause chemical damage to the polarizer.

(8) Wipe off saliva or water drops as soon as possible. Their long time contact with polarizer causes

deformations and color fading.

(9) Do not open the case because inside circuits do not have sufficient strength.

9-2 OPERATING PRECAUTIONS

(1) The device listed in the product specification sheets was designed and manufactured for TV

application

(2) The spike noise causes the mis-operation of circuits. It should be lower than following voltage:

V=±200mV(Over and under shoot voltage)

(3) Response time depends on the temperature. (In lower temperature, it becomes longer..)

(4) Brightness of LED depends on the temperature. (In lower temperature, it becomes lower.) And in

lower temperature, response time (required time that brightness is stable after turned on) becomes

longer.

(5) Be careful for condensation at sudden temperature change. Condensation makes damage to

polarizer or electrical contacted parts. And after fading condensation, smear or spot will occur.

(6) When fixed patterns are displayed for a long time, remnant image is likely to occur.

(7) Module has high frequency circuits. Sufficient suppression to the electromagnetic interference shall

be done by system manufacturers. Grounding and shielding methods may be important to minimize

the interface.

9-3 ELECTROSTATIC DISCHARGE CONTROL

Since a module is composed of electronic circuits, it is not strong to electrostatic discharge. Make certain

that treatment persons are connected to ground through wristband etc. And don’t touch interface pin

directly.

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

Strong light exposure causes degradation of polarizer and color filter.

9-5 STORAGE

When storing modules as spares for a long time, the following precautions are necessary.

(1) Store them in a dark place. Do not expose the module to sunlight or fluorescent light. Keep the

P650HVN02.2 Product Specification

Rev.5.0

temperature between 5 and 35 at normal humidity.

(2) The polarizer surface should not come in contact with any other object. It is recommended that they

be stored in the container in which they were shipped.

℃ ℃

9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM

(1) The protection film is attached to the bezel with a small masking tape. When the protection film is

peeled off, static electricity is generated between the film and polarizer. This should be peeled off

slowly and carefully by people who are electrically grounded and with well ion-blown equipment or

in such a condition, etc.

(2) When the module with protection film attached is stored for a long time, sometimes there remains a

very small amount of glue still on the bezel after the protection film is peeled off.

(3) You can remove the glue easily. When the glue remains on the bezel or its vestige is recognized,

please wipe them off with absorbent cotton waste or other soft material like chamois soaked with

normal-hexane.