ATMEL TS87C58X2 User Manual

BDTIC www.BDTIC.com/ATMEL

Features

• 80C52 Compatible

• 8051 pin and instruction compatible

• Four 8-bit I/O ports

• Thr ee 16 -bit ti m e r/coun ters

• 256 bytes scratchpad RAM

• High-Speed Architecture

• 40 MHz @ 5V, 30MHz @ 3V

• X2 Speed Improvement capability (6 clocks/ m achine cycle)

– 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to – 60 MHz @ 5V, 40 MHz @ 3V)

• Dual Data Pointer

• On-chip ROM/EPROM (16K-bytes, 32K-bytes)

• Programmable Clock Out and Up/Down Timer/Counter 2

• Hardware Watchdog Timer (One-time enabled with Reset-Out)

• Asynchronous port reset

• Interrupt Structure with

• 6 Interrupt sources

• 4 level priority interrupt system

• Full duplex Enhanced UART

• Framing error detection

• Automatic address recognition

• Low EMI (inhibit ALE)

• Power Control modes

• Idle mode

• Power-down mode

• Power-off Flag

• Once mode (On-chip Emulation)

• Power supply: 4.5-5.5V, 2.7-5.5V

• Temperature ranges: Commercial (0 to 70

• Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 F1, CQPJ4 4 (window), CDIL40

(window)

C) and Industrial (-40 to 85oC)

8-bit CMOS Microcontroller 16/32 Kbytes ROM/OTP

TS80C54/58X2 TS87C54/58X2 AT80C54/58X2 AT87C54/58X2

1. Description

TS80C54/58X2 is high perf ormance CMOS ROM , OTP an d EPROM ve rsions of the 80C51 CMOS single chip 8-bit microcontroller.

The TS80C54/58X2 retains all features of the Atmel 80C51 with extended ROM/EPROM capacity (16/32 Kbytes), 256 bytes of internal RAM, a 6-source , 4-level interrupt system, an on-chip oscilator and three timer/counters.

In addition , the TS 80C54 /58X2 a Ha rdware W atchd og Ti mer, a m ore ver satil e seria l channel that facilitates multiprocessor communication ( EUART) and a X2 speed improvement mechanism.

The fully static design of the TS80C54/58X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.

Rev. 4431E–8051–04/06

The TS80C54/58X2 has 2 software-selectable m odes of redu ce d act ivity for further reduc tion i n power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.

PDIL40

PLCC44

PQFP44 F1

VQFP44 1.4 ROM (bytes) EPROM (bytes)

2. Block Diagram

XTAL1 XTAL2

ALE/

PROG

PSEN

EA/VPP

(2) (2)

TS80C54X2 TS80C58X2

TS87C54X2 TS87C58X2

CPU

RxD

(2)(2)

EUART

Timer 0 Timer 1

TxD

C51

CORE

RAM

256x8

INT Ctrl

IB-bus

Parallel I/O Ports

Port 0

Port 1

Vss

Vcc

ROM /EPROM 16/32Kx8

Port 2

16k 32k

0 0

Port 3

T2EX

(1) (1)

Timer2

Watch

Dog

0 0

16k 32k

(2) (2) (2) (2)

RESET

AT/TS8xC54/8X2

INT1

INT0

(1): Alternate function of Port 1

(2): Alternate function of Port 3

4431E–8051–04/06

4. SFR Mapp in g

AT/TS8xC54/8X2

The Special Function Registers (SFRs) of the TS80C54/58X2 fall into the following categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

• I/O port regi s ters: P0, P1, P2, P3

• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON

• Power and clock control registers: PCON

• HDW Watchdog Timer Reset: WDTRST, WDTPRG

• Inter r u p t syste m regi s te r s: IE , IP, IPH

• Oth ers: AUXR, CKCON

4431E–8051–04/06

Table 4-1. All SFRs with their address and their reset value

Bit

Non Bit addressable

address-

able

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h FFh F0h

E8h EFh E0h

D8h DFh D0h PSW

C8h

C0h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

0000 0000

ACC

0000 0000

T2CON

0000 0000

XX00 0000

1111 1111

0X00 0000

1111 1111

SCON

0000 0000

1111 1111

TCON

0000 0000

1111 1111

T2MOD

XXXX XX00

SADEN

0000 0000

SADDR

0000 0000

SBUF

XXXX XXXX

TMOD

0000 0000

0000 0111

RCAP2L

0000 0000

AUXR1

XXXX 0XX0

TL0

0000 0000

DPL

0000 0000

RCAP2H

0000 0000

TL1

0000 0000

DPH

0000 0000

TL2

0000 0000

TH0

0000 0000

TH2

0000 0000

TH1

0000 0000

WDTRST

XXXX XXXX

AUXR

XXXX XXX0

IPH

XX00 0000

WDTPRG

XXXX X000

CKCON

XXXX XXX0

PCON

00X1 0000

F7h

E7h

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

reserved

AT/TS8xC54/8X2

4431E–8051–04/06

5. Pin Configurat ion

AT/TS8xC54/8X2

P1.0 / T2

P1.1 / T2EX

P1.2

P1.3 P1.4 P1.5 P1.6

P1.7

RST

P3.0/RxD

P3.1/TxD

P3.2/INT0 P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2 XTAL1

VSS

6 7

12 13

14 15 16 17

18 19 20

PDIL/

CDIL40

38 37

28 27

23 22 21

VCC P0.0 / A0 P0.1 / A1

P0.2 / A2 P0.3 / A3

P0.4 / A4 P0.5 / A5 P0.6 / A6 P0.7 / A7 EA/VPP ALE/PROG PSEN P2.7 / A15

P2.6 / A14 P2.5 / A13

P2.4 / A12 P2.3 / A11

P2.2 / A10 P2.1 / A9 P2.0 / A8

P1.4

P1.3

P1.2

P0.1/AD1

P0.2/AD2

P0.3/AD3

39 38

34 33

32 31 30 29

P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC* ALE/PRO PSEN P2.7/A15 P2.6/A14 P2.5/A13

P1.5 P1.6 P1.7 RST

P3.0/RxD

NIC*

P3.1/TxD P3.2/INT0 P3.3/INT1

P3.4/T0 P3.5/T1

7 8

9 10 11

12 13

14 15 16 17

P1.4

P1.3

5 4 3 2 1 6

P1.0/T2

P1.1/T2EX

P1.2

PLCC/CQPJ 44

VSS1/NIC*

VCC

P0.0/AD0

44 43 42 41 40

18 19 20 21 22 2 3 24 25 26 27 28

NIC*

VSS

XTAL2

XTAL1

P3.7/RD

P3.6/WR

P1.0/T2

P1.1/T2EX

VSS1/NIC*

VCC

P0.0/AD0

P0.2/AD2

P0.3/AD3

P0.1/AD1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

*NIC: No Internal Connection

P1.5 P1.6 P1.7 RST

NIC*

P3.4/T0

P3.5/T1

43 42 41 40 3944 38 37 36 35 34

3 4

6 7 8

9 10 11

PQFP44 F1 VQFP44 1.4

12 13 14 15 16 17 18 19 20 21 22

VSS

NIC*

XTAL1

P3.6/WR

P3.7/RD

XTAL2

P2.0/A8

P2.1/A9

P0.4/AD4

33 32

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

NIC*

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.3/A11

P2.2/A10

P2.4/A12

4431E–8051–04/06

Table 5-1. Pin Description for 40/44 pin packages

PIN NUMBER

MNEMONIC

Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection.

P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 i s an ope n-d r ain, bi di rec ti on al I/O p or t. P ort 0 p in s that ha ve 1s wr it ten to

P1.0-P1.7 1-8 2-9 40-44

P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 i s an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that

P3.0-P3.7 10-17 11,

Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscilla tor is running, resets

20 22 16 I Ground: 0V reference

40 44 38 I

1-3

12 40 I/OT2 (P1. 0): Timer/Counter 2 external count input/Clockout 23 41 IT2EX (P1.1): Timer/Counter 2 Reload/Captur e/Direct ion Control

13-19

10 11 5 I RXD (P3.0): Serial input port 11 13 7 O TXD (P3.1): Serial output port 12 14 8 I INT0 13 15 9 I INT1 14 16 10 I T0 (P3. 4): Timer 0 ext ernal inp ut 15 17 11 I T1 (P3. 5): Timer 1 external inp ut 16 18 12 O WR 17 19 13 O RD

7-13

TYPE

Power Supply: This is the power supply voltage for normal, idle and power-down

operation

them floa t and can be used as hig h i mpe da nc e in put s. Por t 0 p ins must be pol ari ze d t o Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multip le xe d low-ord er addres s an d data bus durin g ac c es s to ex ternal program and data memor y. In this ap plic at io n, i t uses st r ong i nt ern al pu ll -up wh en em it t in g 1s. Po rt 0 also i nput s t he co de by te s dur i ng E PRO M pr ogr a mmi ng. Ex ter na l pu ll -up s ar e r eq ui red during program verification during which P0 outputs the code bytes.

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that

have 1s written t o them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the int e rnal pu ll -up s. Por t 1 also r ec ei ve s the lo w -or der ad dres s byt e duri ng memo ry programming and verification.

Alter nate func tions for Port 1 include:

have 1s written t o them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external progr am memory and during accesses to external data memor y that use 16 bit addresses (MO VX @DPTR).In this applicat ion, it uses strong internal pull-ups emitti ng 1 s. Dur ing ac ces se s t o e xter na l data memory that u se 8- bi t ad dr es se s (MOV X @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification:

P2.0 to P2.5 for A8 to A13

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that

have 1s written t o them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Some Port 3 pin P3.4 receive the high order address bits during EPROM programming and verification for TS8xC58X2 devices.

Port 3 al so serves t he special features of the 80C51 family, as listed below.

(P3.2): External interrupt 0 (P3.3): External interrupt 1

(P3.6): External data memory write strobe

(P3.7): External data memory read strobe

P3.4 also receives A14 during TS87C58X2 EPROM Programming.

the device. An internal diffused resistor to V externa l capacit or to V

CC.

Name And FunctionDIL LCC VQFP 1.4

permits a power-on reset using only an

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

Table 5-1. Pin Description for 40/44 pin packages

PIN NUMBER

MNEMONIC MNEMONIC PIN NUMBER TYPE NAME AND FUNCTION

ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When

XTAL1 19 21 15 I

31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held

TYPE

Name And FunctionDIL LCC VQFP 1.4

address during an access to external memory. In normal operation, ALE is emitted at a const ant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pu lse is skipped during each access to external data memory. This pin is also the program pulse input (PROG programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches.

executing code from the external program memory, PSEN machine cycle, except that two PSEN external data memory. PSEN memory.

low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (54X2) or 7FFFH (5 8X2). If EA is held hi gh, the de vice executes from internal progr am memory unless the pr ogram cou nter contains an address greater than 3FFFH (54X2) or 7FFFH (58X2). This pin also receives the 12.75V programming supply voltage (V EA

will be internally latched on Reset.

Crystal 1: Input to the inverting oscillator amplifier and i nput to the internal clock generator circuits.

) during EPROM programming. If security level 1 is progra mmed,

is not activated duri ng fetc he s fro m inter n al prog ram

activations are skipped during each access to

is activated twice each

) during EPROM

XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier

4431E–8051–04/06

6. TS80C54/58X2 Enhanced Features

In comparison to t he origina l 80 C52, the T S 80C54/ 58X 2 imp lement s s om e new features, which

are

• The X2 option.

• The Dual Data Pointer.

• The Watchdog.

• The 4 level interrupt priority system.

• The power-off flag.

• The ONCE mod e.

• The AL E disabling.

• Som e enhanced features are also located in the UART and the timer 2.

6.1 X2 Feature

The TS80C54/58X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages:

• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

• Save power c onsum ption while keeping same CPU power (oscillator power saving).

• Save power c onsum ption by dividing dynam ically operating fre quency by 2 in operating and idle modes.

• Increas e CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software.

6.1.1 Description

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 6-2. sho ws the clock generat ion block diag ram. X 2 bit is v al idated on XTAL1÷2 rising edge to av oid gl itc hes when sw itch ing f rom X2 to STD mod e. Fig ure 6- 2. sho ws th e mo de switching waveforms.

Figure 6-1. Clock Generation Diagram

XTAL1:2

XTAL1

XTAL

CKCON reg

0 1

OSC

state machine: 6 clock cycles. CPU control

AT/TS8xC54/8X2

4431E–8051–04/06

Figure 6-2. Mode Switching Waveforms

XTAL1

XTAL1:2

X2 bit

CPU clock

The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode).

CAUTION

In order to prevent any incorrect operation while operating in X2 mode, user must be awa re that all peripherals using clock frequency as time reference (UART, timers ) will have their time reference divided by two. Fo r exampl e a free runnin g timer gen erating an i nterrup t every 20 m s will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.

AT/TS8xC54/8X2

X2 ModeSTD Mode STD Mo de

4431E–8051–04/06

Table 6-1. CKCON Register

CKCON - Clock Control Register (8Fh)

76543210

-------X2

Bit

Number

0X2

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

CPU and peripheral clock bit

Clear to select 12 clock periods per machine cycle (STD mode, F Set to sel ect 6 clock pe riods per machine cy cle (X2 mode, F

Reset Value = XXXX XXX0b Not bit addressable

OSC=FXTAL

/2).

For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel.com)

AT/TS8xC54/8X2

4431E–8051–04/06

7. Dual Data Pointer Register Ddptr

The additional data pointer c an be used to spee d up code execut ion and reduce code size in a number of ways.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DP TR registers that add ress the ext ernal mem ory, an d a single bit called DPS = AUXR1/bit0 (See Tab le 7-1.) that allows the program code to s witch between them (Refer to Figure 7-1).

Figure 7-1. Use of Dual Pointer

DPS

AUXR1(A2H)

DPH(83H) DPL(82H)

DPTR1

AT/TS8xC54/8X2

External Data Memory

DPTR0

4431E–8051–04/06

Table 7-1. AUXR1: Auxiliary R e gister 1

76543210

----GF30-DPS

Bit

Number

3 GF3 This bit is a general purpose user flag

0DPS

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

Always st uck at 0.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Clear to select DPTR0. Set to selec t DPTR1 .

Reset Value = XXXX 00X0 Not bit addressable

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

AT/TS8xC54/8X2

4431E–8051–04/06

7.1 Application

AT/TS8xC54/8X2

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for e xample , block o perations (copy, co mpare, se arch ...) are we ll served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer.

ASSEMBLY LANGUAG E

; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000 MO V DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DP TR,A ; write the byte to DEST 000F A 3 INC DPTR ; increment DEST address 0010 70F6 JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, no te that the I NC instruct ion d oes not di rectl y force th e DPS b it to a p articula r state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the pro per s equence mat ters, not i ts act ual val ue. In oth er words , the b lock mo ve routine works the same whether DPS is '0' or '1' on entry. Observ e that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

4431E–8051–04/06

8. Timer 2

The timer 2 in the TS80C54/58X2 is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascad e. It is cont rolled by T2CON reg ister (See Table 8-1) an d T2M OD regi ster (See Table 8-2). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 has 3 o pe rating mode s: cap ture , au tore load a nd Bau d R ate G ener ator . Thes e m odes are selected by the combination of RCLK, TCLK and CP/RL2 Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description.

Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes.

TS80C54/58X2 Timer 2 includes the following enhancements:

• Aut o-reload mode with up or down counter

• Program m able clock- output

8.1 Auto-Reload Mode

The auto-reload mode configures timer 2 as a 16-bit timer or ev ent counter with automatic reload. If DCEN bit in T 2M OD i s c leared, timer 2 behaves as in 80C5 2 (ref er to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 8-1. In this mode the T2EX pin controls the direction of count.

selects F

(T2CON), as described in the

/12 (timer

OSC

When T2EX is high , timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and genera tes an interrupt request . The overf low also cau ses the 16 -bit value in RCAP2H an d RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 an d TL2 eq uals th e value st ored in RCAP2 H and RCAP2L re gisters. The un derflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggl es when timer 2 overflows or unde rflows acco rding to the th e di rection of t he count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution

AT/TS8xC54/8X2

4431E–8051–04/06

Figure 8-1. Auto-Reload Mode Up/Down Counter (DCEN = 1)

(:6 in X2 mode )

XTAL1

XTAL

OSC

:12

C/T2

T2CONreg

AT/TS8xC54/8X2

TR2

T2CONreg

8.1.1 Programmable Clock-Output

In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 8-2) . The input clock increments TL2 at frequency F counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCA P 2L registers are load ed into TH 2 and TL2. In this mode , timer 2 overf lows do n ot gen erate int errupts. The formula gives the clock-out frequen cy as a function of the system osci llator frequ ency and the value in the RCAP2H and RCAP2L registers :

(DOWN COUNTING RELOAD VALUE)

FFh

(8-bit)

TL2

(8-bit)

RCAP2L

(8-bit)

(UP COUNTING RELOAD VALUE)

FFh

(8-bit)

TH2

(8-bit)

RCAP2H

(8-bit)

T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN

TOG-

TF2

T2CONreg

OSC

T2CONreg

EXF2

TIMER 2

INTERRUPT

/2. The timer repeatedly

4431E–8051–04/06

Cloc k OutF re quen cy

–

---------------------------------------------------------------------------------------- -=

4 65536

osc

RCAP2H–RCA P2L

⁄()×

For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (F

OSC

to 4 MHz (F

/4). The generated clock signal is brought out to T2 pin (P1.0).

OSC

16)

Timer 2 is programmed for the clock-out mode as follows:

• Set T2OE bit in T2MOD register.

• Clear C/T2

bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application.

• To start the timer, set TR2 run control bit in T2CON register.

It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.

Figure 8-2. Clock-Out Mode C/T2

XTAL1

T2EX

= 0

(:1 in X2 mode)

TR2

T2CON reg

Toggle

EXEN2

T2CON reg

TL2

(8-bit)

RCAP2L

(8-bit)

T2OE

T2MOD reg

EXF2

T2CON reg

TH2

(8-bit)

RCAP2H

(8-bit)

OVERFLOW

TIMER 2

INTERRUPT

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

Table 8-1. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7 6 5 4 3 2 1 0

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

Bit

Number

7TF2

6 EXF2

5 RCLK

4TCLK

3 EXEN2

2TR2

1C/T2#

0CP/RL2#

Bit

Mnemonic Description

Timer 2 overflow Flag

Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and T CLK = 0.

Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software . EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)

Receive Clock bit Clear to use timer 1 overflow as receive cl ock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial por t in mode 1 or 3. Set to use timer 2 overflow as transm it clock fo r serial port in mode 1 or 3.

Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or rel oad when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port.

Timer 2 Run control bit Clear to tu rn off timer 2. Set to turn on timer 2.

Timer/Counter 2 select bit

Clear for timer operation (input from internal clock system: F Set for counter oper ation (input from T2 in put pin, falling edge trigger). Must be 0 for clock out mode.

Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, C P/RL2# is ignored and timer is forced to auto -reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.

OSC

4431E–8051–04/06

Reset Value = 0000 0000b Bit addressable

Table 8-2. T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7 6 5 4 3 2 1 0

- - - - - - T2OE DCEN

Bit

Number

1T2OE

0 DCEN

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

Clear to program P1.0/T2 as clock in put or I/O port. Set to program P1.0/T2 as clock output.

Down Counter Enable bit

Clear to disabl e timer 2 as up/down counter . Set to enable timer 2 as up/down count er.

Reset Value = XXXX XX00b Not bit addressable

AT/TS8xC54/8X2

4431E–8051–04/06

9. TS80C54/58X 2 Serial I/O P ort

The serial I/O port in the TS80C54/58X2 is compatible with the serial I/O port in the 80C52. It provides b oth synch rono us and asy nchrono us com mun ication m odes. It operate s as an Un iversal Asynchron ous Receiver an d Trans mitter (UART) i n three full-dup lex mode s (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates

Serial I/O port includes the following enhancements:

• Frami ng error detection

• Aut om atic address recognition

9.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1).

Figure 9-1. Framing Error Block Diagram

RITIRB8TB8RENSM2SM1SM0/FE

AT/TS8xC54/8X2

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD = 0)

PCON (87h)

IDLPDGF0GF1POF-SMOD0SMOD1

To UART framing error control

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 9-3.) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset c an cle ar FE bit. Subsequently received frames with valid stop bits cann ot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 9-

2. and Figure 9-3.).

Figure 9-2. UART Timings in Mode 1

RXD

SMOD0=X

Start

bit

Data byte

D7D6D5D4D3D2D1D0

Stop

bit

4431E–8051–04/06

SMOD0=1

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