TS80C51U2 is high performance CMOS ROM, OTP
and EPROM versions of the 80C51 CMOS single chip
8-bit microcontroller.
The TS80C51U2 retains all features of the 80C51 with
extended ROM/EPROM capacity (16 Kbytes), 256 bytes
of internal RAM, a 7-source , 4-level interrupt system,
an on-chip oscilator and three timer/counters.
In addition, the TS80C51U2 has a second UART,
enhanced functions on both UART, enhanced timer 2,
a hardware watchdog timer, a dual data pointer, a baud
rate generator and a X2 speed improvement mechanism.
The fully static design of the TS80C51U2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C51U2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
● Asynchronous port reset
● Interrupt Structure with
• 7 Interrupt sources
• 4 level priority interrupt system
● Full duplex Enhanced UARTs
• Framing error detection
• Automatic address recognition
● Low EMI (inhibit ALE)
● Power Control modes
• Idle mode
• Power-down mode
• Power-off Flag
● Once mode (On-chip Emulation)
● Power supply: 4.5-5.5V, 2.7-5.5V
● Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85oC)
● Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44
(window), CDIL40 (window)
3. The second UART
In this document, UART_0 will make reference to the
first UART (present in all Atmel Wireless &
Microcontrollers C51 derivatives) and UART_1 will
make reference to the second UART, only present in
the TS80C51U2 part.
Rev. D - 15 January, 20011
The second UART (UART_1) can be seen as an alternate
function of Port 1 (P1.2 or P1.6 for RXD1 and P1.3 or
P1.7 for TXD1) or can be connected to (pin6 or pin12)
and (pin28 or pin34) of 44-pin package (see Pin
TS80C51U2
TS83C51U2
TS87C51U2
configuration). UART_1 is fully compliant with the first one allowing an internal baud rate generator to be the
clock source. This common internal baud rate generator can be used independently by each UART or both as clock
source allowing to program various speeds.
The TS80C51U2 provides 7 sources of interrupt with four priority levels. UART_1 has a lower priority than Timer
2. The Serial Ports are full duplex meaning they can transmit and receive simultaneously. They are also receive
buffered, meaning they can start reception of a second byte before a previously received byte has been read from
the receive register. The Serial Port receive and transmit registers of UART_1 are both accessed at Special Function
Register SBUF_1. Writing to SBUF_1 loads the transmit register and reading SBUF_1 accesses a physical separate
receive register.
The UART_1 port control and status is the Special Function Register SCON_1. This register contains not only the
mode selection bit but also the 9th bit for transmit and receive (TB8_1 and RB8_1) and the serial port interrupt
bits (TI_1 and RI_1). The automatic address recognition feature is enabled when multiprocessor communication
is enabled. Implemented in hardware, automatic address recognition enhances the multiprocessor communication
feature by allowing the Serial Port to examine address of each incoming frame and provides filtering capability.
The UART_1 also comes with Frame error detection, similar to the UART_0.
2Rev. D - 15 January, 2001
PDIL40
PLCC44
VQFP44 1.4
TS80C51U200
TS83C51U216k0
TS87C51U2016k
4. Block Diagram
RxD
Table 1. Memory size
ROM (bytes)EPROM (bytes)
TxD
Vcc
Vss
T2EX
T2
RxD1
TS80C51U2
TS83C51U2
TS87C51U2
TxD1
ALE/
XTAL1
XTAL2
PROG
PSEN
EA/V
RD
WR
(2)(2)
UART_0
CPU
PP
(2)
(2)
Timer 0
Timer 1
(2) (2)(2) (2)
RESET
T0
RAM
256x8
C51
CORE
T1
IB-bus
INT
Ctrl
INT1
INT0
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(3): See pin description
ROM
/EPROM
16Kx8
Parallel I/O Ports
Port 1
Port 0
P0
P1
Port 2
(1) (1)
Timer2
Port 3
P2
(3) (3)
UART_1
WatchDog
P3
Rev. D - 15 January, 20013
TS80C51U2
TS83C51U2
TS87C51U2
5. SFR Mapping
The Special Function Registers (SFRs) of the TS80C51U2 fall into the following categories:
10115IRxD_0 (P3.0): Serial input port for UART_0
11137OTxD_0 (P3.1): Serial output port for UART_0
12148IINT0 (P3.2): External interrupt 0
13159IINT1 (P3.3): External interrupt 1
141610IT0 (P3.4): Timer 0 external input
151711IT1 (P3.5): Timer 1 external input
161812OWR (P3.6): External data memory write strobe
171913ORD (P3.7): External data memory read strobe
42
43
2
3
5,
7-13
TYPE
Power Supply: This is the power supply voltage for normal, idle and power-
down operation
written to them float and can be used as high impedance inputs. Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verification during
which P0 outputs the code bytes.
I/OPort 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups. Port 1 also receives the low-order
address byte during memory programming and verification.
Alternate functions for TSC8x54/58 Port 1 include:
Depending on values of (M1UA_1, M0UA_1) bits located into AUXR register,
the UART_1 pins are alternate functins of P1 with two possible locations.
First location:
P1.2: RxD_1, serial input port for UART_1
I
P1.3: TxD_1, serial output port for UART_1
O
Second location:
P1.6: RxD_1, serial input port for UART_1
I
P1.7: TxD_1, serial output port for UART_1
O
See “Alternate function on Port 1” on page 32
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because oftheinternal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming
and verification: P2.0 to P2.5
I/OPort 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.
NAME AND FUNCTION
6Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 3. Pin Description for 40/44 pin packages
MNEMONIC
Reset9104IReset: A high on this pin for two machine cycles while the oscillator is running,
ALE/PROG303327O (I)Address Latch Enable/Program Pulse: Output pulse for latching the low byte
PSEN293226OProgram Store ENable: The read strobe to external program memory. When
EA/V
PP
XTAL1192115I
XTAL2182014OCrystal 2: Output from the inverting oscillator amplifier
RxD_1-126ISerial Input for UART_1. For 44-pin package only.
TxD_1-3428O
PIN NUMBER
DILLCC VQFP 1.4
313529IExternal Access Enable/Programming Supply Voltage: EA must be externally
TYPE
resets the device. An internal diffused resistor to VSSpermits a power-on reset
using only an external capacitor to V
time-out, the reset pin becomes an output during the time the internal reset is
activated.
of the address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program
pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal
fetches.
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
held low to enable the device to fetch code from external program memory
locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is
held high, the device executes from internal program memory unless the program
counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must
be held low for ROMless devices. This pin also receives the 12.75V programming
supply voltage (VPP) during EPROM programming. If security level 1 is
programmed, EA will be internally latched on Reset.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
Serial Ouput for UART_1. This pin is pulled up by a 100K resistor when not
selected. For 44-pin package only.
NAME AND FUNCTION
If the hardware watchdog reaches its
CC.
Rev. D - 15 January, 20017
TS87C51U2
7. TS80C51U2 Enhanced Features
In comparison to the original 80C52, the TS80C51U2 implements some new features, which are:
• The X2 option.
• The second full duplex enhanced UART.
• The Baud Rate generator.
• The Dual Data Pointer.
• The Watchdog.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• The ALE disabling.
• Some enhanced features are also located in the UARTs and the timer 2.
7.1 X2 Feature
The TS80C51U2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following
advantages:
● Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
● Save power consumption while keeping same CPU power (oscillator power saving).
● Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
● Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.
7.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.
XTAL1:2
XTAL1
F
XTAL
2
X2
0
1
F
OSC
CKCON reg
Figure 1. Clock Generation Diagram
state machine: 6 clock cycles.
CPU control
8Rev. D - 06 december, 2000
TS87C51U2
XTAL1
XTAL1:2
X2 bit
CPU clock
X2 ModeSTD ModeSTD Mode
Figure 2. Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock
cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature
(X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals
using clock frequency as time reference (UARTs, timers) will have their time reference divided by two. For example
a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with
4800 baud rate will have 9600 baud rate.
Rev. D - 06 december, 20009
TS87C51U2
Table 4. CKCON Register
CKCON - Clock Control Register (8Fh)
76543210
-------X2
Bit
Number
7-
6-
5-
4-
3-
2-
1-
0X2
Bit
Mnemonic
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CPU and peripheral clock bit
Reset Value = XXXX XXX0b
Not bit addressable
Description
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F
OSC=FXTAL
OSC=FXTAL
).
/2).
For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com)
10Rev. D - 06 december, 2000
TS80C51U2
TS83C51U2
TS87C51U2
7.2 Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a number of
ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3).
External Data Memory
07
DPS
AUXR1(A2H)
DPH(83H) DPL(82H)
DPTR1
DPTR0
Figure 3. Use of Dual Pointer
Rev. D - 15 January, 200111
TS80C51U2
TS83C51U2
TS87C51U2
Table 5. AUXR1: Auxiliary Register 1
76543210
-------DPS
Bit
Number
7-
6-
5-
4-
3-
2-
1-
0DPS
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XXX0
Not bit addressable
User software should not write 1s to reserved bits. These bits may be used in future 8051 family productsto invoke new feature. In that case, the reset
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.
12Rev. D - 15 January, 2001
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE; address of SOURCE
0003 05A2 INCAUXR1; switch data pointers
0005 90A000 MOV DPTR,#DEST; address of DEST
0008LOOP:
0008 05A2 INCAUXR1; switch data pointers
000A E0MOVX A,@DPTR; get a byte from SOURCE
000B A3INC DPTR; increment SOURCE address
000C 05A2 INCAUXR1; switch data pointers
000E F0MOVX @DPTR,A; write the byte to DEST
000F A3INC DPTR; increment DEST address
0010 70F6 JNZLOOP; check for 0 terminator
0012 05A2 INCAUXR1; (optional) restore DPS
TS80C51U2
TS83C51U2
TS87C51U2
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.
In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence
matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the
opposite state.
Rev. D - 15 January, 200113
TS80C51U2
TS83C51U2
TS87C51U2
7.3 Timer 2
The timer 2 in the TS80C51U2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in
cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation
is similar to Timer 0 and Timer 1. C/T2 selects F
as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the
combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel Wireless & Microcontrollers 8bit Microcontroller Hardware description.
Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of
Capture and Baud Rate Generator Modes.
In TS80C51U2 Timer 2 includes the following enhancements:
● Auto-reload mode with up or down counter
● Programmable clock-output
7.3.1 Auto-Reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit
in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wireless & Microcontrollers 8-bit
Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in
Figure 4. In this mode the T2EX pin controls the direction of count.
/12 (timer operation) or external pin T2 (counter operation)
OSC
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates
an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded
into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and
TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh
into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2
does not generate any interrupt. This bit can be used to provide 17-bit resolution.
14Rev. D - 15 January, 2001
XTAL1
F
XTAL
F
OSC
(:6 in X2 mode)
:12
T2
0
1
C/T2
T2CONreg
TS80C51U2
TS83C51U2
TS87C51U2
TR2
T2CONreg
(DOWN COUNTING RELOAD VALUE)
FFh
(8-bit)
TL2
(8-bit)
RCAP2L
(8-bit)
(UP COUNTING RELOAD VALUE)
FFh
(8-bit)
TH2
(8-bit)
RCAP2H
(8-bit)
T2EX:
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up counting
In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5) . The
input clock increments TL2 at frequency F
At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer
2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system
oscillator frequency and the value in the RCAP2H and RCAP2L registers:
/2. The timer repeatedly counts to overflow from a loaded value.
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz
OSC
16)
/2
to 4 MHz (F
/4). The generated clock signal is brought out to T2 pin (P1.0).
OSC
(F
Timer 2 is programmed for the clock-out mode as follows:
● Set T2OE bit in T2MOD register.
● Clear C/T2 bit in T2CON register.
● Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
● Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different
one depending on the application.
Rev. D - 15 January, 200115
TS80C51U2
TS83C51U2
TS87C51U2
● To start the timer, set TR2 run control bit in T2CON register.
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration,
the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and
RCAP2L registers.
T2EX
T2
XTAL1
:2
(:1 in X2 mode)
TR2
T2CON reg
Toggle
QD
EXEN2
T2CON reg
TL2
(8-bit)
RCAP2L
(8-bit)
T2OE
T2MOD reg
EXF2
T2CON reg
TH2
(8-bit)
RCAP2H
(8-bit)
OVERFLOW
TIMER 2
INTERRUPT
Figure 5. Clock-Out Mode C/T2=0
16Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 6. T2CON Register
T2CON - Timer 2 Control Register (C8h)
76543210
TF2EXF2RCLKTCLKEXEN2TR2C/T2#CP/RL2#
Bit
Number
7TF2
6EXF2
5RCLK_0
4TCLK_0
3EXEN2
2TR2
1C/T2#
Mnemonic
Bit
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
Receive Clock bit for UART_0
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit for UART_0
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
clock the serial port.
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
OSC
).
0CP/RL2#
Reset Value = 0000 0000b
Bit addressable
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Rev. D - 15 January, 200117
TS80C51U2
TS83C51U2
TS87C51U2
Table 7. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
76543210
------T2OEDCEN
Bit
Number
7-
6-
5-
4-
3-
2-
1T2OE
0DCEN
Bit
Mnemonic
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timer 2 Output Enable bit
Down Counter Enable bit
Reset Value = XXXX XX00b
Not bit addressable
Description
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.
18Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
7.4 TS80C51U2 Serial I/O Ports enhancements
The serial I/O ports in the TS80C51U2 are compatible with the serial I/O port in the 80C52.
They provide both synchronous and asynchronous communication modes. They operate as Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates
Serial I/O ports include the following enhancements:
● Framing error detection
● Automatic address recognition
As these improvements apply to both UART, most of the time in the following lines, there won’t be any reference
to UART_0 or UART_1, but only to UART, generally speaking. Idem for the bits in registers.
7.4.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 6).
RITIRB8TB8RENSM2SM1SM0/FE
SCON_0 for UART_0 (98h)
(SCON_1 for UART_1 (C0h))
Set FE bit if stop bit is 0 (framing error) (SMOD0_0 = 1 for UART_0)
SM0 to UART mode control (SMOD0_0 = 0 for UART_0)
SMOD0_0SMOD1_0
To UART framing error control
PCON for UART_0 (87h)
IDLPDGF0GF1POF-
(SMOD bits for UART_1 are
located in BDRCON_1)
Figure 6. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set.
Rev. D - 15 January, 200119
TS80C51U2
TS83C51U2
TS87C51U2
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 7. and Figure 8.).
RXD
SMOD0=X
FE
SMOD0=1
SMOD0=0
SMOD0=1
SMOD0=1
RI
RXD
RI
RI
FE
Start
bit
Data byte
Figure 7. UART Timings in Mode 1
Start
bit
Data byteNinth
D7D6D5D4D3D2D1D0
Stop
bit
D8D7D6D5D4D3D2D1D0
Stop
bit
bit
Figure 8. UART Timings in Modes 2 and 3
7.4.2 Automatic Address Recognition
The automatic address recognition feature is enabled for each UART when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).
7.4.3 Given Address
Each UART has an individual address that is specified in SADDR_0 or SADDR_1 register; the SADEN_0 or
SADEN_1 register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example
20Rev. D - 15 January, 2001
illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
TS80C51U2
TS83C51U2
TS87C51U2
Slave B:SADDR1111 0011b
Slave C:SADDR1111 0010b
SADEN1111 1001b
Given1111 0XX1b
SADEN1111 1101b
Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A
only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but
not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2
clear (e.g. 1111 0001b).
7.4.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as
don’t-care bits, e.g.:
SADDR0101 0110b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a
broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1100b
SADEN1111 1010b
Broadcast 1111 1X11b,
Slave B:SADDR1111 0011b
Slave C:SADDR=1111 0010b
SADEN1111 1001b
Broadcast 1111 1X11B,
SADEN1111 1101b
Broadcast 1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the
master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send
and address FBh.
7.4.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX
XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
Rev. D - 15 January, 200121
TS80C51U2
TS83C51U2
TS87C51U2
7.4.6 Baud Rate Selection for UART0_0 for mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON
registers.
TIMER1_BRG
TIMER2_BRG
RCLK_0
INT_BRG_0
RBCK_0
TIMER1_BRG
TIMER2_BRG
TCLK_0
INT_BRG_0
TBCK_0
0
1
0
1
TIMER_BRG
TIMER_BRG
0
1
0
1
/ 16
/ 16
Rx_0 Clock
Tx_0 Clock
Figure 9. Baud Rate selection
7.4.7 Baud Rate Selection for UART1_1 for mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the BDRCON_1 register.
When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the
BRL reload value, the X2 bit in CKON register, the value of SPD bit (Speed Mode) in BDRCON register and the value
of theSMOD1_0 bit in PCON register (for UART_0) orSMOD1_1 in BDRCON_1 register (for UART_1). The Internal
Baud Rate Generator is common to both UARTs:
SMOD1_0
/2
0
XTAL1
F
XTAL
X2
SPD
BRR
SMOD1_1
/2
0
1
/6
auto reload counter
0
1
BRG
BRL
overflow
/2
Figure 11. Internal Baud Rate
Rev. D - 15 January, 200123
1
0
1
INT_BRG_0
INT_BRG_1
TS80C51U2
TS83C51U2
TS87C51U2
● for UART_1
Baud_Rate =
SMOD1_1
2
2 x 2 x 6
x 2X2 x FXTAL
(1-SPD)
x 16 x [256 - (BRL)]
(BRL) = 256 -
2 x 2 x 6
● for UART_0
Baud_Rate =
2 x 2 x 6
(BRL) = 256 -
2 x 2 x 6
Example of computed value when X2=1, SMOD1=1, SPD=1
Example of computed value when X2=0, SMOD1=0, SPD=0
F
Baud Rates
BRLError (%)BRLError (%)
48002471.232430.16
24002381.232300.16
12002201.232023.55
6001850.161520.16
The baud rate generator can be used for mode 1 or 3 (refer to figures 9 and 10), but also for mode 0 for both
UARTs, thanks to the bit SRC located in BDRCON register (Table 12)
24Rev. D - 15 January, 2001
= 16.384 MHzF
OSC
= 24MHz
OSC
7.5 UARTs registers
SADEN_0 - Slave Address Mask Register for UART_0 (B9h)
76543210
Reset Value = 0000 0000b
SADEN_1 - Slave Address Mask Register for UART_1 (BAh)
76543210
Reset Value = 0000 0000b
SADDR_0 - Slave Address Register for UART_0 (A9h)
76543210
Reset Value = 0000 0000b
TS80C51U2
TS83C51U2
TS87C51U2
SADDR_1 - Slave Address Register for UART_1 (AAh)
76543210
Reset Value = 0000 0000b
SBUF_0 - Serial Buffer Register for UART_0 (99h)
76543210
Reset Value = XXXX XXXXb
SBUF_1 - Serial Buffer Register for UART_1 (C1h)
76543210
Reset Value = XXXX XXXXb
BRL - Baud Rate Reload Register for the internal baud rate generator, UART_0 and UART_1 (9Ah)
76543210
Reset Value = 0000 0000b
Rev. D - 15 January, 200125
TS80C51U2
TS83C51U2
TS87C51U2
Table 8. SCON Register
SCON_0 - Serial Control Register for UART_0 (98h)
76543210
FE_0/
SM0_0
SM1_0SM2_0REN_0TB8_0RB8_0TI_0RI_0
Bit
Number
7FE_0
6SM1_0
5SM2_0
4REN_0
3TB8_0
Bit
Mnemonic
SM0_0
Description
Framing Error bit (SMOD0_0=1) for UART_0
Serial port Mode bit 0 (SMOD0_0=0) for UART_0
Serial port Mode bit 1 for UART_0
Reception Enable bit for UART_0
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_0.
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0_0 must be set to enable access to the FE bit
Refer to SM1 for serial port mode selection.
SMOD0_0 must be cleared to enable access to the SM0_0 bit
SM0_0SM1_0 ModeDescriptionBaud Rate
000Shift RegisterF
0118-bit UARTVariable
1029-bit UARTF
1139-bit UARTVariable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART_0
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
Clear to disable serial reception.
Set to enable serial reception.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
XTAL
XTAL
/12 (F
/64 or F
XTAL
XTAL
/6 X2 mode)
/32 (F
XTAL
/32 or F
/16 X2 mode)
XTAL
Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART_0
Cleared by hardware if 9th bit received is a logic 0.
2RB8_0
1TI_0
0RI_0
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag for UART_0
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
Receive Interrupt flag for UART_0
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.
Reset Value = 0000 0000b
Bit addressable
26Rev. D - 15 January, 2001
Table 9. SCON Register
SCON_1 - Serial Control Register for UART_1 (C0h)
76543210
FE_1/
SM0_1
SM1_1SM2_1REN_1TB8_1RB8_1TI_1RI_1
TS80C51U2
TS83C51U2
TS87C51U2
Bit
Number
7FE_1
6SM1_1
5SM2_1
4REN_1
3TB8_1
Bit
Mnemonic
SM0_1
Description
Framing Error bit (SMOD0_1=1) for UART_1
Serial port Mode bit 0 (SMOD0_1=0) for UART_1
Serial port Mode bit 1 for UART_1
Reception Enable bit for UART_1
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_1.
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0_1 must be set to enable access to the FE bit
Refer to SM1 for serial port mode selection.
SMOD0_1 must be cleared to enable access to the SM0_1 bit
SM0_1SM1_1 ModeDescriptionBaud Rate
000Shift RegisterF
0118-bit UARTVariable
1029-bit UARTF
1139-bit UARTVariable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART_1
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
Clear to disable serial reception.
Set to enable serial reception.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
XTAL
XTAL
/12 (F
/64 or F
XTAL
XTAL
/6 X2 mode)
/32 (F
XTAL
/32 or F
/16 X2 mode)
XTAL
Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART_1
Cleared by hardware if 9th bit received is a logic 0.
2RB8_1
1TI_1
0RI_1
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag for UART_1
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
Receive Interrupt flag for UART_1
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.
Reset Value = 0000 0000b
Bit addressable
Rev. D - 15 January, 200127
TS80C51U2
TS83C51U2
TS87C51U2
Table 10. T2CON Register
T2CON - Timer 2 Control Register (C8h)
76543210
TF2EXF2RCLKTCLKEXEN2TR2C/T2#CP/RL2#
Bit
Number
7TF2
6EXF2
5RCLK_0
4TCLK_0
3EXEN2
2TR2
1C/T2#
Bit
Mnemonic
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
Receive Clock bit for UART_0
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit for UART_0
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
clock the serial port.
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
OSC
).
0CP/RL2#
Reset Value = 0000 0000b
Bit addressable
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
28Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 11. PCON Register
PCON - Power Control Register (87h)
76543210
SMOD1_0SMOD0_0-POFGF1GF0PDIDL
Bit
Number
7SMOD1_0
6SMOD0_0
5-
4POF
3GF1
2GF0
1PD
0IDL
Mnemonic
Bit
Description
Serial port Mode bit 1 for UART_0
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0 for UART_0
Clear to select SM0_0 bit in SCON_0 register.
Set to to select FE_0 bit in SCON_0 register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.
Rev. D - 15 January, 200129
TS80C51U2
TS83C51U2
TS87C51U2
Table 12. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
76543210
---BRRTBCK_0RBCK_0SPDSRC
Bit
BitMne-
Number
7-
6-
5-
4BRR
3TBCK_0
2RBCK_0
1SPD
0SRC
monic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Run Control bit
Clear to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator, for Tx.
Set to select internal Baud Rate Generator for Tx.
Reception Baud Rate Generator Selection bit for UART_1
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator for Rx.
Set to select internal Baud Rate Generator for Rx.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 0000 00XXb
Rev. D - 15 January, 200131
TS80C51U2
TS83C51U2
TS87C51U2
7.6 Alternate function on Port 1
The M1UA_1and M0UA_1 bits located into AUXRregister at bit location 7 and 6 permit to validatealternate functions
located on Port 1. Following the combination of these two bits, the TxD_1 output and RxD_1 input of UART_1 take
place on Port 1 pins (two different locations are possible) and the other locations of TxD_1 and RxD_1 available only
for 44-pin package are no more valid.
Table 14. AUXR Register
AUXR - Auxiliary Register (8Eh)
76543210
M1UA_1M0UA_1-----AO
Bit
Number
7M1UA_1
6M0UA_1
5-
4-
3-
2-
1-
0AO
BitMne-
monic
Description
Multiplex I/Os of UART_1 bit 1
This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins.
Multiplex I/Os of UART_1 bit 0
This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins.
M1UA_1M0UA_1Result
0 0UART_1 pins are disabled.
0 1UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only.
1 0UART_1 pins are alternate functions of P1 located at P1.2 and P1.3.
1 1UART_1 pins are alternate functions of P1 located at P1.6 and P1.7.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
Reset Value = 00XX XXX0b
Not bit addressable
32Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
7.7 Interrupt System
The TS80C51U2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts
(timers 0, 1 and 2) and the two serial port interrupts. These interrupts are shown in Figure 12.
INT0
TF0
INT1
TF1
RI_0
TI_0
TF2
EXF2
RI_1
TI_1
IE0
IE1
IPH, IP
High priority
interrupt
3
0
3
0
3
0
3
0
3
0
3
0
Interrupt
polling
sequence, decreasing
from high to low priority
Individual Enable
Global Disable
Low priority
interrupt
Figure 12. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 16.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing
a bit in the Interrupt Priority register (See Table 17.) and in the Interrupt Priority High register (See Table 18.).
shows the bit values and priority levels associated with each combination.
The second UART interrupt vector is located at address 0033H. All other vector addresses are the same as standard
C52 devices.
Rev. D - 15 January, 200133
TS80C51U2
TS83C51U2
TS87C51U2
Table 15. Priority Level Bit Values
IPH.xIP.xInterrupt Level Priority
000 (Lowest)
011
102
113 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 16. IE Register
IE - Interrupt Enable Register (A8h)
76543210
EAES_1ET2ES_0ET1EX1ET0EX0
Bit
Number
7EA
6ES_1
5ET2
4ES_0
3ET1
2EX1
1ET0
Bit
Mnemonic
Description
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.
Serial port Enable bit for UART_1
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 2 overflow interrupt Enable bit
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
Serial port Enable bit for UART_0
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
34Rev. D - 15 January, 2001
Table 17. IP Register
IP - Interrupt Priority Register (B8h)
76543210
-PS_1PT2PS_0PT1PX1PT0PX0
TS80C51U2
TS83C51U2
TS87C51U2
Bit
Number
7-
6PS_1
5PT2
4PS_0
3PT1
2PX1
1PT0
0PX0
Bit
Mnemonic
Reset Value = X000 0000b
Bit addressable
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Serial port Priority bit for UART_1
Refer to PSH for priority level.
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
Serial port Priority bit for UART_0
Refer to PSH for priority level.
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
External interrupt 1 Priority bit
Refer to PX1H for priority level.
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Rev. D - 15 January, 200135
TS80C51U2
TS83C51U2
TS87C51U2
Table 18. IPH Register
IPH - Interrupt Priority High Register (B7h)
76543210
-PSH_1PT2HPSH_0PT1HPX1HPT0HPX0H
Bit
Number
7-
6PSH_1
5PT2H
4PSH_0
3PT1H
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Serial port Priority High bit for UART_1
PSH_1PS_1Priority Level
00Lowest
01
10
11Highest
Timer 2 overflow interrupt Priority High bit
PT2HPT2Priority Level
00Lowest
01
10
11Highest
Serial port Priority High bit for UART_0
PSH_0PS_0Priority Level
00Lowest
01
10
11Highest
Timer 1 overflow interrupt Priority High bit
PT1HPT1Priority Level
00Lowest
01
10
11Highest
External interrupt 1 Priority High bit
PX1HPX1Priority Level
2PX1H
1PT0H
0PX0H
00Lowest
01
10
11Highest
Timer 0 overflow interrupt Priority High bit
PT0HPT0Priority Level
00Lowest
01
10
11Highest
External interrupt 0 Priority High bit
PX0HPX0Priority Level
00Lowest
01
10
11Highest
Reset Value = X000 0000b
Not bit addressable
36Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
7.8 Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.
In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to
be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or
during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running,
the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
7.9 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to 7.4.6, PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last
instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.
VCCcan be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from
power-down. To properly terminate power-down, the reset or external interrupt should not be executed before V
is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled
and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 13.
When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power
down exit will be completed when the first input will be released. In this case the higher priority interrupt service
routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction
that put TS80C51U2 into power-down mode.
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect
the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
NOTE:Ifidle mode is activated with power-down mode(IDL and PD bits set), the exitsequence is unchanged, whenexecutionis vectored to interrupt,
PD and IDL bits are cleared and idle mode is not entered.
Rev. D - 15 January, 200137
TS80C51U2
TS83C51U2
TS87C51U2
Table 19. The state of ports during idle and power-down modes
Mode
IdleInternal11Port Data*Port DataPort DataPort Data
IdleExternal11FloatingPort DataAddressPort Data
Power DownInternal00Port Data*Port DataPort DataPort Data
Power DownExternal00FloatingPort DataPort DataPort Data
* Port 0 can force a "zero" level. A "one" Level will leave port floating.
Program
Memory
ALEPSENPORT0PORT1PORT2PORT3
38Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
7.10 Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The
WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default
disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,
SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
7.10.1 Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.
The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled,
it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at
least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST
is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T
the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within
the time required to prevent a WDT reset.
To have a more powerful WDT, a 27counter has been added to extend the Time-out capability, ranking from
16ms to 2s @ F
= 12MHz. To manage this feature, refer to WDTPRG register description, Table 21. (SFR0A7h).
OSC
OSC
, where T
OSC
= 1/F
OSC
. To make
Table 20. WDTRST Register
WDTRST Address (0A6h)
7654321
Reset valueXXXXXXX
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the
user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset
or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power
Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51U2
is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51U2 while in
Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter
Idle mode.
40Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
7.11 ONCETM Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using TS80C51U2 without removing the circuit from
the board. The ONCE mode is invoked by driving certain pins of the TS80C51U2; the following sequence must
be exercised:
● Pull ALE low while the device is in reset (RST high) and PSEN is high.
● Hold ALE low as RST is deactivated.
While the TS80C51U2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26.
shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset.
A cold start reset is the one induced by VCCswitch-on. A warm start reset occurs while VCCis still applied to
the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 23.). POF is set by hardware when VCCrises
from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type
of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will
return indeterminate value.
Table 23. PCON Register
PCON - Power Control Register (87h)
76543210
SMOD1_0SMOD0_0-POFGF1GF0PDIDL
Bit
Number
7SMOD1_0
6SMOD0_0
5-
4POF
3GF1
2GF0
1PD
0IDL
Mnemonic
Bit
Description
Serial port Mode bit 1 for UART_0
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0 for UART_0
Clear to select SM0_0 bit in SCON_0 register.
Set to to select FE_0 bit in SCON_0 register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
42Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
7.13 Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data
memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE
signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but
remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is
weakly pulled high.
Table 24. AUXR Register
AUXR - Auxiliary Register (8Eh)
76543210
M1UA_1M0UA_1-----AO
Bit
Number
7M1UA_1
6M0UA_1
5-
4-
3-
2-
1-
0AO
BitMne-
monic
Description
Multiplex I/Os of UART_1 bit 1
This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins.
Multiplex I/Os of UART_1 bit 0
This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins.
M1UA_1M0UA_1Result
0 0UART_1 pins are disabled.
0 1UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only.
1 0UART_1 pins are alternate functions of P1 located at P1.2 and P1.3.
1 1UART_1 pins are alternate functions of P1 located at P1.6 and P1.7.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
Reset Value = 00XX XXX0b
Not bit addressable
Rev. D - 15 January, 200143
TS80C51U2
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TS87C51U2
8. TS80C51U2 ROM
8.1 ROM Structure
The TS83C51U2 ROM memory is divided in three different arrays:
The program Lock system, when programmed, protects the on-chip program against software piracy.
8.2.1 Encryption Array
Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a
byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.
8.2.2 Program Lock Bits
The lock bits when programmed according to Table 25. will provide different level of protection for the on-chip
code and data.
Table 25. Program Lock bits
Program Lock Bits
Security level
1UUU
2PUU
U: unprogrammed
P: programmed
LB1LB2LB3
No program lock features enabled. Code verify will still be encrypted by the encryption
array if programmed. MOVCinstruction executed from external program memory returns
non encrypted data.
MOVC instruction executed from external program memory are disabled from fetching
code bytes from internal memory, EA is sampled and latched on reset.
Protection description
8.2.3 Signature bytes
The TS83C51U2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described
in section 10.
8.2.4 Verify Algorithm
Refer to 9.3.4
44Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
9. TS87C51U2 EPROM
9.1 EPROM Structure
The TS87C51U2 EPROM is divided in two different arrays:
The program Lock system, when programmed, protects the on-chip program against software piracy.
9.2.1 Encryption Array
Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time
a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.
9.2.2 Program Lock Bits
The three lock bits, when programmed according to Table 26., will provide different level of protection for the
on-chip code and data.
Table 26. Program Lock bits
Program Lock Bits
Security
level
1UUU
2PUU
3UPUSame as 2, also verify is disabled.
4UUPSame as 3, also external execution is disabled.
LB1LB2LB3
Noprogram lock featuresenabled. Code verifywill still be encrypted by the encryption
array if programmed. MOVC instruction executed from external program memory
returns non encrypted data.
MOVCinstructionexecutedfromexternalprogram memory are disabledfrom fetching
code bytes from internal memory, EA is sampled and latched on reset, and further
programming of the EPROM is disabled.
U: unprogrammed,
P: programmed
Protection description
WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification.
Rev. D - 15 January, 200145
TS80C51U2
TS83C51U2
TS87C51U2
9.2.3 Signature bytes
The TS87C51U2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described
in section 10.
9.3 EPROM Programming
9.3.1 Set-up modes
In order to program and verify the EPROM or to read the signature bytes, the TS87C51U2 is placed in specific
set-up modes (See Figure 14.).
Control and program signals must be held at the levels indicated in Table 27.
9.3.2 Definition of terms
Address Lines:P1.0-P1.7, P2.0-P2.5 respectively for A0-A13.
Data Lines:P0.0-P0.7 for D0-D7
Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.
Program Signals:ALE/PROG, EA/VPP.
Table 27. EPROM Set-Up Modes
ModeRSTPSEN
Program Code data1012.75V01111
Verify Code data10110011
Program Encryption Array
Address 0-3Fh
Read Signature Bytes10110000
Program Lock bit 11012.75V11111
Program Lock bit 21012.75V11100
Program Lock bit 31012.75V10110
1012.75V01101
ALE/
PROG
EA/
VPP
P2.6P2.7P3.3P3.6P3.7
46Rev. D - 15 January, 2001
PROGRAM
SIGNALS*
EA/VPP
ALE/PROG
TS80C51U2
TS83C51U2
TS87C51U2
+5V
VCC
D0-D7
A0-A7
A8-A13
CONTROL
SIGNALS*
* See Table 31. for proper value on these inputs
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
XTAL14 to 6 MHz
P0.0-P0.7
P1.0-P1.7
P2.0-P2.5
VSS
GND
Figure 14. Set-Up Modes Configuration
9.3.3 Programming Algorithm
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses
applied during byte programming from 25 to 1.
To program the TS87C51U2 the following sequence must be exercised:
● Step 1: Activate the combination of control signals.
● Step 2: Input the valid address on the address lines.
● Step 3: Input the appropriate data on the data lines.
● Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
● Step 5: Pulse ALE/PROG once.
● Step 6: Lower EA/VPP from VPP to VCC
Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is
reached (See Figure 15.).
9.3.4 Verify algorithm
Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify
of the programmed array will ensure reliable programming of the TS87C51U2.
P 2.7 is used to enable data output.
To verify the TS87C51U2 code the following sequence must be exercised:
● Step 1: Activate the combination of program and control signals.
● Step 2: Input the valid address on the address lines.
● Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification (See Figure 15.)
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the
code array is well encrypted.
Rev. D - 15 January, 200147
TS80C51U2
TS83C51U2
TS87C51U2
A0-A12
D0-D7
ALE/PROG
EA/VPP
Control signals
Programming Cycle
Data In
100µs
12.75V
5V
0V
Read/Verify Cycle
Data Out
Figure 15. Programming and Verification Signal’s Waveform
9.4 EPROM Erasure (Windowed Packages Only)
Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full
functionality.
Erasure leaves all the EPROM cells in a 1’s state (FF).
9.4.1 Erasure Characteristics
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15
W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm2rating for 30 minutes, at a distance
of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers.
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately
4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources
over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause
inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque
label be placed over the window.
48Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
10. Signature Bytes
The TS83/87C51U2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the
procedure for EPROM verify but activate the control lines provided in Table 27. for Read Signature Bytes. Table
28. shows the content of the signature byte for the TS83/87C51U2.
Ambiant Temperature Under Bias:
C = commercial0°Cto70°C
I = industrial-40°Cto85°C
Storage Temperature-65°Cto+150°C
Voltage on VCCto V
Voltage on VPPto V
Voltage on Any Pin to V
Power Dissipation1 W
NOTES
1.
Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.
2.This value is based on the maximum allowable die temperature and the thermal resistance of the package.
SS
SS
SS
(1)
-0.5Vto+7V
-0.5Vto+13V
-0.5VtoVCC+ 0.5 V
(2)
11.2 Power consumption measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset,
which made sense for the designs were the CPU was running under reset. In Atmel Wireless & Microcontrollers
new devices, the CPU is no more active during reset, so the power consumption is very low but is not really
representative of what will happen in the customer system. That’s why, while keeping measurements under Reset,
Atmel Wireless & Microcontrollers presents a new way to measure the operating Icc:
Using an internal test ROM, the following code is executed:
Label:SJMP Label (80 FE)
Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1
is driven by the clock.
This is much more representative of the real operating Icc.
50Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
11.3 DC Parameters for Standard Voltage
TA =0°Cto+70°C; VSS=0V;VCC=5V± 10%;F=0to40MHz.
TA = -40°Cto+85°C; VSS=0V;VCC=5V± 10%;F=0to40MHz.
Table 29. DC Parameters in Standard Voltage
SymbolParameterMinTypMaxUnitTest Conditions
V
V
V
V
V
V
V
Input Low Voltage-0.50.2 VCC - 0.1V
IL
Input High Voltage except XTAL1, RST0.2 VCC+ 0.9VCC + 0.5V
IH
Input High Voltage, XTAL1, RST0.7 V
IH1
OL
Output Low Voltage, ports 1, 2, 3
OL1
Output Low Voltage, port 0
Output Low Voltage, ALE, PSEN0.3
OL2
Output High Voltage, ports 1, 2, 3VCC - 0.3
OH
(6)
(6)
CC
VCC - 0.7
V
- 1.5
CC
VCC + 0.5V
0.3
0.45
1.0
0.3
0.45
1.0
0.45
1.0
V
V
V
V
V
V
V
V
V
V
V
V
IOL = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA
IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
IOL = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
VCC = 5 V ± 10%
V
Output High Voltage, port 0VCC - 0.3
OH1
VCC - 0.7
VCC - 1.5
V
V
V
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
VCC = 5 V ± 10%
V
R
I
C
I
I
under
RESET
Output High Voltage,ALE, PSENVCC - 0.3
OH2
VCC - 0.7
VCC - 1.5
RST Pulldown Resistor50
RST
I
Logical 0 Input Current ports 1, 2 and 3-50µAVin = 0.45 V
IL
I
Input Leakage Current±10µA0.45 V < Vin < V
LI
Logical 1 to 0 Transition Current, ports 1, 2, 3-650µAVin = 2.0 V
TL
Capacitance of I/O Buffer10pFFc = 1 MHz
IO
Power Down Current
PD
Power Supply Current Maximum values, X1
CC
mode:
(7)
(5)
90
(5)
20
200kΩ
50µA
1 + 0.4 Freq
(MHz)
@12MHz 5.8
V
V
V
mA
@16MHz 7.4
IOH = -100 µA
IOH = -1.6 mA
IOH = -3.5 mA
= 5 V ± 10%
V
CC
A = 25°C
T
2.0 V < V
CC <
VCC = 5.5 V
5.5 V
(1)
CC
(3)
Rev. D - 15 January, 200151
TS80C51U2
TS83C51U2
TS87C51U2
SymbolParameterMinTypMaxUnitTest Conditions
I
operating
I
idle
Power Supply Current Maximum values, X1
CC
CC
(7)
mode:
Power Supply Current Maximum values, X1
(7)
mode:
3 + 0.6 Freq
(MHz)
@12MHz 10.2
@16MHz 12.6
0.25+0.3Freq
(MHz)
@12MHz 3.9
mA
mA
VCC = 5.5 V
VCC = 5.5 V
(8)
(2)
@16MHz 5.1
11.4 DC Parameters for Low Voltage
TA =0°Cto+70°C; VSS=0V;VCC=2.7Vto5.5V;F=0to30MHz.
TA = -40°Cto+85°C; VSS=0V;VCC=2.7Vto5.5V;F=0to30MHz.
Table 30. DC Parameters for Low Voltage
SymbolParameterMinTypMaxUnitTest Conditions
V
V
V
V
Input Low Voltage-0.50.2 VCC - 0.1V
IL
Input High Voltage except XTAL1, RST0.2 VCC + 0.9VCC + 0.5V
IH
Input High Voltage, XTAL1, RST0.7 V
IH1
OL
Output Low Voltage, ports 1, 2, 3
(6)
CC
VCC + 0.5V
0.45V
IOL = 0.8 mA
(4)
V
OL1
V
V
OH1
I
I
I
R
RST
Output Low Voltage, port 0, ALE, PSEN
Output High Voltage, ports 1, 2, 30.9 V
OH
Output High Voltage, port 0, ALE, PSEN0.9 V
Logical 0 Input Current ports 1, 2 and 3-50µAVin = 0.45 V
IL
Input Leakage Current±10µA0.45 V < Vin < V
LI
Logical 1 to 0 Transition Current, ports 1, 2, 3-650µAVin = 2.0 V
TL
RST Pulldown Resistor50
(6)
CC
CC
(5)
90
0.45V
200kΩ
IOL = 1.6 mA
VIOH = -10 µA
VIOH = -40 µA
CIOCapacitance of I/O Buffer10pFFc = 1 MHz
A = 25°C
T
I
PD
I
CC
under
RESET
I
CC
operating
Power Down Current
Power Supply Current Maximum values, X1
(7)
mode:
Power Supply Current Maximum values, X1
(7)
mode:
(5)
20
(5)
10
50
30
µA
VCC = 2.0 V to 5.5 V
VCC = 2.0 V to 3.3 V
1 + 0.2 Freq
(MHz)
@12MHz 3.4
VCC = 3.3 V
mA
@16MHz 4.2
1 + 0.3 Freq
(MHz)
@12MHz 4.6
VCC = 3.3 V
mA
@16MHz 5.8
(4)
CC
(3)
(3)
(1)
(8)
52Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
SymbolParameterMinTypMaxUnitTest Conditions
I
CC
idle
NOTES
1.I
CC
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used..
2.Idle ICCis measured with all output pins disconnected; XTAL1 driven with T
N.C; Port 0 = VCC; EA = RST = VSS (see Figure 18.).
3.Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 19.).
4.Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports1 and 3. The noise is
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOLpeak 0.6V.A Schmitt Triggeruse is not necessary.
5.Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6.Under steady state (non-transient) conditions, I
Maximum IOL per port pin: 10 mA
Maximum I
Port 0: 26 mA
7.For other values, please contact your sales office.
8.Operating ICC is measured with all output pins disconnected; XTAL1 driven with T
VIH=VCC- 0.5V;XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICCwould be slightly
higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case.
Power Supply Current Maximum values, X1
(7)
mode:
under reset is measured with all output pins disconnected; XTAL1 driven with T
CLCH,TCHCL
must be externally limited as follows:
OL
per 8-bit port:
OL
for all output pins: 71 mA
OL
0.15 Freq
(MHz) + 0.2
@12MHz 2
@16MHz 2.6
, T
CLCH
CLCH
= 5 ns (see Figure 20.), VIL = VSS + 0.5 V,
CHCL
= 5 ns, VIL=VSS+ 0.5 V,VIH=VCC- 0.5 V; XTAL2
, T
= 5 ns (see Figure 20.), VIL = VSS + 0.5 V,
CHCL
mA
VCC = 3.3 V
(2)
V
CC
I
CC
V
CC
V
CC
P0
EA
(NC)
CLOCK
SIGNAL
V
CC
RST
XTAL2
XTAL1
V
SS
Figure 16. ICCTest Condition, under reset
All other pins are disconnected.
Rev. D - 15 January, 200153
TS80C51U2
TS83C51U2
TS87C51U2
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
V
CC
I
CC
V
CC
V
CC
P0
EA
(NC)
CLOCK
SIGNAL
Figure 17. Operating ICCTest Condition
Reset = Vss after a high pulse
during at least 24 clock cycles
(NC)
CLOCK
SIGNAL
Figure 18. ICCTest Condition, Idle Mode
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
XTAL2
XTAL1
V
SS
RST
XTAL2
XTAL1
V
SS
V
CC
EA
I
P0
CC
All other pins are disconnected.
V
CC
I
CC
V
CC
V
CC
P0
EA
All other pins are disconnected.
V
CC
V
CC
(NC)
XTAL2
XTAL1
V
SS
All other pins are disconnected.
Figure 19. ICCTest Condition, Power-Down Mode
VCC-0.5V
0.45V
T
CHCL
T
CLCH
= T
CHCL
T
CLCH
= 5ns.
0.7V
CC
0.2VCC-0.1
Figure 20. Clock Signal Waveform for ICCTests in Active and Idle Modes
54Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
11.5 AC Parameters
11.5.1 Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.
Example:T
T
= Time for ALE Low to PSEN Low.
LLPL
TA =0to+70°C (commercial temperature range); VSS=0V;VCC=5V± 10%; -M and -V ranges.
TA = -40°Cto+85°C (industrial temperature range); VSS=0V; VCC=5V± 10%; -M and -V ranges.
TA =0to+70°C (commercial temperature range); VSS=0V;2.7V<V
TA = -40°Cto+85°C (industrial temperature range); VSS=0V;2.7V<V
Table 31. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals.
Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings
will then be degraded.
Port 010050100
Port 1, 2, 3805080
ALE / PSEN10030100
Table 33., Table 36. and Table 39. give the description of each AC symbols.
Table 34., Table 37. and Table 40. give for each range the AC parameter.
= Time for Address Valid to ALE Low.
AVLL
Table 31. Load Capacitance versus speed range, in pF
-M-V-L
5.5 V; -L range.
CC <
5.5 V; -L range.
CC <
Table 35., Table 38. and Table 41. give the frequency derating formula of the AC parameter. To calculate each
AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value
in the formula. Values of the frequency must be limited to the corresponding speed grade:
Table 32. Max frequency for derating formula regarding the speed grade
AC inputs during testing are driven at VCC- 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement
are made at VIHmin for a logic “1” and VILmax for a logic “0”.
0.2VCC+0.9
0.2VCC-0.1
11.5.14 Float Waveforms
FLOAT
VOH-0.1 V
VOL+0.1 V
V
LOAD
V
V
LOAD
LOAD
Figure 28. Float Waveforms
+0.1 V
-0.1 V
64Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded VOH/VOLlevel occurs. IOL/IOH≥±20mA.
11.5.15 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
INTERNAL
CLOCK
XTAL2
ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
P2 (EXT)
READ CYCLE
RD
P0
P2
WRITE CYCLE
WR
P0
STATE4STATE5
P1P2P1P2
DAT A
SAMPLED
FLOATFLOAT
PCL OUT
INDICATES ADDRESS TRANSITIONS
DPL OR Rt OUT
DPL OR Rt OUT
P1P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
STATE6
STATE1STATE2STATE3STATE4
P1P2P1P2P1P2
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
DAT A
SAMPLED
PCL OUT
SAMPLED
FLOAT
FLOAT
STATE5
P1P2P1P2
DAT A
PCLOUT(EVEN IF PROGRAM
MEMORY IS INTERNAL)
PCL OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P2
PORT OPERATION
MOV DEST P0
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
OLD DATA
P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLEDRXD SAMPLED
NEW DATA
P1, P2, P3 PINS SAMPLED
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0 PINS SAMPLED
Figure 29. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded)
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
Part Number
TS80C51U2:ROMless
TS83C51U2zzz: 16k ROM, zzz is the customer code
TS87C51U2:16k OTP EPROM
R: Tape & Reel
D: Dry Pack
B: Tape & Reel and
Dry Pack
Temperature Range
I: Commercial and Industrial -40 to 85oC
(*) Check with Atmel Wireless & Microcontrollers Sales Office for availability - Ceramic parts only for OTP (TS87C51U2)
Ceramic packages (J, K) are available for prototyping, not for volume production.