ATMEL T98C51CC01 User Manual

Features

• 80C51 Core Architecture

• 256 Bytes of On-chip RAM

• 1K Bytes of On-chip XRAM

• 32K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°C

Erase/Write Cycle: 100K

• Boot Code Section with Independent Lock Bits

• 2K Bytes of On-chip Flash for Bootloader

• In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability

• 2K Bytes of On-chip EEPROM

Erase/Write Cycle: 100K

• 14-sources 4-level Interrupts

• Three 16-bit Timers/Coun ter s

• Full Duplex UART Compatible 80C51

• Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)

• Five Ports: 32 + 2 Digital I/O Lines

• Five-channel 16-bit PCA with:

– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture

• Double Data Pointer

• 21-bit Watchdog Timer (7 Programmable Bits)

• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

• Full CAN Controller:

– Fully Compliant with CAN Rev2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 15 Independent Message Objects:

Each Message Object Programmable on Transmission or Reception
Individual Tag and Mask Filters up to 29-bit Identifier/Channel
8-byte Cyclic Data Register (FIFO)/Message Object
16-bit Status and Control Register/Message Object
16-bit Time-Stamping Registe r/Message Object
CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
Access to Message Object Control and Da ta Registers Via SFR
Programmable Reception Buffer Length Up To 15 Message Objects
Priority Management of Reception of Hits on Several Message Objects at the
Same Time (Basic CAN Feature)
Priority Management for Transmission
Message Object Overrun Interrupt

– Supports:

Time Triggered Communication
Autobaud and Listening Mode

Programmable Automatic Reply Mode
– 1-Mbit/s Maximum Transfer Rate at 8 MHz
– Readable Error Counters
– Programmable Link to On-chip Timer for Time Stamping and Network

Synchronization
– Independent Baud Rate Prescaler
– Data, Remote, Error and Overload Frame Handling

• On-chip Emulation Logic (Enhanced Hook System)

• Power Saving Modes:

–Idle Mode
– Power-down Mode

(1)

Crystal Frequency in X2 Mode

Enhanced 8-bit
Microcontroller
with CAN
Controller and
Flash Memory

T89C51CC01
AT89C51CC01

1. At BRP = 1 sam pling point will be fixed.

Rev. 4129L–CAN–08/05

1

A/T89C51CC01

• Power Supply: 3V to 5.5V

• Temperature Range: Industrial (-40° to +85°C)

• Packages: VQFP44, PLCC44, CA-BGA64

Description The T89C51CC01 is the first member of the CANary

dedicated to CAN network applications.
In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
Besides the full CAN co ntroller T89C51CC 01 provides 32K Byte s of Flash memory

including In-System-Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes
EEPROM and 1.2-Kbyte RAM.

Special attention is paid to the reduction of the electro-magnetic emission of
T89C51CC01.

Block Diagram

Vss

IB-bus

Flash

32kx

8

Vcc

Boot

loader

2kx8

EE

PROM

2kx8

XRAM

1kx8

XTAL1
XTAL2

ALE

PSEN

CPU

RxD

UART

TxD

C51

CORE

RAM

256x8

TM

family of 8-bit microcontrollers

TxDC

ECI

PCA

PCA

T2EX

Timer 2

RxDC

T2

CAN

CONTROLLER

EA

RD

WR

Notes: 1. 8 analog Inputs/8 Digital I/O

2. 2-Bit I/O Port

Timer 0
Timer 1

T0

RESET

T1

INT
Ctrl

INT0

Parallel I/O Ports and Ext. Bus

Port 0P0Port 1

INT1

Port 2

P1(1)

P2

Port 3

P3

Port 4

P4(2)

Watch

Dog

10 bit

ADC

VAREF

VAVCC

VAGND

2

4129L–CAN–08/05

Pin Configuration

P1.4/AN4/CEX1
P1.5/AN5/CEX2
P1.6/AN6/CEX3
P1.7/AN7/CEX4

EA

P3.0/RxD

P3.1/TxD
P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

7
8
9
10
11
12
13
14
15
16
17

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

65432

PLCC44

VAREF

VAGND

RESET

1

4443424140

A/T89C51CC01

VSS

VCC

XTAL1

XTAL2

39

ALE

38

PSEN

37

P0.7/AD7

36

P0.6/AD6

35

P0.5/AD5

34

P0.4/AD4

33

P0.3/AD3

32

P0.2/AD2

31

P0.1/AD1

30

P0.0/AD0

29

P2.0/A8

P1.4/AN4/CEX1
P1.5/AN5/CEX2
P1.6/AN6/CEX3
P1.7/AN7/CEX4

EA

P3.0/RxD

P3.1/TxD
P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

1819202122232425262728

P3.7/RD

1

2

3
4

5

6
7

8
9
10
11

P1.3/AN3/CEX0

P3.6/WR

P1.2/AN2/ECI

43 42 41 40 3944

P4.1/RxDC

P4.0/ TxDC

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VQFP44

P2.7/A15

P2.6/A14

P2.5/A13

VAGND

RESET

VSS

38 37 36 35 34

12 13 17161514 201918 21 22

P2.4/A12

P2.1/A9

P2.3/A11

P2.2/A10

VCC

XTAL1

XTAL2

33

ALE

32

PSEN

31

P0.7/AD7

30

P0.6/AD6

29

P0.5/AD5

28

P0.4 /AD4

27

P0.3 /AD3

26

P0.2 /AD2

25

P0.1 /AD1

24

P0.0 /AD0

23

P2.0/A8

4129L–CAN–08/05

P3.7/RD

P3.6/WR

P2.7/A15

P2.6/A14

P2.5/A13

P4.0/TxDC

P4.1/RxDC

P2.4/A12

P2.1/A9

P2.3/A11

P2.2/A10

3

A/T89C51CC01

CA-BGA64 To p View

21 345678

A

B

C

D

E

F

G

H

EA

P3.0

P3.2

P3.4

P3.6

P1.2/AN2P1.4/AN4 P1.0/AN0

P1.3/AN3P1.5/AN5

P1.6/AN6

NC

P3.1

P3.3 NC

P3.5

P1.1/AN1

NC

NC NC RESET

NC

P4.0

P2.7P3.7

VAGND

VAREF VDD

NCP1.7/AN7

NC

NC

P4.1

P2.6

VSS

VDD

NC

NC

NC

P2.4

P2.5 P2.3 P2.1 P2.0

VSS XTAL1

NC P0.6

NC P0.2 P0.4

NC P0.1 P0.3

P2.2 NC P0.0

NC ALE

PSENNC

XTAL2

P0.7

P0.5

4

4129L–CAN–08/05

Table 1. Pin Description

Pin Name Type Description

VSS GND Circuit ground
VCC Supply Voltage

VAREF Reference Voltage for ADC (input)

VAGND Reference Ground for ADC (internally connected to VSS)

P0.0:7 I/O Port 0:

Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as
high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program
and Data Memory. In this application it uses strong internal pull-ups when emitting 1’s.
Port 0 also outputs the code Bytes during program validation. External pull-ups are required during program verification.

A/T89C51CC01

P1.0:7 I/O Port 1:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for
the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors
and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current
(I

, see section "Electrical Characteristic") because of the internal pull-ups. Port 1 pins are assigned to be used as analog

IL

inputs via the ADCCF register (in this case the internal pull-ups are disconnected).
As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and
the PCA module I/O.

P1.0/AN0/T2
Analog input channel 0,
External clock input for Timer/counter2.

P1.1/AN1/T2EX
Analog input channel 1,
Trigger input for Timer/counter2.

P1.2/AN2/ECI
Analog input channel 2,
PCA external clock input.

P1.3/AN3/CEX0
Analog input channel 3,
PCA module 0 Entry of input/PWM output.

P1.4/AN4/CEX1
Analog input channel 4,
PCA module 1 Entry of input/PWM output.

P1.5/AN5/CEX2
Analog input channel 5,
PCA module 2 Entry of input/PWM output.

P1.6/AN6/CEX3
Analog input channel 6,
PCA module 3 Entry of input/PWM output.

P1.7/AN7/CEX4
Analog input channel 7,
PCA module 4 Entry ot input/PWM output.
Port 1 receives the low-order address byte during EPROM programming and program verification.
It can drive CMOS inputs without external pull-ups.

P2.0:7 I/O Port 2:

4129L–CAN–08/05

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal
pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of
current (I
during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses
(MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1’s. During accesses to external Data
Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register.
It also receives high-order addresses and control signals during program validation.
It can drive CMOS inputs without external pull-ups.

, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byte

IL

5

A/T89C51CC01

Table 1. Pin Description (Continued)

Pin Name Type Description

P3.0:7 I/O Port 3:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal
pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a
source of current (I
The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for
TxD and WR

P3.0/RxD:
Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface

P3.1/TxD:
Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface

P3.2/INT0
External interrupt 0 input/timer 0 gate control input

P3.3/INT1
External interrupt 1 input/timer 1 gate control input

P3.4/T0:
Timer 0 counter input

P3.5/T1:
Timer 1 counter input

P3.6/WR
External Data Memory write strobe; latches the data byte from port 0 into the external data memory

P3.7/RD
External Data Memory read strobe; Enables the external data memory.
It can drive CMOS inputs without external pull-ups.

). The secondary functions are assigned to the pins of port 3 as follows:

:

:

:

:

, see section "Electrical Characteristic") because of the internal pull-ups.

IL

P4.0:1 I/O Port 4:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal
pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of
current (IIL, on the datasheet) because of the internal pull-up transistor.
The output latch corresponding to a secondary function RxDC must be programmed to one for that function to operate. The
secondary functions are assigned to the two pins of port 4 as follows:

P4.0/TxDC:
Transmitter output of CAN controller

P4.1/RxDC:
Receiver input of CAN controller.
It can drive CMOS inputs without external pull-ups.

6

4129L–CAN–08/05

Table 1. Pin Description (Continued)

Pin Name Type Description

Reset:

RESET I/O

ALE O

PSEN O

EA I

XTAL1 I

A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down
resistor to VSS permits power-on reset using only an external capacitor to VCC.

ALE:

An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is
activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are
executed from an internal Flash (EA

PSEN

:

The Program Store Enable output is a control signal that enables the external program memory of the bus during external
fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when
executing from of the external program memory two activations of PSEN are skipped during each access to the external Data
memory. The PSEN is not activated for internal fetches.

:

EA

When External Access is held at the high level, instructions are fetched from the internal Flash when the program counter is
less then 8000H. When held at the low level,T89C51CC01 fetches all instructions from the external program memory

XTAL1:

Input of the inverting oscillator amplifier and input of the internal clock generator circuits.
To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate
above a frequency of 16 MHz, a duty cycle of 50% should be maintained.

A/T89C51CC01

= 1), ALE generation can be disabled by the software.

.

XTAL2 O

XTAL2:

Output from the inverting oscillator amplifier.

I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A

CPU "write to latch" signal initiate s tran sfer of int ernal bus data int o the type -D latch. A
CPU "read latch" signal transfers the latched Q outpu t onto the i nterna l bu s. S im ilar ly, a
"read pin" signal transfers the logical level of the Port pin. Some Port data instructions
activate the "read la tch " signal while others ac tiva te the "r ead pi n" signa l. L atch in struc­tions are referred to as Read-Modify-Write instructions. Each I/O line may be
independently programmed as input or output.

Port 1, Port 3 and Port 4 Figure 1 shows the structur e of Ports 1 and 3, whic h have inter nal pul l-ups. A n externa l

source can pull the pin l ow. Ea ch P ort pi n can be c onfigu red e ither for gene ral-pu rpose
I/O or for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg­ister (x = 1,3 or 4). To use a pi n for gener al-pur pose input, s et the bi t in the Px r egister .
This turns off the output FET drive.

To configure a pin for its al ter nat e fun ction, set the bit in the Px register . W hen the l atch
is set, the "alternate out put functi on" si gnal co ntrols the output lev el (see Fi gure 1) . The
operation of Ports 1, 3 an d 4 is discussed fur the r in the "quasi-Bidirectional Port Opera­tion" section.

4129L–CAN–08/05

7

A/T89C51CC01

Figure 1. Port 1, Port 3 and Port 4 Structure

x
x
x

)

VCC

READ
LATCH

ALTERNATE
OUTPUT
FUNCTION

INTERNAL
PULL-UP (1)

P1.
P3.

INTERNAL
BUS

WRITE
TO
LATCH

READ
PIN

D

CL

P3.X
P4.X

LATCH

QP1.X

ALTERNATE
INPUT
FUNCTION

P4.

Note: The internal pull-up can be disabled on P1 when analog function is selected.

Port 0 and Port 2 Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port

0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3
shows the structure of Port 2. An external source can pull a Port 2 pin low.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg­ister (x = 0 or 2). To use a pin for gen eral -purpos e input , set the bit in the Px r egister to
turn off the output driver FET.

Figure 2. Port 0 Structure

ADDRESS LOW/
DATA

READ
LATCH

INTERNAL
BUS

WRITE
TO
LATCH

READ
PIN

D

P0.X

LATCH

Q

Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as

address/data bus drivers.

2. Port 0 internal strong pull-up s as si st th e log ic -one outp ut for m em ory bus cyc les onl y.
Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.

CONTROL

1
0

VDD

(2)

P0.x (1

8

4129L–CAN–08/05

A/T89C51CC01

Figure 3. Port 2 Structure

READ
LATCH

INTERNAL
BUS

WRITE
TO
LATCH

READ
PIN

D

P2.X

LATCH

ADDRESS HIGH/

Q

CONTROL

1
0

Notes: 1. Port 2 is precluded from use as gen era l-pu r po se I/O Ports when as address /data bus

drivers.

2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for
memory bus cycle.

VDD

INTERNAL
PULL-UP (2)

P2.x (1)

Read-Modify-Write Instructions

When Port 0 and Port 2 are used for an external memory cycle, an internal control signal
switches the output-driver input from the latch output to the internal address/data line.

Some instructions rea d the l atch data rath er th an the pin da ta. T he latch based inst ruc­tions read the data , m odi fy th e d ata and th en r ewrite th e l atc h. Thes e ar e ca ll ed "Re ad­Modify-Write" instructions. Below is a complete list of these special instructions (see
Table ). When the destination operand is a Port or a Port bit, these instructions read the
latch rather than the pin:

Table 2. Re ad-Modify-Write Instruction s

Instruction Description Example

ANL logical AND ANL P1, A
ORL logical OR ORL P2, A
XRL logical EX-OR XRL P3, A
JBC jump if bit = 1 and clear bit J BC P1. 1, LABEL
CPL complement bit CPL P3.0

INC increment INC P2

DEC decrement DEC P2

4129L–CAN–08/05

DJNZ decrement and jump if not zero DJNZ P3, LABEL

MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C

CLR Px.y clear bit y of Port x CLR P2.4
SET Px.y set bit y of Port x SET P3.3

9

A/T89C51CC01

It is not obvious the last three instructions in this list are Read-Modify-Write instructions.

x
x
x
x

These instructions read the port (all 8 bits), modify the specifically addressed bit and
write the new byte back t o the lat ch. Thes e Read- Modif y-Write i nstruc tions a re dire cted
to the latch rather than the pin in order to avoid possible misinterpretation of voltage
(and therefore, logi c) leve ls at th e pin. Fo r exam ple, a P ort bit us ed to dr ive the ba se of
an external bipolar t ransis tor can not rise abov e the tra nsistor’s b ase-emi tter junctio n
voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU
to read the Port at the pi n are misinte rpreted as lo gic zero. A rea d of the latch rath er
than the pins returns the correct logic-one value.

Quasi-Bidirectional Port Operation

Port 1, Port 2, Port 3 an d Port 4 have fix ed internal pul l-ups and are ref erred to as
"quasi-bidirection al " Por ts . Wh en c onf igu re d as an inp u t, th e pin impedance appears as
logic one and sources current in response to an external logic zero condition. Port 0 is a
"true bidirectional" pin. The pins float when configured as input. Resets write logic one to
all Port latches. If logi cal zero i s subseque ntly writte n to a Port latch , it can be retur ned
to input conditions by a logical one written to the latch.

Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output

buffers (and therefore the pin state) update early in the instruction after Read-Modify­Write instruction cycle.

Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull­up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This
extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock
periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull­ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses
logical zero and off when the gate senses logical one. pFET #1 is turned on for two
oscillator periods immediately after a zero-to-one tr ansition in the Port latch. A logical
one at the Port pin turns on pFE T #3 (a we ak pul l-up ) th rough the i nv ert er. T his i nver ter
and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched
on whenever the associated nF ET is switched off. This is tradi tional CMOS switch con­vention. Current strengths are 1/10 that of pFET #3.

Figure 4. Internal Pull-Up Configurations

2 Osc. PERIODS

VCCVCCVCC

10

p1(1)

OUTPUT DATA

INPUT DATA

READ PIN

Note: Port 2 p1 assists the logic-one output for memory bus cycles.

p2

n

p3

P1.
P2.
P3.
P4.

4129L–CAN–08/05

A/T89C51CC01

SFR Mapping The Special Function Registers (SFRs) of the T89C51CC01 fall into the following

categories:

Table 3. C51 Core SFRs

MnemonicAddName 76543210

ACCE0hAccumulator ––––––––
B F0hB Register ––––––––
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP81hStack Pointer ––––––––

Data Pointer Low

DPL 82h

DPH 83h

byte
LSB of DPTR

Data Pointer High
byte

MSB of DPTR

––––––––

––––––––

Table 4. I/O Port SFRs

MnemonicAddName 76543210

P080hPort 0 ––––––––
P190hPort 1 ––––––––
P2A0hPort 2 ––––––––
P3B0hPort 3 ––––––––
P4C0hPort 4 (x2) ––––––––

Table 5. Timers SFRs

MnemonicAddName 76543210

TH0 8Ch

TL0 8Ah

TH1 8Dh

TL1 8Bh

TH2 CDh

Timer/Counter 0 High
byte

Timer/Counter 0 Low
byte

Timer/Counter 1 High
byte

Timer/Counter 1 Low
byte

Timer/Counter 2 High
byte

––––––––

––––––––

––––––––

––––––––

––––––––

TL2 CCh

TCON 88h

TMOD 89h

4129L–CAN–08/05

Timer/Counter 2 Low
byte

Timer/Counter 0 and
1 control

Timer/Counter 0 and
1 Modes

––––––––

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

11

A/T89C51CC01

Table 5. Timers SFRs (Continued)

MnemonicAddName 76543210

T2CON C8h

T2MOD C9h

RCAP2H CBh

RCAP2L CAh

WDTRST A6h

WDTPRG A7h

Timer/Counter 2
control

Timer/Counter 2
Mode

Timer/Counter 2
Reload/Capture High
byte

Timer/Counter 2
Reload/Capture Low
byte

Watchdog Timer
Reset

Watchdog Timer
Program

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

––––––T2OEDCEN

––––––––

––––––––

––––––––

–––––S2S1S0

Table 6. Serial I/O Port SFRs

MnemonicAddName 76543210

SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF99hSerial Data Buffer––––––––
SADEN B9h Slave Addres s Mask – – – – – – – –
SADDRA9hSlave Address ––––––––

Table 7. P CA SF Rs

Mnemonic

CCON D8h PCA Timer/Counter Control CF CR – CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA Timer/Counter Mode CIDL WDTE – – – CPS1 CPS0 ECF
CL E9h PCA Timer/Counter Low byte ––––––––
CH F9h PCA Timer/Counter High byte ––––––––
CCAPM0

CCAPM1
CCAPM2
CCAPM3
CCAPM4

CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H

AddName 76543210

DAh

PCA Timer/Counter Mode 0

DBh

PCA Timer/Counter Mode 1

DCh

PCA Timer/Counter Mode 2

DDh

PCA Timer/Counter Mode 3

DEh

PCA Timer/Counter Mode 4

FAh

PCA Compare Capture Module 0 H

FBh

PCA Compare Capture Module 1 H

FCh

PCA Compare Capture Module 2 H

FDh

PCA Compare Capture Module 3 H

FEh

PCA Compare Capture Module 4 H

CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7

–

ECOM0
ECOM1
ECOM2
ECOM3
ECOM4

CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6

CAPP0
CAPP1
CAPP2
CAPP3
CAPP4

CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5

CAPN0
CAPN1
CAPN2
CAPN3
CAPN4

CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4

MAT0
MAT1
MAT2
MAT3
MAT4

CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3

TOG0
TOG1
TOG2
TOG3
TOG4

CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2

PWM0
PWM1
PWM2
PWM3
PWM4

CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1

ECCF0
ECCF1
ECCF2
ECCF3
ECCF4

CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0

12

4129L–CAN–08/05

Table 7. P CA SFRs (Cont inu ed)

Mnemonic

AddName 76543210

A/T89C51CC01

CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L

EAh

PCA Compare Capture Module 0 L

EBh

PCA Compare Capture Module 1 L

ECh

PCA Compare Capture Module 2 L

EDh

PCA Compare Capture Module 3 L

EEh

PCA Compare Capture Module 4 L

CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7

CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6

CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5

CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4

CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3

CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2

CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1

CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0

Table 8. Interrupt SFRs

MnemonicAddName 76543210

IEN0 A8h

IEN1 E8h

IPL0 B8h

IPH0 B7h

IPL1 F8h

IPH1 F7h

Interrupt Enable
Control 0

Interrupt Enable
Control 1

Interrupt Priorit y
Control Low 0

Interrupt Priorit y
Control High 0

Interrupt Priorit y
Control Low 1

Interrupt Priorit y
Control High1

EA EC ET2 ES ET1 EX1 ET0 EX0

– – – – – ETIM EADC ECAN

– PPC PT2 PS PT1 PX1 PT0 PX0

– PPCH PT2H PSH PT1H PX1H PT0H PX0H

– – – – – POVRL PADCL PCANL

–––––POVRHPADCHPCANH

Table 9. ADC SFRs

MnemonicAddName 76543210

ADCON F3h ADC Control – PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0
ADCF F6h ADC Configuration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
ADCLK F2h ADC Clock – – – PRS4 PRS3 PRS 2 PRS1 PRS0
ADDH F5h ADC Data High byte ADAT9 ADAT8 ADAT7 A DAT6 ADAT5 ADAT4 A DAT3 ADAT2
ADDL F4h ADC Data Low byte – – – – – – ADAT1 ADAT0

Table 10. CAN SFRs

MnemonicAddName 76543210

CANGCON ABh

CANGSTA AAh

CANGIT 9Bh

CANBT1 B4h CAN Bit Timing 1 – BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 –
CANBT2 B5h CAN Bit Timing 2 – SJW1 SJW0 – PRS2 PRS1 PRS0 –

CAN General
Control

CAN General
Status

CAN General
Interrupt

ABRQ OVRQ TTC SYNCTTC

– OVFG – TBSY RBSY ENFG BOFF ERRP

CANIT – OVRTIM OVRBUF SERG CERG FERG AERG

AUT–

BAUD

TEST ENA GRES

CANBT3 B6h CAN Bit Timing 3 – PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP

4129L–CAN–08/05

13

A/T89C51CC01

Table 10. CAN SFRs (Continued)

MnemonicAddName 76543210

CANEN1 CEh

CANEN2 CFh

CANGIE C1h

CANIE1 C2h

CANIE2 C3h

CANSIT1 BA h

CANSIT2 BB h

CANTCON A1h

CANTIMH ADh CAN Timer high

CAN Enable
Channel byte 1

CAN Enable
Channel byte 2

CAN General
Interrupt Enable

CAN Interrupt
Enable Channel
byte 1

CAN Interrupt
Enable Channel
byte 2

CAN Status
Interrupt Channel
byte1

CAN Status
Interrupt Channel
byte2

CAN Timer
Control

– ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8

ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0

– – ENRX ENTX ENERCH ENBUF ENERG –

– IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8

IECH7 IECH6 IECH5 IECH4 IECH3 IECH2 IECH1 IECH0

– SIT14 SIT13 SIT12 SIT11 SIT10 S IT 9 SIT8

SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0

TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0

CANTIM 15CANTIM 14CANTIM 13CANTIM 12CANTIM 11CANTIM 10CANTIM 9CANTIM

8

CANTIML ACh CAN Timer low CANTIM 7 CANTIM 6 CANTIM 5 CANTIM 4 CANTIM 3 CANTIM 2 CANTIM 1 CANTIM 0

CANSTMH AFh

CANSTML AEh

CANTTCH A5h

CANTTCL A4h

CANTEC 9Ch

CANREC 9Dh

CANPAGE B1h CAN Page CHNB3 CHNB2 CHNB1 CHNB0 AINC INDX2 INDX1 INDX0

CANSTCH B2h

CANCONH B3h

CANMSG A3h

CAN Timer Stamp
high

CAN Timer Stamp
low

CAN Timer TTC
high

CAN Timer TTC
low

CAN Transmit
Error Counter

CAN Receive
Error Counter

CAN Status
Channel

CAN Control
Channel

CAN Message
Data

TIMSTMP 15TIMSTMP 14TIMSTMP 13TIMSTMP 12TIMSTMP 11TIMSTMP 10TIMSTMP 9TIMSTMP

TIMSTMP7TIMSTMP 6TIMSTMP 5TIMSTMP 4TIMSTMP 3TIMSTMP 2TIMSTMP 1TIMSTMP

TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 1 0 TIM TTC 9 TIMTTC 8

TIMTTC

7

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

DLCW TXOK RXOK BERR SERR CERR FERR AERR

CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0

MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0

TIMTTC

6

TIMTTC5TIMTTC

4

TIMTTC

3

TIMTTC

2

TIMTTC1TIMTTC

8

0

0

14

4129L–CAN–08/05

A/T89C51CC01

Table 10. CAN SFRs (Continued)

MnemonicAddName 76543210

CANIDT1 BCh

CANIDT2 BDh

CANIDT3 BEh

CANIDT4 BFh

CANIDM1 C4h

CANIDM2 C5h

CAN Identifier T ag
byte 1(Part A)

CAN Identifier T ag
byte 1(PartB)

CAN Identifier T ag
byte 2 (PartA)

CAN Identifier T ag
byte 2 (PartB)

CAN Identifier T ag
byte 3(PartA)

CAN Identifier T ag
byte 3(PartB)

CAN Identifier T ag
byte 4(PartA)

CAN Identifier T ag
byte 4(PartB)

CAN Identifier
Mask byte
1(PartA)

CAN Identifier
Mask byte
1(PartB)

CAN Identifier
Mask byte
2(PartA)

CAN Identifier
Mask byte
2(PartB)

IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 IDT4 IDT3

IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21

IDT2

IDT20

–

IDT12

–

IDT4

IDMSK10

IDMSK28

IDMSK2

IDMSK20

IDT1

IDT19

–

IDT11

–

IDT3

IDMSK9

IDMSK27

IDMSK1

IDMSK19

IDT0

IDT18

–

IDT10

–

IDT2

IDMSK8

IDMSK26

IDMSK0

IDMSK18–IDMSK17–IDMSK16–IDMSK15–IDMSK14–IDMSK13

–

IDT17

–

IDT9

–

IDT1

IDMSK7

IDMSK25

–

IDT16

–

IDT8

–

IDT0

IDMSK6

IDMSK24

–

IDT15

–

IDT7

RTRTAG

–

IDMSK5

IDMSK23

–

IDT14

–

IDT6

–

RB1TAG

IDMSK4

IDMSK22

IDT13

RB0TAG

IDMSK3

IDMSK21

–

–

IDT5

–

CAN Identifier

CANIDM3 C6h

CANIDM4 C7h

Mask byte
3(PartA)

CAN Identifier
Mask byte
3(PartB)

CAN Identifier
Mask byte
4(PartA)

CAN Identifier
Mask byte
4(PartB)

–

IDMSK12–IDMSK11–IDMSK10–IDMSK9–IDMSK8–IDMSK7

–

IDMSK4

–

IDMSK3–IDMSK2

–

IDMSK1–IDMSK0

RTRMSK

–

–

IDMSK6–IDMSK5

–IDEMSK

–

Table 11. Other SFRs

MnemonicAddName 76543210

PCON 87h Power Control SMOD1 SMOD0 – POF GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 – – M0 – XRS1 XRS2 EXTRAM A0
AUXR1 A2h Auxiliary Register 1 – – ENBOOT – GF3 0 – DPS
CKCON 8Fh Clock Control CANX2 W DX 2 P C AX 2 SIX2 T2X2 T1X2 T0X2 X2

4129L–CAN–08/05

15

A/T89C51CC01

Table 11. Other SFRs

MnemonicAddName 76543210

FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY
EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 – – EEE EEBUSY

Table 12. SFR Mapping

(1)

0/8

1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

IPL1

xxxx x000

B

0000 0000

IEN1

xxxx x000

ACC

0000 0000

CCON

00x0 0000

PSW

0000 0000

T2CON

0000 0000

P4

xxxx xx11

IPL0

x000 0000

P3

1111 1111

IEN0

0000 0000

CH

0000 0000

CL

0000 0000

CMOD

00xx x000

FCON

0000 0000

T2MOD

xxxx xx00

CANGIE

11000000

SADEN

0000 0000
CANPAGE

0000 0000

SADDR

0000 0000

CCAP0H

0000 0000

ADCLK

xxx0 0000

CCAP0L

0000 0000

CCAPM0

x000 0000

EECON

xxxx xx00

RCAP2L

0000 0000

CANIE1

x000 0000

CANSIT1

x000 0000

CANSTCH

xxxx xxxx

CANGSTA
1010 0000

CCAP1H

0000 0000

ADCON

x000 0000

CCAP1L

0000 0000

CCAPM1

x000 0000

RCAP2H

0000 0000

CANIE2

0000 0000

CANSIT2

0000 0000

CANCONCH

xxxx xxxx

CANGCON

0000 0000

CCAP2H

0000 0000

ADDL

0000 0000

CCAP2L

0000 0000

CCAPM2

x000 0000

TL2

0000 0000

CANIDM1

xxxx xxxx
CANIDT1

xxxx xxxx

CANBT1

xxxx xxxx

CANTIML

0000 0000

CCAP3H

0000 0000

ADDH

0000 0000

CCAP3L

0000 0000

CCAPM3

x000 0000

TH2

0000 0000

CANIDM2
xxxx xxxx

CANIDT2
xxxx xxxx

CANBT2

xxxx xxxx
CANTIMH

0000 0000

CCAP4H

0000 0000

ADCF

0000 0000

CCAP4L

0000 0000

CCAPM4

x000 0000

CANEN1

x000 0000

CANIDM3

xxxx xxxx
CANIDT3

xxxx xxxx

CANBT3

xxxx xxxx

CANSTMPL

xxxx xxxx

IPH1

xxxx x000

CANEN2

0000 0000

CANIDM4

xxxx xxxx
CANIDT4

xxxx xxxx

IPH0

x000 0000

CANSTMPH

xxxx xxxx

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A0h

98h

90h

88h

80h

P2

1111 1111

SCON

0000 0000

P1

1111 1111

TCON

0000 0000

P0

1111 1111

(1)

0/8

CANTCON

0000 0000

SBUF

0000 0000

TMOD

0000 0000

SP

0000 0111

1/9 2/A 3/B 4/C 5/D 6/E 7/F

Reserved

Note: 1. These registers are bit–addressable.

Sixteen addresses in the SFR space are both byte
whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

16

AUXR1

xxxx 00x0

TL0

0000 0000

DPL

0000 0000

CANMSG
xxxx xxxx

CANGIT

0x00 0000

TL1

0000 0000

DPH

0000 0000

CANTTCL
0000 0000

CANTEC

0000 0000

TH0

0000 0000

–addressable and bit–addressable. The bit–addressable SFR’s are those

CANTTCH
0000 0000

CANREC

0000 0000

TH1

0000 0000

WDTRST
1111 1111

AUXR

x00x 1100

WDTPRG
xxxx x000

CKCON

0000 0000

PCON

00x1 0000

4129L–CAN–08/05

A7h

9Fh

97h

8Fh

87h

A/T89C51CC01

Clock The T89C51CC01 core needs only 6 clock periods per machine cycl e. This feature,

called ”X2”, provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU
power.

• Saves power consumption while keeping the same CPU power (oscillator power
saving).

• Saves power consumption by dividing dynamic operating frequency by 2 in
operating and idle modes.

• Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the ori ginal C51 com patibil ity, a divider -by-2 is in serted betwe en the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by the software.

An extra feature is available to start after Reset in the X2 mode. This feature can be
enabled by a bit X2B in the Hardware Sec urity Byte. Thi s bit is described in the section
"In-System-Programming".

Description T he X2 bit in the CK CON regis ter (see Tabl e 13) allo ws switching from 12 cloc k cycles

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
(STD mode).

Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure

5.).

The Timers 0, 1 and 2, Uart, PCA, W atchdog or CAN switch in X 2 mode onl y if the co r­responding bit is cleared in the CKCON register.

The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1
input. In X2 mode, as thi s divid er is bypas s ed, t he s ig nal s o n XTA L1 m us t hav e a cy clic
ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2
bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2
to the STD mode. Figure 6 shows the mode switching waveforms.

4129L–CAN–08/05

17

A/T89C51CC01

Figure 5. Clock CPU Generation Diagram

X

X

X2B

Hardware byte

On RESET

PCON.0

IDL

X2

CKCON.0

TAL1

÷ 2

0
1

CPU Core
Clock

TAL2

CPU

CLOCK

PD

PCON.1

÷ 2

÷ 2

÷ 2

÷ 2

÷ 2

÷ 2

1
0

÷ 2

1
0

1
0

1
0

1
0

1
0

CPU Core Clock Symbol

1
0

FT0 Clock

FT1 Clock

FT2 Clock

FUart Clock

FPca Cloc k

FWd Clock

FCan Clock

and ADC

18

X2

CKCON.0

CANX2

CKCON.7

WDX2

CKCON.6

PCAX2

CKCON.5

SIX2

CKCON.4

T2X2

CKCON.3

T1X2

CKCON.2

PERIPH

CLOCK

Peripheral Clock Symbol

T0X2

CKCON.1

4129L–CAN–08/05

A/T89C51CC01

Figure 6. Mode Switching Waveforms

XTAL1

XTAL1/2

X2 bit

CPU clock

X2 ModeSTD Mode STD Mode

Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the

clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running
timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have
a 9600 baud rate.

4129L–CAN–08/05

19

A/T89C51CC01

Register Table 13. CKCON Register

CKCON (S:8Fh)
Clock Control Register

76543210

CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit

Number

7CANX2

6WDX2

5PCAX2

4SIX2

3T2X2

2T1X2

1T0X2

Bit

Mnemonic Description

CAN clock

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Watchdog clock

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Arra y cl oc k

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (MODE 0 and 2)

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Timer 2 clock

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Timer 1 clock

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Timer 0 clock

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

(1)

(1)

(1)

(1)

(1)

(1)

(1)

20

CPU clock

0X2

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all
the peripherals.
Set to select 6 clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2"bits.

Note: 1. This control bit is vali dated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = 0000 0000b

4129L–CAN–08/05

A/T89C51CC01

0

Power Management Two power reduction modes are implemented in the T89C51CC01: the Idle mode and

the Power-do wn mode . These modes ar e detai led in th e follo wing se ction s. In ad dition
to these power redu cti on mo des , t he cl oc ks o f th e c ore and peripherals can be dy nam i­cally divided by 2 using the X2 Mode detailed in Section “Clock”.

Reset Pin In order to st art-up (col d rese t) or to restart (war m rese t) p roperl y the micr ocont roller , a

high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of
the internal registers like S F Rs, P C, etc . and to unp re dicta ble behavior of the microcon­troller. A warm reset ca n be applied either dir ectly o n the RST pin or indire ctly by an
internal reset source such as a watchdog, PCA, timer, etc.

At Power-up (Cold Reset) Two conditions are required before enabling a CPU start-up:

• VDD must reach the specified VDD range,

• The level on xtal1 input must be outside the specification (VIH, VIL).

If one of these two conditions are not met, the microcontroller d oes not start cor rectly
and can execute an instruct ion fetch fro m anywhe re in the progr am spac e. An active
level applied on the RST pin must be mainta ined unti l both of th e above c onditi ons are
met. A reset is active wh en the lev el VIH1 is reached an d when the pu lse width c overs
the period of time where VDD and the oscillator are not stabilized. Two parameters have
to be taken into account to determine the reset pulse width:

• VDD rise time (vddrst),

• Oscillator startup time (oscrst).

To determine the capacitor the highest value of these two parameters has to be chosen.
The reset circuitry is shown in Figure 7.

Figure 7. Reset Circuitry

VDD

Crst

RST pin

Rrst

Reset input circuitry

Internal reset

Table 14 and Table 15 give some typical examples for three values of VDD rise times,
two values of oscillator start-up time and two pull-down resistor values.

Table 14. Minimum Reset Capacitor for a 15k Pull-down Resistor

oscrst/vddrst 1ms 10ms 100ms

5ms 2.7µF 4.7µF 47µF

4129L–CAN–08/05

20ms 10µF 15µF 47µF

Note: These values assume VDD starts from 0v to the nominal value. If the time between two

on/off sequences is too fast, the power-supply de coupling capacitors may not be fully
discharged, leading to a bad reset sequence.

21

A/T89C51CC01

Warm Reset To achieve a valid reset, the reset signal must be maintained for at least 2 machine

cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).

Watchdog Reset As detailed in Section “PCA Watchdog Timer”, page 127, the WDT generates a 96-clock

period pulse on the RST p in. In ord er to prop erly p ropa gate this pu lse to th e re st of the
application in case of external capacitor or power-supply supervisor circuit, a 1KΩ resis­tor must be added as shown Figure 8.

Figure 8. Reset Circuitry for WDT reset out usage

VDD

+

Reset Recommendation to Prevent Flash Corruption

VDD

VSS

1K

RST

RST

VSS

RST

R

An example of bad initialization situation may occur in an instance where the bit
ENBOOT in AUXR1 registe r is initiali zed from the har dware bit BLJB upon reset. Sinc e
this bit allows mapping of the bootloader in the code area, a reset failure can be critical.

To CPU core
and peripherals

To other
on-board

circuitry

If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet
due to a bad reset) the b it ENBOOT in SFRs may be set. If the value of Progra m
Counter is accidently in th e range of t he boot memory addresses the n a flash a ccess
(write or erase) may corrupt the Flash on-chip memory.

It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage (power
supply failure, power supply switched off).

Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode,

program execution halts. Idle mode freezes the cl ock to the CPU at known sta tes while
the peripherals continue to be clocked. The CPU status before entering Idle mode is
preserved, i.e., the program counter and program status word register retain their data
for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The
status of the Port pins during Idle mode is detailed in Table 14.

Entering Idle Mode To enter Idle mode, you must set the IDL bit in PCON regi ster (see Table 15 ). The

T89C51CC01 enters Idle mode upon execution of the instruction that sets IDL bit. The
instruction that sets IDL bit is the last instruction executed.

Note: If IDL bit and PD bit are set simultaneously, the T89C51CC01 enters Power-down mode.

Then it does not go in Idle mode when exiting Power-down mode.

Exiting Idle Mode There are two ways to exit Idle mode:

1. Generate an enabled interrupt.
– Hardware clears IDL bit in PCON register which restores the clock to the

CPU. Execution resumes with the interrupt service routine. Upon completion

22

4129L–CAN–08/05

A/T89C51CC01

of the interrupt service routine, program execution resumes with the
instruction immediately following the instruction that activated Idle mode.
The general-purpose flags (GF1 and GF0 in PCON register) may be used to
indicate whether an interrupt occurred during normal operation or during Idle
mode. When Idle mode is exited by an interrupt, the interrupt service routine
may examine GF1 and GF0.

2. Generate a reset.
– A logic high on the RST pin clears IDL bit in PCON register directly and

asynchronously. This restores the clock to the CPU. Program execution
momentarily resumes with the instruction immediately following the
instruction that activated the Idle mode and may continue for a number of
clock cycles before the internal reset algorithm takes control. Reset
initializes the T89C51CC01 and vectors the CPU to address C:0000h.

Note: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated Idle
mode should not write to a Port pin or to the external RAM.

2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle.

Power-down Mode The Power-down mode places the T89C51CC01 in a very low power state. Power-down

mode stops the oscillator and freezes all clocks at known states. The CPU status prior to
entering Power-down mode is preserved, i.e., the program cou nter, program status
word register retain their data for the duration of Power-down mode. In addition, the
SFRs and RAM content s a re pres erv ed. T h e s tatu s of the Po rt pins dur in g P ower -do w n
mode is detailed in Table 14.

Entering Power-down Mode To enter Power-d own mode , set PD bi t in PCO N regist er. The T 89C51CC0 1 enter s the

Power-down mo de upon ex ecution of t he inst ruction th at sets PD bi t. The inst ruction
that sets PD bit is the last instruction executed.

Exiting Power-down Mode If VDD was reduced during the Power-down mode, do not exit Power-down mode until

VDD is restored to the normal operating level.
There are two ways to exit the Power-down mode:

1. Generate an enabled external interrupt.
– The T89C51CC01 provides capability to exit from Power-down using INT0#,

INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTx# input,
execution resumes when the input is released (see Figure 9) while using
KINx input, execution resumes after counting 1024 clock ensuring the
oscillator is restarted properly (see Figure 8). Execution resumes with the
interrupt service routine. Upon completion of the interrupt service routine,
program execution resumes with the instruction immediately following the
instruction that activated Power-down mode.

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Note: 1. The external interrupt used to exit Power-down mode must be configured as level

sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,
the duration of the interrupt must be long enough to allow the oscillator to stabilize.
The execution will only resume when the interrupt is deasserted.

2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
RAM content.

23

A/T89C51CC01

Figure 9. Power-down Exit Waveform Using INT1:0#

INT1:0#

OSC

Power-down phase Oscillator restart phase Active phaseActive phase

2. Generate a reset.
– A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the T89C51CC01 and vectors
the CPU to address 0000h.

Notes: 1. D ur i ng the t im e th at ex e cuti o n re su me s, th e i nt er na l R AM ca n no t be ac ce ss ed ; ho w -

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.

2. Exit from power-down by res et r ede fine s all the SFRs, but does not affect the inte rna l
RAM content.

24

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Registers Table 15. PCON Register

PCON (S:87h) – Power configuration Register

76543210

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

A/T89C51CC01

Bit

Number

7SMOD1

6SMOD0

5-

4POF

3GF1

2GF0

1PD

Bit

Mnemonic Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.
Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Clear to recognize next reset type.
Set by hardware when V
software.

General-purpose flag 1

One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.

General-purpose flag 0

One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.

Power-down Mode bit

Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-down mode.
If IDL and PD are both set, PD takes precedence.

rises from 0 to its nominal voltage. Can also be set by

cc

Idle Mode bit

0IDL

Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.

Reset Value = 00X1 0000b

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25

A/T89C51CC01

Data Memory The T89C51CC01 provides data memory access in two different spaces:

1. The internal space mapped in three separate segments:

• the lower 128 Bytes RAM segment.

• the upper 128 Bytes RAM segment.

• the expanded 1024 Bytes RAM segment (XRAM).

2. The external space.
A fourth internal segment is available but dedicated to Special Function Registers,

SFRs, (addresses 80h to FFh) accessible by direct addressing mode.
Figure 11 shows the internal and external data memory spaces organization.

Figure 10. Internal Memory - RAM

FFh

128 Bytes

Internal RAM

indirect addressing
80h
7Fh

128 Bytes

Internal RAM

direct or indirect

00h

addressing

Upper

Lower

FFh

direct addressing

80h

Special

Function

Registers

Figure 11 . Internal and External Data Memory Organization XRAM-XRAM

FFFFh

64K Bytes

External XRAM

FFh or 3FFh

256 up to 1024 Bytes

Internal XRAM

EXTRAM = 0

EXTRAM = 1

26

00h

Internal

0000h

External

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A/T89C51CC01

Internal Space

Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 11) are acce ssible from address 00h to 7Fh

using direct or indirect address ing modes. T he lowest 32 Bytes are grouped in to 4
banks of 8 registers ( R0 to R7) . Tw o bits RS0 and R S1 in P SW regi st er (see Figur e 18)
select which bank is in use according to Table 16. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct address­ing, and can be used for context switching in interrupt service routines.

Table 16. Register Bank Selection

RS1 RS0 Description

0 0 Register bank 0 from 00h to 07h
0 1 Register bank 0 from 08h to 0Fh
1 0 Register bank 0 from 10h to 17h
1 1 Register bank 0 from 18h to 1Fh

The next 16 Bytes above the register banks form a block of bit-addressable memory
space. The C51 instruction set includes a wide selection of single-bit instructions, and
the 128 bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00h to 7Fh.

Figure 12. Lower 128 Bytes Internal RAM Organization

7Fh

30h

20h
18h
10h
08h
00h

2Fh

Bit-Addressable Space
(Bit Addresses 0-7Fh)

1Fh

17h

4 Banks of
8 Registers

0Fh

R0-R7

07h

Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect

addressing mode.

Expanded RAM The on-chip 1024 B y tes o f e xp and ed RAM ( XRAM ) ar e acc es sibl e f ro m add re ss 0000h

to 03FFh using indirect addressing mode through MOVX instructions. In this address
range, the bit EXTRAM in AUXR register is used to select the XRAM (default) or the
XRAM. As shown in Figure 11 when EXTRAM = 0, the XRAM is selected and when
EXTRAM = 1, the XRAM is selected.

The size of XRAM can be configured by XRS1-0 bit in AUXR register (default size is
1024 Bytes).

Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and
must then be initialized properly.

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27

A/T89C51CC01

External Space

Memory Interfac e The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (RD
Figure 13 shows the structure of the external address bus. P0 carries address A7:0

while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 17
describes the external memory interface signals.

Figure 13. External Data Memory Interface Structure

, WR, and ALE).

T89C51CC01

AD7:0

A15:8

Latch

P2

ALE

P0

WR

Table 17. External Data Memory Interface Signals

Signal

Name Type Description

A15:8 O

AD7:0 I/O

ALE O

RD

Address Lines

Upper address lines for the external bus.

Address/Data Lines

Multiplexed lower address lines and data for the external
memory.

Address Latch Enable

ALE signals indicates that valid address information are available
on lines AD7:0.

Read

O

Read signal output to external data memory.

A7:0

RAM

PERIPHERAL

A15:8

A7:0

D7:0
OERD

WR

Alternative

Function

P2.7:0

P0.7:0

-

P3.7

WR

Write

O

Write signal output to external memory.

External Bus Cycles This section describes the bus cycles the T89C51CC01 executes to read (see

Figure 14), and write data (see Figure 15) in the external data memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor­mation on X2 mode.

Slow peripherals can be acc essed b y stretc hing th e read and write cycles . This is done
using the M0 bit in AUXR reg ister. S etting t his bi t changes the widt h of the RD
signals from 3 to 15 CPU clock periods.

For simplicity, the accompanying figures depict the bus cycle waveforms in idealized
form and do not provide precise timing information. For bus cycle timing parameters
refer to the Section “AC Characteristics”.

28

P3.6

and WR

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Figure 14. External Data Read Waveforms

CPU Clock

ALE

1

RD

A/T89C51CC01

P0

P2

Notes: 1. RD signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instr uction, P2 outputs SFR content.

P2

DPL or Ri D7:0

DPH or P22

Figure 15. External Data Write Waveforms

CPU Clock

ALE

WR1

P0

P2

P2

DPL or Ri D7:0

DPH or P22

4129L–CAN–08/05

Notes: 1. WR signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instr uction, P2 outputs SFR content.

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A/T89C51CC01

Dual Data Pointer

Description The T89C51CC01 implements a second data pointer for speedi ng up code execution

and reducing code size in case of intensive usage of external memory accesses.
DPTR 0 and DPTR 1 ar e seen b y the CPU as DPTR an d are acc essed using th e SFR
addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1
register (see Figure 20) is used to select whether DPTR is the data pointer 0 or the data
pointer 1 (see Figure 16).

Figure 16. Dual Data Pointer Implementation

DPL0
DPL1

DPTR0

DPTR1

DPH0
DPH1

0
1

DPS

0
1

DPL

AUXR1.0

DPH

DPTR

Application Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare…) are well served by
using one data pointer as a “source” pointer and the other one as a “destination” pointer.
Hereafter is an example of block move implementation using the two pointers and coded
in assembler. The latest C compiler takes als o advantag e of this feature b y providin g
enhanced algorithm libraries.

The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the
DPS bit in the AUXR 1 reg ister. H owever , note that th e INC i nstruc tion do es no t direc tly
force the DPS bit to a particular state, but simply toggles it. In simple routines, such as
the block move exa mple, o nly the f act that DP S is tog gled i n the pr oper s equenc e mat­ters, not its actual value. In other words, the block move routine works the same whether
DPS is '0' or '1' on entry.

30

; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is
added

AUXR1EQU0A2h

move:movDPTR,#SOURCE ; address of SOURCE

incAUXR1 ; switch data pointers
movDPTR,#DEST ; address of DEST

mv_loop:incAUXR1; switch data pointers

movxA,@DPTR; get a byte from SOURCE
incDPTR; increment SOURCE address
incAUXR1; switch data pointers
movx@DPTR,A; write the byte to DEST
incDPTR; increment DEST address
jnzmv_loop; check for NULL terminator

end_move:

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