ATMEL T89C51RD2 User Manual
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T89C51RD2
0 to 40MHz Flash Programmable 8-bit Microcontroller
1. Description
ATMEL Wireless and Microcontrollers T89C51RD2 is
high performance CMOS Flash version of the 80C51
CMOS single chip 8-bit microcontroller. It contains a
64 Kbytes Flash memory block for program and for data.
The 64 Kbytes Flash memory can be programmed either
in parallel mode or in serial mode with the ISP capability
or with software. The programming voltage is internally
generated from the standard VCCpin.
The T89C51RD2 retains all features of the ATMEL
Wireless and Microcontrollers 80C52 with 256 bytes of
internal RAM, a 7-source 4-level interrupt controller and
three timer/counters.
In addition, the T89C51RD2 has a Programmable
Counter Array, an XRAM of 1024 bytes, an EEPROM
of 2048 bytes, a Hardware Watchdog Timer, a more
versatile serial channel that facilitates multiprocessor
communication (EUART) and a speed improvement
2. Features
• 80C52 Compatible
• 8051 pin and instruction compatible
• Four 8-bit I/O ports (or 6 in 64/68 pins packages)
• Three 16-bit timer/counters
• 256 bytes scratch pad RAM
• 7 Interrupt sources with 4 priority levels
• ISP (In System Programming) using standard V
power supply.
• Boot FLASH contains low level FLASH
programming routines and a default serial loader
• High-Speed Architecture
• 40 MHz in standard mode
• 20 MHz in X2 mode (6 clocks/machine cycle)
• 64K bytes on-chip Flash program / data Memory
• Byte and page (128 bytes) erase and write
• 10k write cycles
• On-chip 1024 bytes expanded RAM (XRAM)
• Software selectable size (0, 256, 512, 768, 1024
bytes)
• 768 bytes selected at reset for T87C51RD2
compatibility
CC
mechanism (X2 mode). Pinout is either the standard 40/
44 pins of the C52 or an extended version with 6 ports
in a 64/68 pins package.
The fully static design of the T89C51RD2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T89C51RD2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
The added features of the T89C51RD2 makes it more
powerful for applications that need pulse width
modulation, high speed I/O and counting capabilities
such as alarms, motor control, corded phones, smart card
readers.
• Dual Data Pointer
• Variable length MOVX for slow RAM/peripherals
• Improved X2 mode with independant selection for
CPU and each peripheral
• 2 k bytes EEPROM block for data storage
• 100K Write cycle
• Programmable Counter Array with:
• High Speed Output,
• Compare / Capture,
• Pulse Width Modulator,
• Watchdog Timer Capabilities
• Asynchronous port reset
• Full duplex Enhanced UART
• Low EMI (inhibit ALE)
• Hardware Watchdog Timer (One-time enabled with
Reset-Out)
• Power control modes:
• Idle Mode.
• Power-down mode.
Rev. F - 15 February, 2001 1
T89C51RD2
• Power supply:
- M version: Commercial and industrial
4.5V to 5.5V : 40MHz X1 Mode, 20MHz X2 Mode
3V to 5.5V : 33MHz X1 Mode, 16 MHz X2 Mode
- L version: Commercial and industrial
2.7V to 3.6V : 25MHz X1 Mode, 12MHz X2 Mode
• Temperature ranges: Commercial (0 to +70°C) and industrial (-40 to +85°C).
• Packages: PDIL40, PLCC44, VQFP44, PLCC68, VQFP64
Table 1. Memory Size
PDIL40
PLCC44
Flash (bytes) EEPROM (bytes) XRAM (bytes)
VQFP44 1.4
T89C51RD2 64k 2k 1024 1280 32
TOTAL RAM
(bytes)
I/O
PLCC68
Flash (bytes)
VQFP64 1.4
EEPROM
(bytes)
XRAM (bytes)
TOTAL RAM
(bytes)
T89C51RD2 64k 2k 1024 1280 48
3. Block Diagram
CC
Vss
IB-bus
V
Flash
64Kx8
Parallel I/O Ports & Ext. Bus
Port 1
Port 0
Port 2
XRAM
1Kx8
Port 3
EEPROM
2Kx8
PCA
ECI
(1)
PCA
Port 5Port 4
(2)(2)
(1)
Watch
Dog
T2EX
(1) (1)
Timer2
ALE/
XTAL1
XTAL2
PROG
PSEN
EA
RD
WR
(3)
(3)
CPU
RxD
(3)(3)
EUART
Timer 0
Timer 1
TxD
C51
CORE
RAM
256x8
INT
Ctrl
I/O
T2
(3) (3) (3) (3)
P1
P2
RESET
T0
T1
INT1
INT0
(1): Alternate function of Port 1
(2): Only available on high pin count packages
(3): Alternate function of Port 3
P0
P3
P5
P4
2 Rev. F - 15 February, 2001
T89C51RD2
4. SFR Mapping
The Special Function Registers (SFRs) of the T89C51RD2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3, P4, P5
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• Hardware Watchdog Timer register: WDTRST, WDTPRG
• Interrupt system registers: IE, IP, IPH
• Flash and EEPROM registers: FCON, EECON, EETIM
• Others: AUXR, AUXR1, CKCON
Table below shows all SFRs with their address and their reset value.
Bit
address-
able
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
B
0000 0000
P5
1111 1111CL0000 0000
ACC
0000 0000
CCON
00X0 0000
PSW
0000 0000
T2CON
0000 0000
P4
1111 1111
IP
X000 000
P3
1111 1111
IE
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111SP0000 0111
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
CH
0000 0000
CMOD
00XX X000
FCON
XXXX 0000
T2MOD
XXXX XX00
SADEN
0000 0000
SADDR
0000 0000
SBUF
XXXX XXXX
TMOD
0000 0000
CCAP0H
XXXX XXXX
CCAP0L
XXXX XXXX
CCAPM0
X000 0000
EECON
XXXX XX00
RCAP2L
0000 0000
AUXR1
XXXX 00X0
TL0
0000 0000
DPL
0000 0000
XXXX XXXX
XXXX XXXX
Non Bit addressable
CCAP1H
XXXX XXXX
CCAP1L
XXXX XXXX
CCAPM1
X000 0000
EETIM
0000 0000
RCAP2H
0000 0000
TL1
0000 0000
DPH
0000 0000
CCAPL2H
CCAPL2L
CCAPM2
X000 0000
TL2
0000 0000
TH0
0000 0000
CCAPL3H
XXXX XXXX
CCAPL3L
XXXX XXXX
CCAPM3
X000 0000
TH2
0000 0000
TH1
0000 0000
CCAPL4H
XXXX XXXX
CCAPL4L
XXXX XXXX
CCAPM4
X000 0000
WDTRST
XXXX XXXX
AUXR
XX0X 1000
P5
1111 1111
IPH
X000 0000
WDTPRG
XXXX X000
CKCON
X000 0000
PCON
00X1 0000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
Rev. F - 15 February, 2001 3
T89C51RD2
reserved
4 Rev. F - 15 February, 2001
5. Pin Configuration
T89C51RD2
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7CEX4
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
3
4
5
9
10
11
14
15
16
17
40
VCC
39
2
6
7
8
PDIL
12
13
18
19
20
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE/PROG
PSEN
P2.7/AD15
P2.6/AD14
P2.5/AD13
P2.4/AD12
P2.3/AD11
P2.2/AD10
P2.1/AD9
P2.0/AD8
P1.4/CEX1
P1.3/CEX0
P1.1/T2EX
P1.2/ECI
P1.0/T2
VSS1/NIC*
P1.5/CEX2
P1.6/CEX3
P1.7/CEx4
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
VCC
P0.0/AD0
RST
NIC*
P0.2/AD2
P0.3/AD3
P0.1/AD1
P1.4/CEX1
P1.3/CEX0
5 4 3 2 1 6
7
8
9
10
11
12
13
14
15
16
17
18 19 23222120 262524 27 28
P3.7/RD
P3.6/WR
P1.1/T2EX
P1.2/ECI
PLCC
XTAL2
XTAL1
P1.0/T2
VSS1/NIC*
VCC
44 43 42 41 40
NIC*
VSS
P2.0/A8
P0.0/AD0
P2.1/A9
P0.3/AD3
P0.2/AD2
P0.1/AD1
37
36
35
31
30
29
P2.2/A10
P2.3/A11
P2.4/A12
39
38
34
33
32
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
*NIC: No Internal Connection
RST
NIC*
P3.4/T0
P3.5/T1
43 42 41 40 3944
1
2
3
4
5
6
7
8
9
10
11
12 13 17161514 201918 21 22
XTAL2
P3.7/RD
P3.6/WR
38 37 36 35 34
VQFP44 1.4
VSS
NIC*
XTAL1
P2.0/A8
P2.1/A9
P2.2/A10
33
32
31
30
29
28
27
26
25
24
23
P2.3/A11
P2.4/A12
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
Rev. F - 15 February, 2001 5
T89C51RD2
G
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VSS1
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P5.5
P5.6
P5.7
VCC
P4.0
P4.1
P4.2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P0.4/AD4
89
27 28
P5.4
NIC
P0.5/AD5
P0.6/AD6
P5.3
29 30 313233
ALE/PRO
NIC
PSEN
NIC
EA
P0.7/AD7
23567 4 1 686766656463
PLCC 68
36 37 38 39 40 41
34 35
P2.7/A15
P2.6/A14
P5.2
62 61
42 43
P5.1
P2.5/A13
60
59
58
57
56
55
54
53
52
51
50
49
48
4647P4.4
45
44
P5.0
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
P2.0/A8
P4.6
NIC
VSS
P4.5
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P4.3
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
VSS1
P1.0/T2
P4.0
P1.1/T2EX
P1.2/EC1
P1.3/CEX0
P4.1
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NIC
RST
P0.4/AD4
P5.4
P5.3
NIC
NIC
NIC
NIC
P3.0/RxD
ALE/PROG
PSEN
EA
P0.5/AD5
NIC
P0.6/AD6
P0.7/AD7
58 5051525354555657596061626364 49
VQFP64 1.4
2618 19 20 21 22 23 24 25 27 28 29 30 31 3217
NIC
NIC
P5.2
P2.7/A15
P2.6/A14
P3.1/TxD
P3.2/INT0
P5.1
P5.0
P2.5/A13
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P3.4/T0
P3.3/INT1
P3.5/T1
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
P2.0/A8
P4.6
NIC
VSS
P4.5
XTAL1
XTAL2
P3.7/RD
P4.4
P3.6/WR
P4.3
P4.2
P1.6/CEX3
P1.5/CEX2
NIC
NIC
RST
P1.7/CEX4
NIC
P3.0/RxD
NIC
NIC
P3.1/TxD
P3.4/T0
P3.5/T1
P3.2/INT0
P3.3/INT1
NIC: No InternalConnection
6 Rev. F - 15 February, 2001
T89C51RD2
Mnemonic
V
SS
Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection.
V
CC
P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
P1.0-P1.7 1-8 2-9 40-44
P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
P3.0-P3.7 10-17 11,
Pin Number
DIL LCC VQFP 1.4
20 22 16 I Ground: 0V reference
40 44 38 I
1-3
1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
3 4 42 I ECI (P1.2): External Clock for the PCA
4 5 43 I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
5 6 44 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
6 7 1 I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2
7 8 2 I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3
8 9 3 I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4
5,
13-19
10 11 5 I RXD (P3.0): Serial input port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt 0
13 15 9 I INT1 (P3.3): External interrupt 1
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
7-13
Type
Power Supply: This is the power supply voltage for normal, idle and powerdown operation
written to them float and can be used as high impedance inputs. Port 0 must be
polarized to VCCor VSSin order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verification during
which P0 outputs the code bytes.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 1 pins that are externally pulled low will source
current because of the internal pull-ups. Port 1 also receives the low-order address
byte during memory programming and verification.
Alternate functions for TSC8x54/58 Port 1 include:
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming
and verification:
P2.0 to P2.5 for RB devices
P2.0 to P2.6 for RC devices
P2.0 to P2.7 for RD devices.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 3 pins that are externally pulled low will source
current because of the internal pull-ups. Port 3 also serves the special features
of the 80C51 family, as listed below.
Name and Function
Rev. F - 15 February, 2001 7
T89C51RD2
Mnemonic
Reset 9 10 4 I/O Reset: A high on this pin for two machine cycles while the oscillator is running,
ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte
PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When
EA 31 35 29 I External Access Enable: EA must be externally held low to enable the device
XTAL1 19 21 15 I
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier
Pin Number
DIL LCC VQFP 1.4
17 19 13 O RD (P3.7): External data memory read strobe
Type
resets the device. An internal diffused resistor to VSSpermits a power-on reset
using only an external capacitor to VCC. This pin is an output when the hardware
watchdog forces a system reset.
of the address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program
pulse input (PROG) during Flash programming. ALE can be disabled by setting
SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches.
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
to fetch code from external program memory locations 0000H to FFFFH (RD).
If security level 1 is programmed, EA will be internally latched on Reset.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
Name and Function
8 Rev. F - 15 February, 2001
T89C51RD2
5.1. Pin Description for 64/68 pin Packages
Port 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1 written to them are pulled
high by the internal pull ups and can be used as inputs.
As inputs, pins that are externally pulled low will source current because of the internal pull-ups.
Refer to the previous pin description for other pins.
PLCC68
VSS 51, 18 9/40
VCC 17 8
P0.0 15 6
P0.1 14 5
P0.2 12 3
P0.3 11 2
P0.4 9 64
P0.5 6 61
P0.6 5 60
P0.7 3 59
P1.0 19 10
P1.1 21 12
P1.2 22 13
P1.3 23 14
P1.4 25 16
P1.5 27 18
P1.6 28 19
P1.7 29 20
P2.0 54 43
P2.1 55 44
P2.2 56 45
P2.3 58 47
P2.4 59 48
P2.5 61 50
P2.6 64 53
P2.7 65 54
P3.0 34 25
P3.1 39 28
P3.2 40 29
P3.3 41 30
P3.4 42 31
P3.5 43 32
P3.6 45 34
P3.7 47 36
RESET 30 21
ALE/PROG 68 56
PSEN 67 55
EA 2 58
XTAL1 49 38
XTAL2 48 37
P4.0 20 11
P4.1 24 15
P4.2 26 17
P4.3 44 33
P4.4 46 35
P4.5 50 39
P4.6 53 42
P4.7 57 46
P5.0 60 49
P5.1 62 51
P5.2 63 52
P5.3 7 62
P5.4 8 63
P5.5 10 1
P5.6 13 4
P5.7 16 7
SQUARE
VQFP64 1.4
Rev. F - 15 February, 2001 9
T89C51RD2
6. Enhanced Features
In comparison to the original 80C52, the T89C51RD2 implements some new features, which are:
• The X2 option.
• The Dual Data Pointer.
• The extended RAM.
• The Programmable Counter Array (PCA).
• The Watchdog.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• The ALE disabling.
• Some enhanced features are also located in the UART and the timer 2.
6.1. X2 Feature and Clock Generation
The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following
advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.
6.1.1. Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.
XTAL1:2
XTAL1
F
XTAL
2
0
1
X2
CKCON reg
F
OSC
state machine: 6 clock cycles.
CPU control
Figure 1. Clock Generation Diagram
Rev. F - 15 February, 2001 10
T89C51RD2
XTAL1
XTAL1:2
X2 bit
CPU clock
X2 ModeSTD Mode STD Mode
Figure 2. Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 2.) allows to switch from 12 clock periods per instruction to 6
clock periods and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the
X2 feature (X2 mode).
The T0X2, T1X2, T2X2, SiX2, PcaX2 and WdX2 bits in the CKCON register (See Table 2.) allow to switch from
standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods
per peripheral clock cycle). These bits are active only in X2 mode.
More information about the X2 mode can be found in the application note ANM072 "How to take advantage of
the X2 features in TS80C51 microcontroller?"
Table 2. CKCON Register
CKCON - Clock Control Register (8Fh)
7 6 5 4 3 2 1 0
- WdX2 PcaX2 SiX2 T2X2 T1X2 T0X2 X2
Bit
Number
7 - Reserved
6 WdX2
5 PcaX2
4 SiX2
Bit
Mnemonic
Description
Watchdogclock(Thiscontrol bit is validated when the CPU clock X2 is set; when X2 is low,this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
3 T2X2
2 T1X2
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
11 Rev. F - 15 February, 2001
T89C51RD2
Bit
Number
1 T0X2
0 X2
Bit
Mnemonic
Reset Value = X000 0000b
Not bit addressable
Description
Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
CPU clock
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits.
Rev. F - 15 February, 2001 12
T89C51RD2
6.2. Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location.
There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 3.) that allows the program code to switch between them (Refer to Figure 3).
External Data Memory
07
DPS
AUXR1(A2H)
DPH(83H) DPL(82H)
DPTR1
DPTR0
AUXR1
Address 0A2H
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
b. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
Application
Figure 3. Use of Dual Pointer
Table 3. AUXR1: Auxiliary Register 1
- - - - GF3 0 - DPS
Reset value X X X X 0 0 X 0
Symbol
- Not implemented, reserved for future use.
DPS Data Pointer Selection.
GF3 This bit is a general purpose user flag
products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active
value will be 1. The value read from a reserved bit is indeterminate.
Function
DPS Operating Mode
0 DPTR0 Selected
1 DPTR1 Selected
a
b
.
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.
ASSEMBLY LANGUAGE
Rev. F - 15 February, 2001 13
T89C51RD2
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note
that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple
routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not
its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe
that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
14 Rev. F - 15 February, 2001
T89C51RD2
6.3. Expanded RAM (XRAM)
The T89C51RD2 provide additional Bytes of random access memory (RAM) space for increased data parameter
handling and high level language usage.
T89C51RD2 devices have expanded RAM in external data space; Maximum size and location are described in Table 4.
Table 4. Description of expanded RAM
Port XRAM size
T89C51RD2 1024 00h 3FFh
Start End
The T89C51RD2 has internal data memory that is mapped into four separate segments.
The four segments are:
• 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.
• 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
• 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only.
• 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit
cleared in the AUXR register. (See )
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed
by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they
have the same address, but are physically separate from SFR space.
Address
FF or 3FF
XRAM
00
FF
Upper
128 bytes
Internal
Ram
indirect accesses
80 80
Lower
128 bytes
Internal
Ram
direct or indirect
accesses
00
FF
Special
Function
Register
direct accesses
FFFF
External
Data
Memory
0100 or 0400
0000
Figure 4. Internal and External Data Memory Address
When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the
upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data ,accesses the SFR
at location 0A0H (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0,
# data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
Rev. F - 15 February, 2001 15
T89C51RD2
• The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions.
This part of memory which is physically located on-chip, logically occupies the first bytes of external data
memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table . This
can be useful if external peripherals are mapped at addresses already used by the internal XRAM.
• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any
of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6
(WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations
higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the
same way as in the standard 80C51, so with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done thanks to the use of DPTR.
• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri
will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output
higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a
sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes
the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read
or write signals on P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data
memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are extended from 6 to
30 clock periods. This is useful to access external slow peripherals.
Auxiliary Register AUXR
AUXR
Address 08EH
Reset value X X 0 X 1 0 0 0
Symbol Function
- Not implemented, reserved for future use.
AO Disable/Enable ALE
AO Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used)
1 ALE is active only during a MOVX or MOVC instruction
EXTRAM Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR
EXTRAM Operating Mode
0 Internal XRAM access using MOVX @ Ri/ @ DPTR
1 External data memory access
XRS0
XRS1
M0 Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0
XRAM size: Accessible size of the XRAM
XRS1:0 XRAM size
00 256 bytes
01 512 bytes
10 768 bytes (default)
11 1024 bytes
M0 Pulse length in clock period
0 6
1 30
- - M0 - XRS1 XRS0 EXTRAM AO
a
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In
that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
16 Rev. F - 15 February, 2001
T89C51RD2
6.4. Timer 2
The timer 2 in the T89C51RD2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in
cascade. It is controlled by T2CON register (See Table 5) and T2MOD register (See Table 6). Timer 2 operation
is similar to Timer 0 and Timer 1. C/T2 selects F
as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the
combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the ATMEL Wireless and Micrcontrollers
8-bit Microcontroller Hardware description.
Refer to the ATMEL Wireless and Micrcontrollers 8-bit Microcontroller Hardware description for the description
of Capture and Baud Rate Generator Modes.
In T89C51RD2 Timer 2 includes the following enhancements:
• Auto-reload mode with up or down counter
• Programmable clock-output
6.4.1. Auto-Reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit
in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the ATMEL Wireless and Micrcontrollers 8-bit
Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in
Figure 5. In this mode the T2EX pin controls the direction of count.
/12 (timer operation) or external pin T2 (counter operation)
OSC
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates
an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded
into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and
TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh
into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2
does not generate any interrupt. This bit can be used to provide 17-bit resolution.
Rev. F - 15 February, 2001 17
T89C51RD2
XTAL1
F
XTAL
F
:12
OSC
T2
(DOWN COUNTING RELOAD VALUE)
FFh
(8-bit)
TL2
(8-bit)
RCAP2L
(8-bit)
(UP COUNTING RELOAD VALUE)
0
1
C/T2
T2CONreg
FFh
(8-bit)
TH2
(8-bit)
RCAP2H
(8-bit)
Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1)
TR2
T2CONreg
T2EX:
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up counting
TOGGLE
TF2
T2CONreg
T2CONreg
EXF2
TIMER 2
INTERRUPT
6.4.2. Programmable Clock-Output
In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6) . The
input clock increments TL2 at frequency F
/2. The timer repeatedly counts to overflow from a loaded value.
OSC
At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer
2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system
oscillator frequency and the value in the RCAP2H and RCAP2L registers :
F
Clock OutFrequency–
--------------------------------------------------------------------------------------=
4 65536 RCAP2H– RCAP2L⁄()×
osc
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz
OSC
16)
/2
to 4 MHz (F
/4). The generated clock signal is brought out to T2 pin (P1.0).
OSC
(F
Timer 2 is programmed for the clock-out mode as follows:
• Set T2OE bit in T2MOD register.
• Clear C/T2 bit in T2CON register.
• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different
one depending on the application.
• To start the timer, set TR2 run control bit in T2CON register.
18 Rev. F - 15 February, 2001
T89C51RD2
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration,
the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and
RCAP2L registers.
T2EX
T2
XTAL1
:2
TR2
T2CON reg
Toggle
QD
EXEN2
T2CON reg
TL2
(8-bit)
RCAP2L
(8-bit)
T2OE
T2MOD reg
EXF2
T2CON reg
TH2
(8-bit)
RCAP2H
(8-bit)
OVEFLOW
TIMER 2
INTERRUPT
Figure 6. Clock-Out Mode C/T2=0
Rev. F - 15 February, 2001 19
T89C51RD2
Table 5. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7 6 5 4 3 2 1 0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number
7 TF2
6 EXF2
5 RCLK
4 TCLK
3 EXEN2
2 TR2
1 C/T2#
Bit
Mnemonic
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
clock the serial port.
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
OSC
).
0 CP/RL2#
Reset Value = 0000 0000b
Bit addressable
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
20 Rev. F - 15 February, 2001
T89C51RD2
Table 6. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7 6 5 4 3 2 1 0
- - - - - - T2OE DCEN
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 -
1 T2OE
0 DCEN
Bit
Mnemonic
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timer 2 Output Enable bit
Down Counter Enable bit
Reset Value = XXXX XX00b
Not bit addressable
Description
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.
Rev. F - 15 February, 2001 21
T89C51RD2
6.5. Programmable Counter Array PCA
The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its
advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/
counter which serves as the time base for an array of five compare/ capture modules. Its clock input can be
programmed to count any one of the following signals:
• Oscillator frequency ÷ 12 (÷ 6 in X2 mode)
• Oscillator frequency ÷ 4(÷ 2 in X2 mode)
• Timer 0 overflow
• External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
• rising and/or falling edge capture,
• software timer,
• high-speed output, or
• pulse width modulator.
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 31).
When the compare/capture modules are programmed in the capture mode, software timer, or high speed output
mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer
overflow share one interrupt vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below.
If the port is not used for the PCA, it can still be used for standard I/O.
PCA component External I/O Pin
16-bit Counter P1.2 / ECI
16-bit Module 0 P1.3 / CEX0
16-bit Module 1 P1.4 / CEX1
16-bit Module 2 P1.5 / CEX2
16-bit Module 3 P1.6 / CEX3
16-bit Module 4 P1.7 / CEX4
The PCA timer is a common time base for all five modules (See Figure 7). The timer count source is determined
from the CPS1 and CPS0 bits in the CMOD SFR (See Table 7) and can be programmed to run at:
• 1/12 the oscillator frequency. (Or 1/6 in X2 Mode)
• 1/4 the oscillator frequency. (Or 1/2 in X2 Mode)
• The Timer 0 overflow
• The input on the ECI pin (P1.2)
Rev. F - 15 February, 2001 22
T89C51RD2
Fosc /12
Fosc / 4
T0 OVF
P1.2
CH CL
16 bit up/down counter
overflow
To PCA
modules
It
CIDL CPS1 CPS0 ECF
WDTE
Idle
CF CR
Figure 7. PCA Timer/Counter
Table 7. CMOD: PCA Counter Mode Register
CMOD
Address 0D9H
Reset value 0 0 X X X 0 0 0
Symbol
CIDL
WDTE
- Not implemented, reserved for future use.
CPS1 PCA Count Pulse Select bit 1.
CPS0 PCA Count Pulse Select bit 0.
ECF
Function
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during
idle Mode. CIDL = 1 programs it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.
WDTE = 1 enables it.
CPS1 CPS0 Selected PCA input.
0 0 Internal clock f
0 1 Internal clock f
1 0 Timer 0 Overflow
1 1 External clock at ECI/P1.2 pin (max rate = f
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
CIDL WDTE - - - CPS1 CPS0 ECF
CCF4 CCF3 CCF2 CCF1 CCF0
a
b
/12 ( Or f
osc
/4 ( Or f
osc
/6 in X2 Mode).
osc
/2 in X2 Mode).
osc
osc
/8)
CMOD
0xD9
CCON
0xD8
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
b. f
= oscillator frequency
osc
The CMOD SFR includes three additional bits associated with the PCA (See Figure 7 and Table 7).
• The CIDL bit which allows the PCA to stop during idle mode.
• The WDTE bit which enables or disables the watchdog function on module 4.
23 Rev. F - 15 February, 2001
T89C51RD2
• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set
when the PCA timer overflows.
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module
(Refer to Table 8).
• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit.
• Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set. The CF bit can only be cleared by software.
• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by
hardware when either a match or a capture occurs. These flags also can only be cleared by software.
Table 8. CCON: PCA Counter Control Register
CCON
Address 0D8H
Reset value 0 0 X 0 0 0 0 0
Symbol
CF
CR
- Not implemented, reserved for future use.
CCF4
CCF3
CCF2
CCF1
CCF0
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags
an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but
can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared
by software to turn the PCA counter off.
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
a
The watchdog timer function is implemented in module 4 (See Figure 10).
The PCA interrupt system is shown in Figure 8
Rev. F - 15 February, 2001 24
T89C51RD2
CCON
0xD8
To Interrupt
priority decoder
PCA Timer/Counter
Module 0
Module 1
Module 2
Module 3
Module 4
ECF
CF CR
ECCFn
CCF4 CCF3 CCF2 CCF1 CCF0
CCAPMn.0CMOD.0
IE.6 IE.7
EC EA
Figure 8. PCA Interrupt System
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:
• 16-bit Capture, positive-edge triggered,
• 16-bit Capture, negative-edge triggered,
• 16-bit Capture, both positive and negative-edge triggered,
• 16-bit Software Timer,
• 16-bit High Speed Output,
• 8-bit Pulse Width Modulator.
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module
0, CCAPM1 for module 1, etc. (See Table 9). The registers contain the bits that control the mode that each module
will operate in.
• The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the
CCON SFR to generate an interrupt when a match or compare occurs in the associated module.
• PWM (CCAPMn.1) enables the pulse width modulation mode.
• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there
is a match between the PCA counter and the module's capture/compare register.
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there
is a match between the PCA counter and the module's capture/compare register.
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will
be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both
bits are set both edges will be enabled and a capture will occur for either transition.
• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
Table 10 shows the CCAPMn settings for the various PCA functions.
.
25 Rev. F - 15 February, 2001
Table 9. CCAPMn: PCA Modules Compare/Capture Control Registers
CCAPMn Address
n=0-4
T89C51RD2
CCAPM0=0DAH
CCAPM1=0DBH
CCAPM2=0DCH
CCAPM3=0DDH
CCAPM4=0DEH
- ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn
Reset value X 0 0 0 0 0 0 0
Symbol
- Not implemented, reserved for future use.
ECOMn Enable Comparator. ECOMn = 1 enables the comparator function.
CAPPn Capture Positive, CAPPn = 1 enables positive edge capture.
CAPNn Capture Negative, CAPNn = 1 enables negative edge capture.
MATn
TOGn
PWMn
ECCFn
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
Function
a
Match. When MATn = 1, a match of the PCA counter with this module's compare/capture
register causes the CCFn bit in CCON to be set, flagging an interrupt.
Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture
register causes the CEXn pin to toggle.
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width
modulated output.
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate
an interrupt.
Table 10. PCA Module Modes (CCAPMn Registers)
ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function
0 0 0 0 0 0 0 No Operation
X10000X
X01000X
X 1 1 0 0 0 X 16-bit capture by a transition on CEXn
100100X
1 0 0 1 1 0 X 16-bit High Speed Output
1 0 0 0 0 1 0 8-bit PWM
1 0 0 1 X 0 X Watchdog Timer (module 4 only)
16-bit capture by a positive-edge
trigger on CEXn
16-bit capture by a negative trigger on
CEXn
16-bit Software Timer / Compare
mode.
There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and
these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module
is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 11 & Table 12)
Rev. F - 15 February, 2001 26
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