ATMEL T5761-TGQ, T5760-TGQ, T5761-TG, T5760-TG Datasheet

UHF ASK/FSK Receiver

Description

The T5760/T5761 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with the Atmel Wireless & Microcontrollers’ PLL RF transmitter T5750. Its main applications are in

Features

D Fully integrated LC-VCO and PLL loop filter

T5761T5760

the areas of telemetering, security technology and keyless-entry systems. It can be used in the frequency receiving range of f0 = 868 to 870 MHz or f0 = 902 to 928 MHz for ASK or FSK data transmission. All the statements made below refer to 868.3 MHz and

915.0 MHz applications.

D Programmable digital noise suppresion D Very high sensitivity with power matched LNA D 30 dB image rejection D High system IIP3 (–16 dBm), system 1-dB compres-

sion point (–25 dBm)

D High large-signal capability at GSM band (blocking

–30 dBm @ + 20 MHz, IIP3 = –12 dBm @ + 20 MHz)

D 5 V to 20 V automotive compatible data interface D Data clock available for Manchester- and Bi-phase-

coded signals

System Block Diagram

UHF ASK/FSK

Remote control transmitter

T5750

XTO

PLL

VCO

Power

amp.

Antenna

D Receiving bandwidth BIF = 600 kHz for low cost

90-ppm crystals

D Low power consumption due to configurable polling

D Temperature range –40°C to 105°C

D ESD protection 2 kV HBM, 200 V MM

D Communication to mC possible via a single

bi-directional data line

D Low-cost solution due to high integration level with

minimum external circuitry requirements

UHF ASK/FSK

Remote control receiver

T5760/

1...5

Antenna

T5761

LNA VCO

Demod.

IF Amp

Control

PLL XTO

Figure 1. System block diagram

Ordering Information

Extended Type Number Package Remarks

T5760-TG SO20 Tube, for 868 MHz ISM band

T5760-TGQ SO20 Taped and reeled, for 868 MHz ISM band

T5761-TG SO20 Tube, for 915 MHz ISM band

T5761-TGQ SO20 Taped and reeled, for 915 MHz ISM band

Rev. A2, 19-Oct-00 1 (32)

Preliminary Information

T5760

T5761/

Pin Description

Pin Symbol Function

1 SENS Sensitivity-control resistor 2 IC_

ACTIVE

3 CDEM Lower cut-off frequency data fil-

4 AVCC Analog power supply 5 TEST 1 Test pin, during operation at GND 6 AGND Analog ground 7 n.c. Not connected, connect to GND 8 LNAREF High-frequency reference node

9 LNA_IN RF input 10 LNAGND DC ground LNA and mixer 11 TEST 2 Do not connect during operating 12 TEST 3 Test pin, during operation at GND 13 n.c. Not connected, connect to GND 14 XTAL Crystal oscillator XTAL connec-

15 DVCC Digital power supply 16 TEST 4 Test pin, during operation at

17 DATA_

CLK 18 DGND Digital ground 19 POLL-

ING/_ON

20 DATA Data output / configuration input

IC condition indicator Low = sleep mode High = active mode

ter

LNA and mixer

tion

DVCC Bit clock of data stream

Selects polling or rceiving mode Low: receiving mode High: polling mode

SENS

IC_ACTIVE

CDEM

AVCC

TEST 1

AGND

n.c.

LNAREF

LNA_IN

LNAGND

T5760/

T5761

Figure 2. Pinning SO20

DATA

POLLING /_ON

DGND

DATA_CLK

TEST 4

DVCC

XTAL

n.c.

TEST 3

TEST 2

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Rev. A2, 19-Oct-00

Preliminary Information

Block Diagram

T5761T5760

CDEM

SENS

AVCC AGND DGND

DVCC

FSK/ASK–

demodulator

and data filter

Rssi Limiter out

RSSI IF

Amp.

4. Order

f0=950 kHz/

1 MHz

LPF

fg=2.2MHz

IF Amp.

Poly–LPF fg=7MHz

Dem_out

Sensitivity–

reduction

Polling circuit

control logic

FE CLK

Standby logic

Loop–

filter

LC–VCO

interface

and

Data –

XTO

DATA

POLLING/_ON

DATA_CLK

IC_ACTIVE

XTAL

LNAREF

LNA_IN

LNA

LNAGND

Figure 3. Block diagram

RF Front End

The RF front end of the receiver is a low-IF heterodyne configuration that converts the input signal into a 950-kHz/ 1-MHz IF signal with an image rejection of typical 30dB. According to figure 3 the front end consists of an LNA (low noise amplifier), LO (local oscillator), I/Q mixer, polyphase lowpass filter and an IF amplifier.

The PLL generates the carrier frequency for the mixer via a full integrated synthesizer with integrated low noise LC-VCO (voltage controlled oscillator ) and PLL-loopfilter. The XTO ( crystal oscillator ) generates the reference frequency f erates two times the mixer drive frequency f signals for the mixer are generated with a divide by two circuit ( fLO = f

VCO

and feed into a phase frequency detector and compared

. The integrated LC-VCO gen-

XTO

/2 ). f

is divided by a factor of 256

VCO

. The I/Q

:256

with f

. The output of the phase frequency detector is

XTO

feed into an integrated loopfilter and thereby generates the control voltage for the VCO. If fLO is determined, f

can be calculated using the following formula:

XTO

= fLO / 128

XTO

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at Pin XTAL. According to figure 4, the crystal should be connected to GND with a series capacitor CL. The value of that capacitor is recommended by the crystal supplier. Due to a somewhat inductive impedance at steady state oscillation and some PCB parasitics a lower value of CL is normally necessary.

Rev. A2, 19-Oct-00 3 (32)

Preliminary Information

T5760

T5761/

The value of CL should be optimized for the individual board layout to achieve the exact value of f

XTO

(the best way is to use a crystal with known load resonance frequency to find the right value for this capacitor) and hereby of fLO. When designing the system in terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered.

If a crystal with $30 ppm adjustment tolerance at 25_C , $50ppm over T emperature –40_C to 105_C, $10 ppm of total aging and a CM ( motional capacitance ) of 7 fF is used, an additional XTO pulling of $30 ppm has to be added.

The resulting total LO tolerance of $120ppm agrees with the receiving bandwidth specification of the T5760/T5761 if the T5750 has also a total LO tolerance of $120 ppm.

n.c.

DVCC

XTAL

TEST 3

TEST 2

Figure 4. XTO peripherals

The nominal frequency fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula (low side injection):

fLO = fRF – f

To determine fLO , the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter is tuned by the crystal frequency f

. This means that there is a fixed relation

XTO

between fIF and fLO. fIF = fLO / 915 The relation is designed to achieve the nominal IF fre-

quency of fIF = 950 kHz for the 868.3 MHz version. For the 915 MHz version an IF frequency of fIF = 1.0 MHz results.

The RF input either from an antenna or from a RF generator must be transformed to the RF input Pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver T5760/T5761 exhibits its highest sensitivity if the LNA is power matched. This makes the matching to an SAW filter as well as to 50 W or an antenna more easy.

Figure 33 shows a typical input matching network for f

= 868.3 MHz to 50 W. Figure 34 illustrates an according input matching for 868.3 MHz to an SAW. The input matching network shown in Figure 33 is the reference network for the parameters given in the electrical characteristics.

Analog Signal Processing

IF Filter

The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 950 kHz for applications where fRF =

868.3 MHz and fIF =1.0 MHz for fRF = 915 MHz. The nominal bandwidth is 600 kHz.

Limiting RSSI Amplifier

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DR its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity.

In FSK mode the S/N ratio is not affected by the dynamic range of the RSSI amplifier, because only the hard limited signal from a high gain limiting amplifier is used by the demodulator.

The output voltage of the RSSI amplifier is internally compared to a threshold voltage V mined by the value of the external resistor R connected between Pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. By this means it is possible to operate the receiver at a lower sensitivity.

If R sensitivity. It is also possible to connect the Pin SENS directly to GND to get the maximum sensitivity.

If R lower sensitivity. The reduced sensitivity is defined by the value of R noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier.

Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in figure 33

= 60 dB. If the RSSI amplifier is operated within

RSSI

. V

Th_red

is connected to GND, the receiver switches to full

Sens

is connected to VS, the receiver operates at a

Sens

, the maximum sensitivity by the signal-to-

Sens

Th_red

Sens

is deter-

. R

Sens

4 (32)

Rev. A2, 19-Oct-00

Preliminary Information

T5761T5760

and exhibits the best possible sensitivity and at the same time power matching at RF_IN.

can be connected to VS or GND via a µC. The

Sens

receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at Pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to figure 5 is issued at Pin DATA to indicate that the receiver is still active (see also figure 32).

DATA

DATA_min

Figure 5. Steady L state limited DATA output pattern

DATA_L_max

FSK/ASK Demodulator and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the OPMODE register. Logic ‘L’ sets the demodulator to FSK, applying ‘H’ to ASK mode.

In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal to noise ratio is achieved. This circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10 dB the data signal can be detected properly, but better values are found for many modulation schemes of the competing transmitter.

The FSK demodulator is intended to be used for an FSK deviation of 10 kHz ≤ Df ≤ 100 kHz. In FSK mode the data signal can be detected if the S/N (ratio to suppress inband noise signals) exceeds about 2 dB. This value is valid for all modulation schemes of a disturber signal.

The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order highpass and a 2nd-order lowpass filter

The highpass filter cut-off frequency is defined by an external capacitor connected to Pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula:

fcu_DF +

In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if selfpolling is used. On the other hand CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics.

The cut-off frequency of the lowpass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to chapter ‘Configuration of the Receiver’). The BR_Range must be set in accordance to the used baud-rate.

The T5760/T5761 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V The sensitivity may be reduced by up to 2 dB in that condition.

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (t defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver.

2 p 30 kW CDEM

DC_min

= 33% and V

). These limits are

ee_sig

DC_max

= 66%.

Receiving Characteristics

The RF receiver T5760/T5761 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity and large signal capability. The receiving frequency response without a SAW front-end filter is illustrated in figures 6 and 7. This example relates to ASK mode. FSK mode exhibit similar behavior. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 3 dB must be considered, but the over all selectivity is much better.

When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the T5760/T5761. Lowcost crystals are specified to be within ±90 ppm over tolerance, temperature and aging. The XTO deviation of the T5760/T5761 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm worst case for a crystal with CM = 7 fF. If a crystal of ±90 ppm is used, the total deviation is ±120 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode.

Rev. A2, 19-Oct-00 5 (32)

Preliminary Information

T5760

T5761/

–10

–20

–30

dP ( dB )

–40

–50

–60

–4 –3 –2 –101234

df ( MHz )

Figure 6. Narrow band receiving frequency response

–20

–40

dP ( dB )

–60

–80

–100

–12 –9 –6 –3036912

df ( MHz )

Figure 7. Wide band receiving frequency response

Polling Circuit and Control Logic

The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected the receiver remains active and transfers the data to the connected µC. If there is no valid signal present the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected µC is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected µC. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc.

Regarding the number of connection wires to the mC, the receiver is very flexible. It can be either operated by a

single bi-directional line to save ports to the connected mC or it can be operated by up to five uni-directional ports.

Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry and the analog filtering is derived from one clock. This clock cycle T

is derived from the crystal oscillator (XTO) in

Clk

combination with a divide by 14 circuit. According to chapter ‘RF Front End’, the frequency of the crystal oscillator (f

) is defined by the RF input signal (f

XTO

RFin

) which also defines the operating frequency of the local oscillator (fLO). The basic clock cycle is T T

= 2.066 ms for f

Clk

= 1.961 ms for f

Clk

controls the following application-relevant parame-

Clk

= 915 MHz

= 14/ f

Clk

= 868.3 MHz and

XTO

giving

ters:

D Timing of the polling circuit including bit check D Timing of the analog and digital signal processing D Timing of the register programming D Frequency of the reset marker D IF filter center frequency (f

IF0

)

Most applications are dominated by two transmission frequencies: f f

= 868.3 MHz in Europe. In order to ease the

Transmit

usage of all T

= 915 MHz is mainly used in USA,

Transmit

-dependent parameters on this electrical

Clk

characteristics display three conditions for each parameter.

D Application USA

= 7.14063 MHz, T

XTO

= 1.961 µs)

Clk

D Application Europe

= 6.77617 MHz, T

XTO

= 2.066 µs)

Clk

D Other applications

The electrical characteristic is given as a function of T

Clk

The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range) which is defined in the OPMODE register. This clock cycle T

XClk

is defined

by the following formulas for further reference: BR_Range = BR_Range0: T

BR_Range1: T BR_Range2: T BR_Range3: T

XClk XClk XClk XClk

= 8 × T = 4 × T = 2 × T = 1 × T

Clk Clk Clk Clk

Polling Mode

According to figure 11, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode the signal processing circuitry is disabled for the time period T IS = I

. During the start-up period, T

Soff

processing circuits are enabled and settled. In the follow-

while consuming low current of

Sleep

Startup

, all signal

6 (32)

Rev. A2, 19-Oct-00

Preliminary Information

T5761T5760

ing bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period T

Bit-check

. This period varies check by check as it is a statistical process. An average value for T

Bit-check

Startup

is given in the electrical characteristics. During

and T

Bit-check

the current consumption is IS = I

Son

The condition of the receiver is indicated on Pin IC_ACTIVE. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as:

Spoll

During T

Soff

Sleep

and T

) I

Son

) T

Startup

the receiver is not sensitive to

Startup

) T

Bitcheck

)

a transmitter signal. To guarantee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. The required length of the preburst depends on the polling parameters T T (T and the number of bits (N

Startup

Start,µC

, T

Bit-check

). Thus, T

and the start-up time of a connected µC

Bit-check

depends on the actual bit rate

Bit-check

) to be tested.

Sleep

The following formula indicates how to calculate the preburst length.

Preburst

w T

Sleep

+ T

Startup

+ T

Bit-check

+ T

Start_mC

Sleep Mode

The length of period T

Sleep of the OPMODE register, the extension factor

is defined by the 5-bit word

Sleep

XSleep (according to table 9), and the basic clock cycle T

. It is calculated to be:

Clk

= Sleep X

Sleep

1024 T

Sleep

Clk

In US- and European applications, the maximum value of T

is about 60 ms if XSleep is set to 1. The time reso-

Sleep

lution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleep

Std

to’1’.

According to table 8, the highest register value of sleep sets the receiver into a permanent sleep condition. The receiver remains in that condition until another value for

Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line and may also be used for µC polling – via Pin POLLING/_ON, the receiver can be switched on and off.

Rev. A2, 19-Oct-00 7 (32)

Preliminary Information

T5760

T5761/

Sleep mode:

All circuits for signal processing are disabled. Only XTO and Polling logic is enabled. Output level on Pin IC_ACTIVE => low

= I

Soff

= Sleep × X

Sleep

× 1024 × T

Sleep

Start-up mode:

The signal processing circuits are enabled. After the start-up time (T

Startup

are in stable condition and ready to receive. Output level on Pin IC_ACTIVE => high

= I

Son

Startup

Bit-check mode:

The incomming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. Output level on Pin IC_ACTIVE => high

= I

Son

Bit-check

Bit check

OK ?

YES

Receiving mode:

The receiver is turned on permanently and passes the data stream to the connected mC. It can be set to Sleep mode through an OFF command via Pin DATA or POLLING/_ON. Output level on Pin IC_ACTIVE => high

= I

Son

OFF command

Clk

) all circuits

Sleep: 5-bit word defined by Sleep0 to

Sleep4 in OPMODE register

: Extension factor defined by

Sleep

XSleep

Std

according to table 9

: Basic clock cycle defined by f

Clk

and Pin MODE

: Is defined by the selected baud rate

Startup

range and T

. The baud-rate range

Clk

is defined by Baud0 and Baud1 in the OPMODE register.

Bit-check:

Depends on the result of the bit check

If the bit check is ok, T

Bit-check

depends on the number of bits to be checked (N

Bit-check

) and on the

utilized data rate.

If the bit check fails, the average time period for that check depends on the selected baud-rate range and

. The baud-rate range is

on T

Clk

defined by Baud0 and Baud1 in the OPMODE register.

XTO

( Number of checked Bits: 3 )

IC_ACTIVE

Bit check

Dem_out

Data_out (DATA)

Start–up mode

8 (32)

Start–up

Figure 8. Polling mode flow chart

Bit check ok

1/2 Bit

Bit–check

Bit–check mode

1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit

Figure 9. Timing diagram for complete successful bit check

Preliminary Information

Receiving mode

Rev. A2, 19-Oct-00

T5761T5760

Bit-Check Mode

In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable.

Configuring the Bit Check

Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N

Bit-check

in the OPMODE register. This implies 0, 6, 12 and 18 edge to edge checks respectively. If N

Bit-check

is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if N

Bit-check

is set to a lower value. In polling mode, the bit-check time is not dependent on N

Bit-check

. Figure 12 shows an example where 3 bits are tested successfully and the data signal is transferred to Pin DATA.

According to figure 13, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bit-check limit T and the upper bit-check limit T

Lim_max

continued. If tee is smaller than T T

Lim_max

, the bit check will be terminated and the re-

, the check will be

Lim_min

or t

Lim_min

exceeds

ceiver switches to sleep mode.

1/f

Sig

Dem_out

Figure 10. Valid time window for bit check

Lim_min

Lim_max

For best noise immunity it is recommended to use a low span between T

Lim_min

and T

Lim_max

. This is achieved us-

ing a fixed frequency at a 50% duty cycle for the transmitter preburst. A ‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good choice concerning that advice. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ± 25% regarding the expected edge-to-edge time tee. Us- ing pre-burst patterns that contain various edge-to-edge time periods, the bit-check limits must be programmed according to the required span.

The bit-check limits are determined by means of the formula below.

Lim_min

Lim_max

= Lim_min × T

XClk

= (Lim_max –1) × T

XClk

Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.

Using above formulas, Lim_min and Lim_max can be determined according to the required T and T T

Lim_max

DATA_L_min

. The time resolution defining T

XClk

is T

. The minimum edge-to-edge time t

XClk

, t

DATA_H_min

) is defined according to the

Lim_min

, T

Lim_max

Lim_min

and

chapter ‘Receiving Mode’. The lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63.

If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (N

Bit-check

) to prevent

switching to receiving mode due to noise. Figures 14, 15 and 16 illustrate the bit check for the bit-

check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during T

. The output of the ASK/ FSK

Startup

demodulator (Dem_out) is undefined during that period. When the bit check becomes active, the bit-check counter is clocked with the cycle T

XClk

Figure 14 shows how the bit check proceeds if the bitcheck counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In figure 15 the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in figure 16.

Rev. A2, 19-Oct-00 9 (32)

Preliminary Information

T5760

T5761/

( Lim_min = 14, Lim_max = 24 )

IC_ACTIVE

Bit check

Dem_out Bit–check–

counter

( Lim_min = 14, Lim_max = 24 )

IC_ACTIVE

Bit check

Dem_out

Bit–check– counter

Start–up

Start–up mode

Start–up

Start–up mode

3456 245

7 81 36789111213

XClk

Figure 11. Timing diagram during bit check

1/2 Bit

23456 2451 1 3 6789 111210

Bit–check

Bit–check mode

Bit check ok

1/2 Bit

Bit–check

Bit–check mode

Bit check failed ( CV_Lim < Lim_min )

17 18123456

15 16

Sleep mode

Sleep

Bit check ok

1/2 Bit 1/2 Bit

78910111213

14 15

1234

Figure 12. Timing diagram for failed bit check (condition: CV_Lim < Lim_min)

( Lim_min = 14, Lim_max = 24 )

IC_ACTIVE

Bit check

Dem_out Bit–check–

counter

Start–up

Start–up mode

23456 245

1 7 36789

Bit–check

Bit–check mode

Figure 13. Timing diagram for failed bit check (condition: CV_Lim >= Lim_max)

Duration of the Bit Check

If no transmitter signal is present during the bit check, the output of the ASK/ FSK demodulator delivers random signals. The bit check is a statistical process and T

Bit-check

varies for each check. Therefore, an average value for T

Bit-check

Clk

Bit-check

is given in the electrical characteristics. depends on the selected baud-rate range and on

. A higher baud-rate range causes a lower value for

resulting in a lower current consumption in pol-

ling mode. In the presence of a valid transmitter signal, T

dependent on the frequency of that signal, f count of the checked bits, N

Bit-check

. A higher value for

Bit-check

Sig

, and the

Bit check failed ( CV_Lim >= Lim_max )

1/2 Bit

11 1210

Bit-check

14 15 161718 19 21 22 23 24

thereby results in a longer period for T

Sleep

Sleep mode

Bit-check

requiring a higher value for the transmitter pre-burst T

Preburst

Receiving Mode

If the bit check was successful for all bits specified by N

Bit-check

, the receiver switches to receiving mode. According to figure 9, the internal data signal is switched to Pin DATA in that case and the data clock is available after the start bit has been detected (figure 20). A connected µC can be woken up by the negative edge at Pin DATA or by the data clock at Pin DATA_CLK. The receiver stays in that condition until it is switched back to polling mode explicitly.

10 (32)

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Preliminary Information

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