Atmel STK594 User Manual
STK594
..............................................................................................
User Guide
Table of Contents
Section 1
Introduction ...........................................................................................1-1
1.1 Features....................................................................................................1-2
Section 2
Using the STK594 Top Module.............................................................2-1
2.1 Preparing the STK500 for Use with the STK594.......................................2-1
2.1.1 Adjusting VTARGET for the AT94K Devices......................................2-1
2.1.2 Connecting the STK594 to the STK500 Starter Kit ............................2-1
2.2 PORT Connectors.....................................................................................2-2
2.2.1 PORT E ..............................................................................................2-2
2.3 Programming the AT94K Devices.............................................................2-3
2.4 JTAG Connector .......................................................................................2-3
2.5 TOSC Switch.............................................................................................2-4
2.6 Universal Asynchronous Receiver Transmitter (UART)............................2-4
2.6.1 Second RS-232C Port ........................................................................2-4
2.7 Two-Wire Serial Interface (TWSI) .............................................................2-5
2.7.1 Description of Configuration Memory Pins .........................................2-5
2.8 External Interrupts.....................................................................................2-5
2.9 Split Power Supply Support ......................................................................2-6
2.10 XTAL Switch .............................................................................................2-6
2.11 Reset Switches .........................................................................................2-6
Section 3
Installing System Designer ...................................................................3-1
3.1 System Requirements...............................................................................3-1
3.2 System Designer Installation.....................................................................3-2
3.3 Configuration Programming System (CPS) Installation ............................3-2
3.4 System Designer Licensing.......................................................................3-2
3.4.1 Requesting a System Designer License.............................................3-2
3.4.2 Configuring the System Designer License .........................................3-3
3.4.3 Testing the System Designer License ................................................3-3
3.4.4 Troubleshooting..................................................................................3-3
Section 4
Using System Designer ........................................................................4-1
4.1 Preparing the Example Files .....................................................................4-1
4.2 Description ................................................................................................4-1
4.3 Design Flow ..............................................................................................4-2
4.4 Creating a Project .....................................................................................4-2
4.5 Assembling the Microcontroller Source Code...........................................4-7
4.6 Synthesizing the FPGA Source File..........................................................4-7
4.7 AVR-FPGA Interface.................................................................................4-8
4.8 FPGA Place and Route.............................................................................4-9
4.9 Bitstream Generation ..............................................................................4-11
4.10 Programming and Design Execution ......................................................4-12
4.10.1 Hardware Setup................................................................................4-12
4.10.2 Software Setup.................................................................................4-13
4.11 Running the Design ................................................................................4-14
Section 5
Technical Specifications .......................................................................5-1
Section 6
Complete Schematics...........................................................................6-1
Section 1
Introduction
The STK594 board is a top module designed to add AT94K FPSLIC™support to the
STK500 development board. With this board the STK500 is extended to support all current AT94K FPSLIC devices in a single development environment.
The STK594 includes connectors, jumpers and hardware allowing full utilization of the
new features of the FPSLIC family, see Figure 1-1.
This user guide acts as a general getting started guide as well as a complete technical
reference for advanced users.
In addition to adding support for new devices, it also adds new support for peripherals
previously not supported by the STK500. An additional RS-232 port and a Two-Wire
Serial Interface are among the new features.
Figure 1-1.
STK594 Top Module for STK500
FPSLIC STK594 User Guide 1-1
Rev. 2819A–FPSLI–07/02
Introduction
1.1 Features
n
STK500 Compatible
n
AVR Studio®and System Designer™Compatible
n
Supports AT94KAL and AT94KAX Devices
n
Supports all Added Features in FPSLIC Devices
n
JTAG Connector for On-chip Debugging Using JTAG ICE
n
Additional RS-232C Port with Available RTS/CTS Handshake Lines
n
On-board 32 kHz Crystal for Easy RTC Implementations
1-2 FPSLIC STK594 User Guide
2819A–FPSLI–07/02
Section 2
Using the STK594 Top Module
2.1 Preparing the STK500 for Use with the STK594
2.1.1 Adjusting VTARGET for the AT94K Devices
2.1.2 Connecting the STK594 to the STK500 Starter Kit
Prior to using the STK594 with the STK500, it is necessary to make a few adjustments
to the STK500 Starter Kit to allow for proper operation of Atmel’s AT94K FPSLIC
devices.
According to the AT94K Series datasheet, the V
{V
|3.0<VCC= 3.6} Volts, with respect to ground. The STK594 board requires that
CC
theSTK500boardsuppliesaV
Prior to using the STK594 board, it is necessary to adjust the VTARGET to a value
between 3.0 and 3.6V. For more information on adjusting VTARGET from within AVR
Studio, consult section 5.3.5.1 of the STK500 User Guide, available on the Atmel web
site (www.atmel.com).
Note:
The STK594 should be connected to the STK500 expansion header 0 and 1. It is important that the top module is connected in the correct orientation as shown in Figure 2-1
on page 2. The EXPAND0 written on the STK594 top module should match the
EXPAND0 written beside the expansion header on the STK500 board.
It may be necessary to adjust the VDDvoltage, see “Split Power Supply Support”
on page 6 of this section for more information.
within the operating range for the AT94K devices.
CC
operating voltage is specified where
CC
FPSLIC STK594 User Guide 2-1
Rev. 2819A–FPSLI–07/02
Using the STK594 Top Module
Figure 2-1.
Connecting the STK594 to the STK500 Board
Note:
Note:
2.2 PORT Connectors
2.2.1 PORT E Figure 2-2 shows the pinout for the I/O port headers Port E.
Since the AT94K devices have additional ports not available on the STK500, these ports
are located on the STK594 board. The STK594 ports have the same pinout and functionality as the ports on the STK500 board. Since Port A to Port D are already present
on the STK500 board, they are not duplicated on the STK594.
Figure 2-2.
Connecting the STK594 with the wrong orientation may damage the boards.
Do not mount the STK594 at the same time an AVR is mounted on the STK500
board.
General I/O Ports
1 2
PE0
PE2
PE4
PE6
GND
PE1
PE3
PE5
PE7
VTG
PORT E
Note:
Port E is also present on the STK500, but only PE0 to PE2 (3 least significant
bits) are accessible. To access all Port E bits the connector on the STK594
must be used.
2-2 FPSLIC STK594 User Guide
2819A–FPSLI–07/02
Using the STK594 Top Module
2.3 Programming the AT94K Devices
The FPSLIC configuration process involves configuring the FPGA, the AVR®program
code and the FPSLIC data memory. This configuration requires a single bitstream that
configures the FPGA, the embedded AVR Program SRAM and the FPSLIC Data
SRAM. The combined bitstream is automatically generated by the Bitstream Generator,
a System Designer software utility.
After a reset and the internal clearing of the configuration data, the FPSLIC device selfinitiates configuration. The Master mode uses an internal oscillator to provide the Configuration Clock (CCLK) for clocking the external EEPROM (configurator), which
contains the configuration data. After auto-configuration is complete, re-configuration
can be initiated manually by the user, if needed.
Note:
Note:
For more details on programming procedures, refer to Section 4.10.
The AT94K devices also support Self-Programming. For more information on
this topic, refer to the “Code-Self Modify” application note available on the Atmel
web site.
The AT94K devices also support Cache Logic®Configuration. For more information on this topic, refer to the “Cache Logic Configuration” application note
available on the Atmel web site.
2.4 JTAG Connector The JTAG connector is intended for the AT94K devices that have a built-in JTAG inter-
face. The pinout of the JTAG connector is shown in Figure 2-3 and is compliant with the
pinout of the JTAG ICE available from Atmel. Connecting a JTAG ICE to this connector
allows On-chip Debugging of the AT94K devices.
More information about the JTAG ICE and On-chip Debugging can be found in the AVR
JTAG ICE user guide, available on the Atmel web site.
Figure 2-3.
JTAG Connector
1 2
TCK
TDO
TMS
VTG
TDI
GND
VTG
RST
N/C
GND
JTAG
Note:
Figure 2-4 shows how to connect the JTAG ICE probe on the STK594 board.
Figure 2-4.
To determine if your AT94K device supports JTAG Debug, examine the date
code. Any parts with a J after their date code support JTAG. Example, 4201J.
Connecting JTAG ICE to the STK594
FPSLIC STK594 User Guide 2-3
2819A–FPSLI–07/02
Using the STK594 Top Module
2.5 TOSC Switch The AT94K device provides dedicated I/O pins for TOSC1 and TOSC2, rather than
sharing with the general purpose I/O pins. The TOSC switch selects whether or not the
32 kHz crystal is connected to the pins of the device.
Figure 2-5 shows a simplified block schematic on how this is implemented.
2.6 Universal Asynchronous Receiver Transmitter (UART)
Figure 2-5.
TOSC Block Schematic
FPSLIC
32 kHz
TOSC2
TOSC1
TOSC Switch
Unlike traditional AVR microcontrollers, the AT94K device provides the option of having
separate I/O pins for the UARTs rather than sharing with the general purpose I/O pins.
Figure 2-6 shows the pinout of a header for the dedicated UART pins.
Figure 2-6.
UART Header
1 2
RX0
RX1
TX0
TX1
UART
2.6.1 Second RS-232C Port
The AT94K device has an additional UART. The RS-232 port on the STK594 board has
in addition to the RXD and TXD lines support for RTS and CTS flow control. Figure 2-7
shows a simplified block schematic on how this is implemented.
Note:
The UART in AT94K devices does not support hardware RTS or CTS control. If
such functionality is needed, it must be implemented in software.
Figure 2-7.
UART Block Schematic
4
6
2
3
7
RS232 SPARE2
8
5
RS-232/Logic Level
Converter
RxD TxD
CTS RTS
This UART can also be used from devices placed in the STK500 board. Simply connect
the appropriate port pins to RXD and TXD on the STK594 board.
Note:
If no software RTS/CTS flow control is implemented, a jumper shorting RTS and
CTS will ensure correct communication with an external application that uses
such flow control.
2-4 FPSLIC STK594 User Guide
2819A–FPSLI–07/02
Using the STK594 Top Module
2.7 Two-Wire Serial Interface (TWSI)
2.7.1 Description of Configuration Memory Pins
The AT94K device includes dedicated I/O pins for the TWSI rather than sharing with the
general purpose I/O pins.
Figure 2-8 shows the pinout of a header for the dedicated TWSI pins.
Figure 2-8.
TWSI Header
1 2
SCLSDA
TWSI
An AT17LV010-10CC 1-Mbit Configuration Memory is included on the STK594 for supplying the AT94K FPSLIC device with its configuration data, as well as for non-volatile
data storage. The configurator is a high-density EEPROM with a TWSI interface. A
detailed datasheet of the Configuration Memory can be obtained from the Atmel web
site.
The configurator can be connected to the I/O pins of the embedded AVR microcontroller. The 4-pin header marked
the configurator to the I/O pins of the target AVR microcontroller. Two-wire cables are
included with the STK500 for connecting the configurator to the I/O pins.
Figure 2-9 shows the pinout of a header for the Configuration Memory pins.
Figure 2-9.
Configuration Memory Header
CONFIG
can be used for connecting the TWSI interface of
2.8 External Interrupts
1 2
cSDA
cSER_EN
cSCL
N/C
CONFIG
Unlike traditional AVR microcontrollers, the AT94K device provides the option of having
separate I/O pins for the External Interrupts rather than sharing with the general purpose
I/O pins.
Figure 2-10 shows the pinout of a header for the dedicated External Interrupt pins.
Figure 2-10.
External Interrupt Header
1 2
INTP0
INTP2
INTP1
INTP3
EXT
FPSLIC STK594 User Guide 2-5
2819A–FPSLI–07/02
Using the STK594 Top Module
2.9 Split Power Supply Support
The AT94K FPSLIC devices exist in two different variations, the AL and AX. The AL
variation is a 3.3V device manufactured on a 0.35µ process, while the AX variation has
a 1.8V core manufactured on a 0.18µ process. The primary difference between the two
variations, is that the AX device requires a split power supply, as the I/Os are still powered from a 3.3V supply, while the core operates at 1.8V.
The STK594 supports both AT94K variations. If an AX variant is being used it is necessary to supply the proper core to the AT94K device. Figure 2-11 shows how to set the
jumper to select the core voltage.
Figure 2-11.
AT94K Core Voltage Selector
AT94KAL
AL
VDD
AX
AT94KAX
AL
VDD
AX
2.10 XTAL Switch An oscillator is included on the STK594 for supplying an additional clock to the AT94K
FPSLIC device. The XTAL switch selects if the oscillator is connected to the XTAL1 pin,
or whether the clock is provided by the STK500.
Figure 2-12 shows a simplified block schematic on how this is implemented.
Figure 2-12.
XTAL Block Schematic
FPSLIC
XTAL1
XTAL2
XT1
XT2
OSC
2.11 Reset Switches The reset switch found on the STK594 is connected to the AT94K’s RESET pin. When
pressed, the AT94K device will reset and initiate a configuration download from the configuration memory.
The reset switch found on the STK500 is connected to the AVRRESET
the embedded AVR microcontroller resets and begins execution at location $0000.
. When pressed,
2-6 FPSLIC STK594 User Guide
2819A–FPSLI–07/02
Section 3
Installing System Designer
System Designer is the ideal software platform for all AT94K FPSLIC development. It
includes an Editor, an Assembler and a Debugger as its development tools for the
embedded AVR development, and also includes a Simulator, Synthesizer and a Place
and Route tool for FPGA development. System Designer also includes a Co-Verification
suite powered by Mentor Graphics
and AVR design concurrently.
®
, allowing for step-by-step simulation of the FPGA
3.1 System Requirements
For a single-user system, System Designer requires a personal computer equipped as
follows:
n
CD-ROM Drive
n
250-Mbyte Minimum Hard Drive
n
128-Mbyte RAM
n
Parallel Interface Port
n
Windows®95/98/2000/Me, or WindowsNT®4.0
n
Network Interface Card or Security Dongle
The software security dongle is used to generate a unique HOSTID for systems without
a network interface card. The security dongle is connected to the PC through the
parallel port interface. It is possible to configure a floating network license through the
security dongle. The security dongle allows users to use the software dongle on different
machines by removing and placing the dongle on other machines.
FPSLIC STK594 User Guide 3-1
Rev. 2819A–FP SLI– 07/02
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