Atmel SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321 Datasheet

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SAM7S512 SAM7S256 SAM7S128 SAM7S64

Features

AT91SAM

ARM-based Flash MCU

SAM7S321 SAM7S32 SAM7S161 SAM7S16

• Incorporates the ARM7TDMI

– High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support

• Internal High-speed Flash

– 512 Kbytes (SAM7S512) Organized in Two Contiguous Banks of 1024 P ages of 256

Bytes (Dual Plane) – 256 Kbytes (SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane) – 64 Kbytes (SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane) – 32 Kbytes (SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane) – 16 Kbytes (SAM7S161/16) Organized in 256 Pages of 64 Bytes (Single Plane) – Single Cycle Access at Up to 30 MHz in Worst Case Conditions – Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed – Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms – 10,000 Write Cycles, 10-year Data Retention Capability , Sector Loc k Capabi lities, Flash

Security Bit – Fast Flash Programming Interface for High Volume Production

• Internal High-speed SRAM, Single-cycle Access at Maximum Speed

– 64 Kbytes (SAM7S512/256) – 32 Kbytes (SAM7S128) – 16 Kbytes (SAM7S64) – 8 Kbytes (SAM7S321/32) – 4 Kbytes (SAM7S161/16)

• Memory Controller (MC)

– Embedded Flash Controller, Abort Status and Misalignment Detection

• Reset Controller (RSTC)

– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector – Provides External Reset Signal Shaping and Reset Source Status

• Clock Generator (CKGR)

– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL

• Power Management Controller (PMC)

– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500

Hz) and Idle Mode – Three Programmable External Clock Signals

• Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Tw o (SAM7S512/256/128/64/321/161) or One (SAM7S32/16) External Interrupt Source(s)

and One Fast Interrupt Source, Spurious Interrupt Prot ected

ARM® Thumb® Processor

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• Debug Unit (DBGU)

– 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention – Mode for General Purpose 2-wire UART Serial Communication

• Periodic Interval Timer (PIT)

– 20-bit Programmable Counter plus 12-bit Interval Counter

• Windowed Watchdog (WDT)

– 12-bit key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

• Real-time Timer (RTT)

– 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator

• One Parallel Input/Output Controller (PIOA)

– Thirty-two (SAM7S512/256/128/64/321/161) or twenty-one (SAM7S32/16) Programmable I/O Lines Multiplexed with up to

Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up resistor and Synchronous Output

• Eleven (SAM7S512/256/128/64/321/161) or Nine (SAM7S32/16) Peripheral DMA Controller (PDC) Channels

• One USB 2.0 Full Speed (12 Mbits per Second) Device Port (Except for the SAM7S32/16).

– On-chip Transceiver, 328-byte Configurable Integrated FIFOs

• One Synchronous Serial Controller (SSC)

– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

• Two (SAM7S512/256/128/64/321/161) or One (SAM7S32/16) Universal Synchronous/Asynchronous Receiver Transmitters

(USART)

– Individual Baud Rate Generator, IrDA – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support – Full Modem Line Support on USART1 (SAM7S512/256/128/64/321/161)

Infrared Modulation/Demodulation

• One Master/Slave Serial Peripheral Interface (SPI)

– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects

• One Three-channel 16-bit Timer/Counter (TC)

– Three External Clock Input and Two Multi-purpose I/O Pins per Channel (SAM7S512/256/128/64/321/161) – One External Clock Input and Two Multi-purpose I/O Pins for the first Two Channels Only (SAM7S32/16) – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

• One Four-channel 16-bit PWM Controller (PWMC)

• One Two-wire Interface (TWI)

– Master Mode Support Only, All Two-wire Atmel EEPROMs and I

(SAM7S512/256/128/64/321/32) – Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs and I

(SAM7S161/16)

C Compatible Devices Supported

• One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os

• SAM-BA

• IEEE

™

Boot Assistant – Default Boot program – Interface with SAM-BA Graphic User Interface

1149.1 JTAG Boundary Scan on All Digital Pins

• 5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each (SAM7S161/16 I/Os Not 5V-tolerant)

• Power Supplies

– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components – 3.3V or 1.8V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brow n-out Detector

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• Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions

• Available in 64-lead LQFP Green or 64-pad QFN Green Package (SAM7S512/256/128/64/321/161) and 48-lead LQFP Green or

48-pad QFN Green Package (SAM7S32/16)

1. Description

Atmel’s SAM7S is a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a high-speed Flash and an SRAM, a large set of peripherals, including a USB 2.0 device (except for the SAM7S32 and SAM7S16), and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory.

The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality.

The SAM7S Series system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.

The SAM7S Series are general-purpose microcontrollers. Their integrated USB Device port makes them ideal devices for peripheral applications requiring connectivity to a PC or cellular phone. Their aggressive price point and high level of integration pushes their scope of use far into the cost-sensitive, high-volume consumer market.

1.1 Configuration Summary of the SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321, SAM7S32, SAM7S161 and SAM7S16

The SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321, SAM7S32, SAM7S161 and SAM7S16 differ in memory size, peripheral set and package. Table 1-1 summarizes the configuration of the six devices.

Except for the SAM7S32/16, all other SAM7S devices are package and pinout compatible.

Table 1-1. Configuration Summary

USB

Flash

Device Flash TWI

SAM7S512 512 Kbytes Master dual plane 64 Kbytes 1 2

SAM7S256 256 Kbytes Master single plane 64 Kbytes 1 2

SAM7S128 128 Kbytes Master single plane 32 Kbytes 1 2

SAM7S64 64 Kbytes Master single plane 16 Kbytes 1 2

SAM7S321 32 Kbytes Master single plane 8 Kbytes 1 2

SAM7S32 32 Kbytes Master single plane 8 Kbytes

SAM7S161 16 Kbytes

SAM7S16 16 Kbytes

Master/ Slave

Organization SRAM

single plane 4 Kbytes 1 2

single plane 4 Kbytes

Device Port USART

not present

Notes: 1. Fractional Baud Rate.

2. Full modem line support on USART1.

3. Only two TC channels are accessible through the PIO.

11 9 3

External Interrupt Source

(1) (2)

2113Yes32

(1) (2)

2113Yes32

(1) (2)

2113Yes32

(2)

2113Yes32

(2)

2113Yes32

(2)

2 11 3 No 32 LQFP

PDC ChannelsTCChannels

(3)

I/O 5V Tolerant

Yes 21

No 21

I/O Lines Package

LQFP/ QFN 64

LQFP/ QFN 48

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TDI TDO TMS TCK

NRST

FIQ

IRQ0-IRQ1

PCK0-PCK2

PMC

Peripheral Bridge

Peripheral Data

Controller

AIC

PLL

RCOSC

SRAM

64/32/16/8/4 Kbytes

ARM7TDMI

Processor

ICE

JTAG

SCAN

JTAGSEL

PIOA

USART0

SSC

Timer Counter

RXD0

TXD0

SCK0

RTS0 CTS0

NPCS0 NPCS1 NPCS2 NPCS3

MISO MOSI

SPCK

Flash

512/256/

128/64/32/16 Kbytes

Reset

Controller

DRXD DTXD

TF TK TD RD RK RF TCLK0 TCLK1 TCLK2 TIOA0 TIOB0

TIOA1 TIOB1

TIOA2 TIOB2

Memory Controller

Abort

Status

Address Decoder

Misalignment

Detection

PIO

APB

POR

Embedded

Flash

Controller

AD0 AD1 AD2 AD3

ADTRG

PLLRC

11 Channels

PDC

USART1

RXD1

TXD1

SCK1

RTS1

CTS1 DCD1 DSR1 DTR1

RI1

PDC

PDC PDC

PDC

SPI

PDC

ADC

ADVREF

PDC

TC0

TC1 TC2

TWD TWCK

TWI

OSC

XIN

XOUT

VDDIN

PWMC

PWM0 PWM1 PWM2 PWM3

1.8 V

Voltage

Regulator

USB Device

FIFO

DDM DDP

Transceiver

GND VDDOUT

BOD

VDDCORE

AD4 AD5 AD6 AD7

VDDFLASH

Fast Flash

Programming

Interface

ERASE

PIO

PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN2

PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3

VDDIO

TST

DBGU

PDC PDC

PIO

PIT

WDT

RTT

System Controller

VDDCORE

SAM-BA

ROM

2. Block Diagram

Figure 2-1. SAM7S512/256/128/64/321/161 Block Diagram

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ROM

TDI TDO TMS

TCK

NRST

FIQ

IRQ0

PCK0-PCK2

JTAGSEL

RXD0

TXD0

SCK0

RTS0

CTS0 NPCS0 NPCS1 NPCS2 NPCS3

MISO

MOSI

SPCK

DRXD

DTXD

TF TK TD RD RK RF TCLK0

TIOA0 TIOB0

TIOA1 TIOB1

AD0 AD1 AD2 AD3

ADTRG

PLLRC

9 Channels

ADVREF

TWD TWCK

XIN

XOUT

VDDIN

PWM0 PWM1 PWM2 PWM3

GND VDDOUT

VDDCORE

AD4 AD5 AD6 AD7

VDDFLASH

ERASE

PGMD0-PGMD7 PGMNCMD PGMEN0-PGMEN2

PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3

VDDIO

TST

VDDCORE

SRAM

8/4 Kbytes

ARM7TDMI

Processor

Flash

32/16 Kbytes

APB

SAM-BA

PMC

Peripheral Bridge

Peripheral DMA

Controller

AIC

PLL

RCOSC

ICE

JTAG

SCAN

PIOA

USART0

SSC

Timer Counter

Reset

Controller

Memory Controller

Abort

Status

Address Decoder

Misalignment

Detection

PIO

POR

Embedded

Flash

Controller

PDC

PDC PDC

PDC

SPI

PDC

ADC

PDC

TC0

TC1

TC2

TWI

OSC

PWMC

1.8 V

Voltage

Regulator

BOD

Fast Flash

Programming

Interface

PIO

DBGU

PDC

PIO

PIT

WDT

RTT

System Controller

Figure 2-2. SAM7S32/16 Block Diagram

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3. Signal Description

Table 3-1. Signal Description List

Active

Signal Name Function Type

Power

VDDIN

Voltage and ADC Regulator Power Supply Input

Power 3.0 to 3.6V

VDDOUT Voltage Regulator Output Power 1.85V nominal VDDFLASH Flash Power Supply Power 3.0V to 3.6V VDDIO I/O Lines Power Supply Power 3.0V to 3.6V or 1.65V to 1.95V VDDCORE Core Power Supply Power 1.65V to 1.95V VDDPLL PLL Power 1.65V to 1.95V GND Ground Ground

Clocks, Oscillators and PLLs

XIN Main Oscillator Input Input XOUT Main Oscillator Output Output PLLRC PLL Filter Input PCK0 - PCK2 Programmable Clock Output Output

ICE and JTAG

TCK Test Clock Input No pull-up resistor TDI Test Data In Input No pull-up resistor TDO Test Data Out Output TMS Test Mode Select Input No pull-up resistor JTAGSEL JTAG Selection Input Pull-down resistor

Flash Memory

ERASE

Flash and NVM Configuration Bits Erase Command

Input High Pull-down resistor

Reset/Test

NRST Microcontroller Reset I/O Low Open-drain with pull-Up resistor TST Test Mode Select Input High Pull-down resistor

Debug Unit

DRXD Debug Receive Data Input DTXD Debug Transmit Data Output

AIC

IRQ0 - IRQ1 External Interrupt Inputs Input IRQ1 not present on SAM7S32/16 FIQ Fast Interrupt Input Input

PIO

PA0 - PA31 Parallel IO Controller A I/O

Level Comments

(1)

Pulled-up input at reset PA0 - PA20 only on SAM7S32/16

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Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

Level Comments

USB Device Port

DDM USB Device Port Data - Analog not present on SAM7S32/16 DDP USB Device Port Data + Analog not present on SAM7S32/16

USART

SCK0 - SCK1 Serial Clock I/O SCK1 not present on SAM7S32/16 TXD0 - TXD1 Transmit Data I/O TXD1 not present on SAM7S32/16 RXD0 - RXD1 Receive Data Input RXD1 not present on SAM7S32/16 RTS0 - RTS1 Request To Send Output RTS1 not present on SAM7S32/16 CTS0 - CTS1 Clear To Send Input CTS1 not present on SAM7S32/16 DCD1 Data Carrier Detect Input not present on SAM7S32/16 DTR1 Data Terminal Ready Output not present on SAM7S32/16 DSR1 Data Set Ready Input not present on SAM7S32/16 RI1 Ring Indicator Input not present on SAM7S32/16

Synchronous Serial Controller

TD Transmit Data Output RD Receive Data Input TK Transmit Clock I/O RK Receive Clock I/O TF Transmit Frame Sync I/O RF Receive Frame Sync I/O

Timer/Counter

TCLK0 - TCLK2 External Clock Inputs Input

TCLK1 and TCLK2 not present on

SAM7S32/16 TIOA0 - TIOA2 I/O Line A I/O TIOA2 not present on SAM7S32/16 TIOB0 - TIOB2 I/O Line B I/O TIOB2 not present on SAM7S32/16

PWM Controller

PWM0 - PWM3 PWM Channels Output

SPI

MISO Master In Slave Out I/O MOSI Master Out Slave In I/O SPCK SPI Serial Clock I/O NPCS0 SPI Peripheral Chip Select 0 I/O Low NPCS1-NPCS3 SPI Peripheral Chip Select 1 to 3 Output Low

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Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

Level Comments

Two-Wire Interface

TWD Two-wire Serial Data I/O TWCK Two-wire Serial Clock I/O

Analog-to-Digital Converter

AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset AD4-AD7 Analog Inputs Analog Analog Inputs ADTRG ADC Trigger Input ADVREF ADC Reference Analog

Fast Flash Programming Interface

PGMEN0-PGMEN2 Programming Enabling Input PGMM0-PGMM3 Programming Mode Input PGMD0-PGMD15 Programming Data I/O PGMD0-PGMD7 only on SAM7S32/16 PGMRDY Programming Ready Output High PGMNVALID Data Direction Output Low PGMNOE Programming Read Input Low PGMCK Programming Clock Input PGMNCMD Programming Command Input Low

Note: 1. Refer to Section 6. “I/O Lines Considerations” on page 14.

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4. Package and Pinout

116

3348

161

The SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package. The SAM7S161 is available in a 64-Lead LQFP package. The SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package.

4.1 64-lead LQFP and 64-pad QFN Package Outlines

Figure 4-1 and Figure 4-2 show the orientation of the 64-lead LQFP and the 64-pad QFN package. A detailed

mechanical description is given in the section Mechanical Characteristics of the full datasheet.

Figure 4-1. 64-lead LQFP Package (Top View)

Figure 4-2. 64-pad QFN Package (Top View)

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4.2 64-lead LQFP and 64-pad QFN Pinout

Table 4-1. SAM7S512/256/128/64/321/161 Pinout

1 ADVREF 17 GND 33 TDI 49 TDO 2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL 3 AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS 4 AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31 5 AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK 6 AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE 7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE 8 VDDOUT 24 VDDCORE 40 TST 56 DDM

9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 DDP 10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO 11 PA21/PGMD9 27 PA12/PGMD0 43 PA3 59 VDDFLASH 12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND 13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT 14 PA22/PGMD10 30 PA9/PGMM1 46 GND 62 XIN/PGMCK 15 PA23/PGMD11 31 PA8/PGMM0 47 PA1/PGMEN1 63 PLLRC 16 PA20/PGMD8/AD3 32 PA7/PGMNVALID 48 PA0/PGMEN0 64 VDDPLL

Note: 1. The bottom pad of the QFN package must be connected to ground.

(1)

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4.3 48-lead LQFP and 48-pad QFN Package Outlines

112

2536

121

Figure 4-3 and Figure 4-4 show the orientation of the 48-lead LQFP and the 48-pad QFN package. A detailed

mechanical description is given in the section Mechanical Characteristics of the full datasheet.

Figure 4-3. 48-lead LQFP Package (Top View)

Figure 4-4. 48-pad QFN Package (Top View)

4.4 48-lead LQFP and 48-pad QFN Pinout

Table 4-2. SAM7S32/16 Pinout

1 ADVREF 13 VDDIO 25 TDI 37 TDO 2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL 3 AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS 4 AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK 5 AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE 6 AD7 18 VDDCORE 30 TST 42 ERASE 7 VDDIN 19 PA12/PGMD0 31 PA3 43 VDDFLASH 8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 GND

9 PA17/PGMD5/AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT 10 PA18/PGMD6/AD1 22 PA9/PGMM1 34 GND 46 XIN/PGMCK 11 PA19/PGMD7/AD2 23 PA8/PGMM0 35 PA1/PGMEN1 47 PLLRC 12 PA20/AD3 24 PA7/PGMNVALID 36 PA0/PGMEN0 48 VDDPLL

Note: 1. The bottom pad of the QFN package must be connected to ground.

(1)

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5. Power Considerations

5.1 Power Supplies

The SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are:

z VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal. z VDDOUT pin. It is the output of the 1.8V voltage regulator. z VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.0V

to 3.6V , 3 .3V nominal or from 1.65V to 1.95V, 1.8V nominal. Note that supplying less than 3.0V to VDDIO prevents any use of the USB transceivers.

z VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges

from 3.0V to 3.6V, 3.3V nominal.

z VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be

connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly.

During startup, core supply voltage (VDDCORE) slope must be superior or equal to 6V/ms.

z VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin.

No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.

In order to decrease current consumption, if the voltage regulator and the ADC are not used, VDDIN, ADVREF, AD4, AD5, AD6 and AD7 should be connected to GND. In this case VDDOUT should be left unconnected.

5.2 Power Consumption

The SAM7S Series has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset. When the brown-out detector is activated, 20 µA static current is added.

The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.

5.3 Voltage Regulator

The SAM7S Series embeds a voltage regulator that is managed by the System Controller. In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current. The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA static current and draws 1

mA of output current. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to

achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT and GND.

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.

5.4 Typical Powering Schematics

The SAM7S Series supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-1 shows the power schematics to be used for USB bus-powered systems.

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Figure 5-1. 3.3V System Single Power Supply Schematic

Power Source

ranges

from 4.5V (USB)

to 18V

3.3V

VDDIN

Voltage

Regulator

VDDOUT

VDDIO

DC/DC Converter

VDDCORE

VDDFLASH

VDDPLL

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6. I/O Lines Considerations

6.1 JTAG Port Pins

TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor.

TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates

a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.

6.2 Test Pin

The TST pin is used for manufacturing test, fast programming mode or SAM-BA Boot Recovery of the SAM7S Series when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.

To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low. To enter SAM-BA Boot Recovery, the TST pin and the PA0, PA1 and PA2 pins should be tied high for at least 10

seconds. Then a power cycle of the board is mandatory. Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.

6.3 Reset Pin

The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to reset all the components of the system.

The NRST pin integrates a permanent pull-up resistor to VDDIO.

6.4 ERASE Pin

The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.

6.5 PIO Controller A Lines

z All the I/O lines PA0 to PA31on SAM7S512/256/128/64/321 (PA0 to PA20 on SAM7S32) are 5V-tolerant and all

integrate a programmable pull-up resistor.

z All the I/O lines PA0 to PA31 on SAM7S161 (PA0 to PA20 on SAM7S16) are not 5V-tolerant and all integrate a

programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to

5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled will create a current path through the pull-up resistor from the I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines default to input with the pull-up resistor enabled at reset.

6.6 I/O Line Drive Levels

The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 150 mA (100 mA for SAM7S32/16).

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7. Processor and Architecture

7.1 ARM7TDMI Processor

z RISC processor based on ARMv4T Von Neumann architecture

z Runs at up to 55 MHz, providing 0.9 MIPS/MHz

z Two instruction sets

z ARM z Thumb

z Three-stage pipeline architecture

z Instruction Fetch (F) z Instruction Decode (D) z Execute (E)

7.2 Debug and Test Features

z Integrated EmbeddedICE

z Two watchpoint units z Test access port accessible through a JTAG protocol z Debug communication channel

z Debug Unit

z Two-pin UART z Debug communication channel interrupt handling z Chip ID Register

z IEEE1149.1 JTAG Boundary-scan on all digital pins

high-performance 32-bit instruction set

high code density 16-bit instruction set

™

(embedded in-circuit emulator)

7.3 Memory Controller

z Bus Arbiter

z Handles requests from the ARM7TDMI and the Peripheral DMA Controller

z Address decoder provides selection signals for

z Three internal 1 Mbyte memory areas z One 256 Mbyte embedded peripheral area

z Abort Status Registers

z Source, Type and all parameters of the access leading to an abort are saved z Facilitates debug by detection of bad pointers

z Misalignment Detector

z Alignment checking of all data accesses z Abort generation in case of misalignment

z Remap Command

z Remaps the SRAM in place of the embedded non-volatile memory z Allows handling of dynamic exception vectors

z Embedded Flash Controller

z Embedded Flash interface, up to three programmable wait states z Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states z Key-protected program, erase and lock/unlock sequencer z Single command for erasing, programming and locking operations z Interrupt generation in case of forbidden operation

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7.4 Peripheral DMA Controller

z Handles data transfer between peripherals and memories z Eleven channels: SAM7S512/256/128/64/321/161 z Nine channels: SAM7S32/16

z Two for each USART z Two for the Debug Unit z Two for the Serial Synchronous Controller z Two for the Serial Peripheral Interface z One for the Analog-to-digital Converter

z Low bus arbitration overhead

z One Master Clock cycle needed for a transfer from memory to peripheral z Two Master Clock cycles needed for a transfer from peripheral to memory

z Next Pointer management for reducing interrupt latency requirements z Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):

Receive DBGU Receive USART0 Receive USART1 Receive SSC Receive ADC Receive SPI Transmit D BGU Transmit USART0 Transmit USART1 Transmit SSC Transmit SPI

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8. Memories

8.1 SAM7S512

z 512 Kbytes of Flash Memory, dual plane

z 2 contiguous banks of 1024 pages of 256 bytes z Fast access time, 30 MHz single-cycle access in Worst Case conditions z Page programming time: 6 ms, including page auto-erase z Page programming without auto-erase: 3 ms z Full chip erase time: 15 ms z 10,000 write cycles, 10-year data retention capability z 32 lock bits, protecting 32 sectors of 64 pages z Protection Mode to secure contents of the Flash

z 64 Kbytes of Fast SRAM

z Single-cycle access at full speed

8.2 SAM7S256

z 256 Kbytes of Flash Memory, single plane

z 1024 pages of 256 bytes z Fast access time, 30 MHz single-cycle access in Worst Case conditions z Page programming time: 6 ms, including page auto-erase z Page programming without auto-erase: 3 ms z Full chip erase time: 15 ms z 10,000 write cycles, 10-year data retention capability z 16 lock bits, protecting 16 sectors of 64 pages z Protection Mode to secure contents of the Flash

z 64 Kbytes of Fast SRAM

z Single-cycle access at full speed

8.3 SAM7S128

z 128 Kbytes of Flash Memory, single plane

z 512 pages of 256 bytes z Fast access time, 30 MHz single-cycle access in Worst Case conditions z Page programming time: 6 ms, including page auto-erase z Page programming without auto-erase: 3 ms z Full chip erase time: 15 ms z 10,000 write cycles, 10-year data retention capability z 8 lock bits, protecting 8 sectors of 64 pages z Protection Mode to secure contents of the Flash

z 32 Kbytes of Fast SRAM

z Single-cycle access at full speed

8.4 SAM7S64

z 64 Kbytes of Flash Memory, single plane

z 512 pages of 128 bytes

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z Fast access time, 30 MHz single-cycle access in Worst Case conditions z Page programming time: 6 ms, including page auto-erase z Page programming without auto-erase: 3 ms z Full chip erase time: 15 ms z 10,000 write cycles, 10-year data retention capability z 16 lock bits, protecting 16 sectors of 32 pages z Protection Mode to secure contents of the Flash

z 16 Kbytes of Fast SRAM

z Single-cycle access at full speed

8.5 SAM7S321/32

z 32 Kbytes of Flash Memory, single plane

z 256 pages of 128 bytes z Fast access time, 30 MHz single-cycle access in Worst Case conditions z Page programming time: 6 ms, including page auto-erase z Page programming without auto-erase: 3 ms z Full chip erase time: 15 ms z 10,000 write cycles, 10-year data retention capability z 8 lock bits, protecting 8 sectors of 32 pages z Protection Mode to secure contents of the Flash

z 8 Kbytes of Fast SRAM

z Single-cycle access at full speed

8.6 SAM7S161/16

z 16 Kbytes of Flash Memory, single plane

z 256 pages of 64 bytes z Fast access time, 30 MHz single-cycle access in Worst Case conditions z Page programming time: 6 ms, including page auto-erase z Page programming without auto-erase: 3 ms z Full chip erase time: 15 ms z 10,000 write cycles, 10-year data retention capability z 8 lock bits, protecting 8 sectors of 32 pages z Protection Mode to secure contents of the Flash

z 4 Kbytes of Fast SRAM

z Single-cycle access at full speed

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Figure 8-1. SAM7S512/256/128/64/321/32/161/16 Memory Mapping

Internal Memory Mapping

0x0000 0000

Flash before Remap

SRAM after Remap

0x000F FFF

0x0000 0000

Address Memory Space

Internal Memories

256 MBytes

0x0010 0000

0x001F FFF

0x0020 0000

0x002F FFF

0x0030 0000

Internal Flash

Internal SRAM

Reserved

(1)

1 MBytes

253 MBytes

Note: (1) Can be Flash or SRAM

depending on REMAP.

0x0FFF FFFF

0x1000 0000

0xEFFF FFFF

0xF000 0000

0xFFFF FFFF

Undefined

(Abort)

Internal Peripherals

14 x 256 MBytes 3,584 MBytes

256M Bytes

0x0FFF FFFF

0xF000 0000

0xFFF9 FFFF

0xFFFA 0000

0xFFFA 3FFF

0xFFFA 4000

0xFFFA FFFF

0xFFFB 0000

0xFFFB 3FFF

0xFFFB 4000

0xFFFB 7FFF

0xFFFB 8000

0xFFFB BFFF 0xFFFB C000

0xFFFB FFFF

0xFFFC 0000

0xFFFC 3FFF

0xFFFC 4000

0xFFFC 7FFF

0xFFFC 8000

0xFFFC BFFF 0xFFFC C000

0xFFFC FFFF

0xFFFD 0000

0xFFFD 3FFF

0xFFFD 4000

0xFFFD 7FFF

0xFFFD 8000

0xFFFD BFFF 0xFFFD C000

0xFFFD FFFF

0xFFFE 0000

0xFFFE 3FFF

0xFFFE 4000 0xFFFF EFFF

0xFFFF F000 0xFFFF FFFF

Peripheral Mapping

Reserved

TC0, TC1, TC2

Reserved

UDP

Reserved

TWI

Reserved

USART0

USART1

Reserved

PWMC

Reserved

SSC

ADC

Reserved

SPI

Reserved

SYSC

16 Kbytes

16 Kbytes (Reserved on SAM7S32/16)

16 Kbytes

16 Kbytes 16 Kbytes

(Reserved on SAM7S32/16)

16 Kbytes

System Controller Mapping 0xFFFF F000

AIC

0xFFFF F1FF 0xFFFF F200

DBGU

0xFFFF F3FF 0xFFFF F400

PIOA

0xFFFF F5FF 0xFFFF F600

Reserved

0xFFFF FBFF 0xFFFF FC00

0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F

0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F

0xFFFF FD40 0xFFFF FD4F

0xFFFF FD60 0xFFFF FC6F

0xFFFF FD70 0xFFFF FEFF

0xFFFF FF00

0xFFFF FFFF

PMC

RSTC

Reserved

RTT

PIT

WDT

Reserved

VREG

Reserved

512 Bytes/ 128 registers

256 Bytes/ 64 registers

16 Bytes/ 4 registers

16 Bytes/ 4 registers 16 Bytes/ 4 registers

4 Bytes/ 1 register

256 Bytes/ 64 registers

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8.7 Memory Mapping

256 MBytes

Flash Before Remap

SRAM After Remap

Undefined Areas

(Abort)

0x000F FFFF

0x001F FFFF

0x002F FFFF

0x0FFF FFFF

1 MBytes

253 MBytes

Internal Flash

Internal SRAM

0x0000 0000

0x0010 0000

0x0020 0000

0x0030 0000

8.7.1 Internal SRAM

z The SAM7S512 embeds a high-speed 64-Kbyte SRAM bank. z The SAM7S256 embeds a high-speed 64-Kbyte SRAM bank. z The SAM7S128 embeds a high-speed 32-Kbyte SRAM bank. z The SAM7S64 embeds a high-speed 16-Kbyte SRAM bank. z The SAM7S321 embeds a high-speed 8-Kbyte SRAM bank. z The SAM7S32 embeds a high-speed 8-Kbyte SRAM bank. z The SAM7S161 embeds a high-speed 4-Kbyte SRAM bank. z The SAM7S16 embeds a high-speed 4-Kbyte SRAM bank

After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0.

8.7.2 Internal ROM

The SAM7S Series embeds an Internal ROM. The ROM contains the FFPI and the SAM-BA program. The internal ROM is not mapped by default.

8.7.3 Internal Flash

z The SAM7S512 features two contiguous banks (dual plane) of 256 Kbytes of Flash. z The SAM7S256 features one bank (single plane) of 256 Kbytes of Flash. z The SAM7S128 features one bank (single plane) of 128 Kbytes of Flash. z The SAM7S64 features one bank (single plane) of 64 Kbytes of Flash. z The SAM7S321/32 features one bank (single plane) of 32 Kbytes of Flash. z The SAM7S161/16 features one bank (single plane) of 16 Kbytes of Flash.

At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command.

Figure 8-2. Internal Memory Ma pping

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8.8 Embedded Flash

8.8.1 Flash Overview

z The Flash of the SAM7S512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes

are organized in 32-bit words.

z The Flash of the SAM7S256 is organized in 1024 pages (single plane) of 256 bytes. The 262,144 bytes are

organized in 32-bit words.

z The Flash of the SAM7S128 is organized in 512 pages (single plane) of 256 bytes. The 131,072 bytes are

organized in 32-bit words.

z The Flash of the SAM7S64 is organized in 512 pages (single plane) of 128 bytes. The 65,536 bytes are organized

in 32-bit words.

z The Flash of the SAM7S321/32 is organized in 256 pages (single plane) of 128 bytes. The 32,768 bytes are

organized in 32-bit words.

z The Flash of the SAM7S161/16 is organized in 256 pages (single plane) of 64 bytes. The 16,384 bytes are

organized in 32-bit words.

z The Flash of the SAM7S512/256/128 contains a 256-byte write buffer, accessible through a 32-bit interface. z The Flash of the SAM7S64/321/32/161/16 contains a 128-byte write buffer, accessible through a 32-bit interface.

The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions.

When Flash is not used (read or write access), it is automatically placed into standby mode.

8.8.2 Embedded Flash Controller

The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows:

z programming of the access parameters of the Flash (number of wait states, timings, etc.) z starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. z getting the end status of the last command z getting error status z programming interrupts on the end of the last commands or on errors

The Embedded Flash Controller also provides a dual 32-bit prefetch buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode.

Two EFCs are embedded in the SAM7S512 to control each bank of 256 Kbytes. Dual plane organization allows concurrent Read and Program. Read from one memory plane may be performed even while program or erase functions are being executed in the other memory plane.

One EFC is embedded in the SAM7S256/128/64/32/321/161/16 to control the single plane 256/128/64/32/16 Kbytes.

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8.8.3 Lock Regions

8.8.3.1 SAM7S512

Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR register rises and the interrupt line rises if the LOCKE bit has been written at 1 in the MC_FMR register.

The 16 NVM bits (or 32 NVM bits) are software programmable through the corresponding EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.8.3.2 SAM7S256

The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.8.3.3 SAM7S128

The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.8.3.4 SAM7S64

The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S64 contains 16 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes.

The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.8.3.5 SAM7S321/32

The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S321/32 contains 8 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes.

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The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.8.3.6 SAM7S161/16

The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S161/16 contains 8 lock regions and each lock region contains 32 pages of 64 bytes. Each lock region has a size of 2 Kbytes.

The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

Table 8-1 summarizes the configuration of the eight devices.

Table 8-1. Flash Configuration Summary

Device Number of Lock Bits Number of Pages in the Lock Region Page Size

SAM7S512 32 64 256 bytes SAM7S256 16 64 256 bytes SAM7S128 8 64 256 bytes SAM7S64 16 32 128 bytes SAM7S321/32 8 32 128 bytes SAM7S161/16 8 32 64 bytes

8.8.4 Security Bit Feature

The SAM7S Series features a security bit, based on a specific NVM Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.

This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted.

It is important to note that the assertion of the ERASE pin should always be longer than 50 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is

safer to connect it directly to GND for the final application.

8.8.5 Non-volatile Brownout Detector Control

Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state.

These two GPNVM bits can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.

 GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it

disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.

 The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1

enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset.

Asserting ERASE disables the brownout reset by default.

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8.8.6 Calibration Bits

Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.

8.9 Fast Flash Programming Interface

The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.

The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the

PA0 and PA1 pins are all tied high and PA2 is tied low.

8.10 SAM-BA Boot Assistant

The SAM-BA® Boot Recovery restores the SAM-BA Boot in th e fir st t wo s ec tor s o f th e o n -chip Fla sh me m or y. T h e SAM-BA Boot recovery is performed when the TST pin and t he PA0, PA1 an d PA2 pins ar e all tied high f or 10 seconds. Then, a power cycle of the board is mandatory.

The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory.

The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port. (The SAM7S32/16 have no USB Device Port.)

z Communication through the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-

detection.

z Communication through the USB Device Port is limited to an 18.432 MHz crystal. (

The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).

9. System Controller

The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF

F000 and 0xFFFF FFFF.

Figure 9-1 on page 26 and Figure 9-2 on page 27 show the product specific System Controller Block Diagrams. Figure 8-1 on page 20 shows the mapping of the of the User Interface of the System Controller peripherals. Note that the

memory controller configuration user interface is also mapped within this address space.

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Figure 9-1. System Contro lle r Block Diagram (SAM7S512/256/128/64/321/161)

NRST

SLCK

Advanced

Interrupt Controller

Real-Time

Timer

Periodic

Interval

Timer

Reset

Controller

PA0-PA31

periph_nreset

System Controller

Watchdog

Timer

wdt_fault WDRPROC

PIO

Controller

POR

BOD

RCOSC

gpnvm[0]

cal

Power

Management

Controller

OSC

PLL

XIN

XOUT

PLLRC

MAINCK

PLLCK

pit_irq

MCK

proc_nreset

wdt_irq

periph_irq{2]periph_nreset

periph_clk[2..14]

PCK

MCK

pmc_irq

UDPCK

nirq nfiq

rtt_irq

Embedded Peripherals

periph_clk[2]

pck[0-2]

in out enable

ARM7TDMI

SLCK

irq0-irq1 fiq

irq0-irq1

fiq

periph_irq[4..14]

periph_irq[2..14]

int

periph_nreset

periph_clk[4..14]

Embedded

Flash

flash_poe

jtag_nreset

flash_poe

gpnvm[0..1]

flash_wrdis

proc_nreset

periph_nreset

dbgu_txd

dbgu_rxd

pit_irq

rtt_irq

dbgu_irq

pmc_irq

rstc_irq

wdt_irq

rstc_irq

SLCK

gpnvm[1]

Boundary Scan

TAP Controller

jtag_nreset

debug

PCK

debug

idle

debug

Memory

Controller

MCK

proc_nreset

bod_rst_en

proc_nreset

idle

Debug

Unit

dbgu_irq

MCK

dbgu_rxd

periph_nreset

force_ntrst dbgu_txd

USB Device

Port

UDPCK

periph_nreset

periph_clk[11]

periph_irq[11]

usb_suspend

Voltage

Regulator

standby

Voltage

Regulator

Mode

Controller

security_bit

cal

power_on_reset force_ntrst

cal

power_on_reset

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Figure 9-2. System Contro lle r Block Diagram (SAM7S32/16)

NRST

SLCK

Advanced

Interrupt

Controller

Real-Time

Timer

Periodic

Interval

Timer

Reset

Controller

PA0-PA20

periph_nreset

System Controller

Watchdog

Timer

wdt_fault WDRPROC

PIO

Controller

POR

BOD

RCOSC

gpnvm[0]

cal

Power

Management

Controller

OSC

PLL

XIN

XOUT

PLLRC

MAINCK

PLLCK

pit_irq

MCK

proc_nreset

wdt_irq

periph_irq{2]periph_nreset

periph_clk[2..14]

PCK

MCK

pmc_irq

nirq nfiq

rtt_irq

Embedded Peripherals

periph_clk[2]

pck[0-2]

in out enable

ARM7TDMI

SLCK

irq0 fiq

irq0

fiq

periph_irq[4..14]

periph_irq[2..14]

int

periph_nreset

periph_clk[4..14]

Embedded

Flash

flash_poe

gpnvm[0..1]

flash_wrdis

proc_nreset

periph_nreset

dbgu_txd

dbgu_rxd

pit_irq

rtt_irq

dbgu_irq

pmc_irq

rstc_irq

wdt_irq

rstc_irq

SLCK

gpnvm[1]

Boundary Scan

TAP Controller

jtag_nreset

debug

PCK

debug

idle

debug

Memory

Controller

MCK

proc_nreset

bod_rst_en

proc_nreset

periph_nreset

idle

Debug

Unit

dbgu_irq

MCK

dbgu_rxd

periph_nreset

force_ntrst dbgu_txd

Voltage

Regulator

standby

Voltage

Regulator

Mode

Controller

security_bit

cal

force_ntrst

cal

flash_poe

jtag_nreset

power_on_reset

flash_wrdis

power_on_reset

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9.1 Reset Controller

The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. In addition, it controls the internal resets and the NRST pin open-drain output. It allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement.

Note that if NRST is used as a reset output signal for external devices during power-off, the brownout detector must be activated.

9.1.1 Brownout Detector and Power-on Reset

The SAM7S Series embeds a brownout detection circuit and a power-on reset cell. Both are supplied with and monitor VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brownouts occur on the VDDCORE power supply.

The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device.

The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE.

Only VDDCORE is monitored. When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot-, defined as

Vbot - hyst/2), the brownout output is immediately activated. When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + hyst/2), the reset is released. The

brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs.

The threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated.

The brownout detector is low-power, as it consumes less than 20 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash.

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9.2 Clock Generator

Embedded

Oscillator

Main

Oscillator

PLL and

Divider

Clock Generator

Power

Management

Controller

XIN

XOUT

PLLRC

Slow Clock SLCK

Main Clock MAINCK

PLL Clock PLLCK

Control

Status

The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics:

z RC Oscillator ranges between 22 kHz and 42 kHz z Main Oscillator frequency ranges between 3 and 20 MHz z Main Oscillator can be bypassed z PLL output ranges between 80 and 220 MHz

It provides SLCK, MAINCK and PLLCK.

Figure 9-3. Clock Generator Block Diagram

9.3 Power Management Controller

The Power Management Controller uses the Clock Generator outputs to provide:

z the Processor Clock PCK z the Master Clock MCK z the USB Clock UDPCK (not present on SAM7S32/16) z all the peripheral clocks, independently controllable z three programmable clock outputs

The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption

while waiting for an interrupt.

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MCK

periph_clk[2..14]

int

UDPCK

usb_suspend

SLCK

MAINCK

PLLCK

Prescaler

/1,/2,/4,...,/64

PCK

Processor

Clock

Controller

Idle Mode

Master Clock Controller

Peripherals

Clock Controller

ON/OFF

USB Clock Controller

ON/OFF

SLCK

MAINCK

PLLCK

Prescaler

/1,/2,/4,...,/64

Programmable Clock Controller

PLLCK

Divider /1,/2,/4

pck[0..2]

Figure 9-4. Power Management Controller Block Diagra m

9.4 Advanced Interrupt Controller

z Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor z Individually maskable and vectored interrupt sources

z Source 0 is reserved for the Fast Interrupt Input (FIQ) z Source 1 is reserved for system peripherals RTT, PIT, EFC, PMC, DBGU, etc.) z Other sources control the peripheral interrupts or external interrupts z Programmable edge-triggered or level-sensitive internal sources z Programmable positive/negative edge-triggered or high/low level-sensitive external sources

z 8-level Priority Controller

z Drives the normal interrupt of the processor z Handles priority of the interrupt sources z Higher priority interrupts can be served during service of lower priority interrupt

z Vectoring

z Optimizes interrupt service routine branch and execution z One 32-bit vector register per interrupt source z Interrupt vector register reads the corresponding current interrupt vector

z Protect Mode

z Fast Forcing

z General Interrupt Mask

z Easy debugging by preventing automatic operations

z Permits redirecting any interrupt source on the fast interrupt

z Provides processor synchronization on events without triggering an interrupt

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9.5 Debug Unit

z Comprises:

z One two-pin UART z One Interface for the Debug Communication Channel (DCC) support z One set of Chip ID Registers z One Interface providing ICE Access Prevention

z Two-pin UART

z Implemented features are compatible with the USART z Programmable Baud Rate Generator z Parity, Framing and Overrun Error z Automatic Echo, Local Loopback and Remote Loopback Channel Modes

z Debug Communication Channel Support

z Offers visibility of COMMRX and COMMTX signals from the ARM Processor

z Chip ID Registers

z Identification of the device revision, sizes of the embedded memories, set of peripherals z Chip ID is 0x270B0A40 for AT91SAM7S512 Rev A z Chip ID is 0x270B0A4F for AT91SAM7S512 Rev B z Chip ID is 0x270D0940 for AT91SAM7S256 Rev A z Chip ID is 0x270B0941 for AT91SAM7S256 Rev B z Chip ID is 0x270B0942 for AT91SAM7S256 Rev C z Chip ID is 0x270B0943 for AT91SAM7S256 Rev D z Chip ID is 0x270C0740 for AT91SAM7S128 Rev A z Chip ID is 0x270A0741 for AT91SAM7S128 Rev B z Chip ID is 0x270A0742 for AT91SAM7S128 Rev C z Chip ID is 0x270A0743 for AT91SAM7S128 Rev D z Chip ID is 0x27090540 for AT91SAM7S64 Rev A z Chip ID is 0x27090543 for AT91SAM7S64 Rev B z Chip ID is 0x27090544 for AT91SAM7S64 Rev C z Chip ID is 0x27080342 for AT91SAM7S321 Rev A z Chip ID is 0x27080340 for AT91SAM7S32 Rev A z Chip ID is 0x27080341 for AT91SAM7S32 Rev B z Chip ID is 0x27050241 for AT9SAM7S161 Rev A z Chip ID is 0x27050240 for AT91SAM7S16 Rev A

Note: Refer to the errata section of the datasheet for updates on chip ID.

9.6 Periodic Interval Timer

z 20-bit programmable counter plus 12-bit interval counter

9.7 Watchdog Timer

z 12-bit key-protected Programmable Counter running on prescaled SCLK z Provides reset or interrupt signals to the system z Counter may be stopped while the processor is in debug state or in idle mode

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9.8 Real-time Timer

z 32-bit free-running counter with alarm running on prescaled SCLK z Programmable 16-bit prescaler for SLCK accuracy compensation

9.9 PIO Controller

z One PIO Controller, controlling 32 I/O lines (21 for SAM7S32/16) z Fully programmable through set/clear registers z Multiplexing of two peripheral functions per I/O line z For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)

z Input change interrupt z Half a clock period glitch filter z Multi-drive option enables driving in open drain z Programmable pull-up on each I/O line z Pin data status register, supplies visibility of the level on the pin at any time

z Synchronous output, prov ides Set and Clear of several I/O lines in a single write

9.10 Voltage Regulator Controller

The aim of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).

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10. Peripherals

10.1 User Interface

The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space.

A complete memory map is provided in Figure 8-1 on page 20.

10.2 Peripheral Identifiers

The SAM7S Series embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the SAM7S512/256/128/64/321/161. Table 10-2 defines the Peripheral Identifiers of the SAM7S32/16. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.

Table 10-1. Peripheral Identifiers (SAM7S512/256/128/64/321/161)

Peripheral ID

0 AIC Advanced Interrupt Controller FIQ 1 SYSC 2 PIOA Parallel I/O Controller A 3 Reserved 4 ADC 5 SPI Serial Peripheral Interface 6 US0 USART 0 7 US1 USART 1 8 SSC Synchronous Serial Controller 9 TWI Two-wire Interface 10 PWMC PWM Controller 11 UDP USB Device Port 12 TC0 Timer/Counter 0 13 TC1 Timer/Counter 1 14 TC2 Timer/Counter 2 15 - 29 Reserved

Peripheral Mnemonic

(1)

Peripheral Name

System

Analog-to Digital Converter

External Interrupt

30 AIC Advanced Interrupt Controller IRQ0 31 AIC Advanced Interrupt Controller IRQ1

Note: 1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller

is continuously clocked. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.

Note: 1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller

is continuously clocked. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.

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Table 10-2. Peripheral Identifiers (SAM7S32/16)

Peripheral ID

0 AIC Advanced Interrupt Controller FIQ 1 SYSC 2 PIOA Parallel I/O Controller A 3 Reserved 4 ADC 5 SPI Serial Peripheral Interface 6 US USART 7 Reserved 8 SSC Synchronous Serial Controller 9 TWI Two-wire Interface 10 PWMC PWM Controller 11 Reserved 12 TC0 Timer/Counter 0 13 TC1 Timer/Counter 1 14 TC2 Timer/Counter 2 15 - 29 Reserved 30 AIC Advanced Interrupt Controller IRQ0 31 Reserved

Peripheral Mnemonic

(1)

Peripheral Name

System

Analog-to Digital Converter

External Interrupt

10.3 Peripheral Multiplexing on PIO Lines

The SAM7S Series features one PIO controller, PIOA, that multiplexes the I/O lines of the peripheral set. PIO Controller A controls 32 lines (21 lines for SAM7S32/16). Each line can be assigned to one of two peripheral

functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller.

Table 10-3, “Multiplexing on PIO Controller A (SAM7S512/256/128/64/321/161),” on page 35 and Table 10-4, “Multiplexing on PIO Controller A (SAM7S32/16),” on page 36 define how the I/O lines of the peripherals A, B or the

analog inputs are multiplexed on the PIO Controller A. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application.

Note that some peripheral functions that are output only may be duplicated in the table. All pins reset in their Parallel I/O lines function are configured as input with the programmable pull-up enabled, so that the

device is maintained in a static state as soon as a reset is detected.

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10.4 PIO Controller A Multiplexing

Table 10-3. Multiplexing on PIO Controller A (SAM7S512/256/128/64/321/161)

PIO Controller A Application Usage

I/O Line Peripheral A Peripheral B Comments Function Comments

PA0 PWM0 TIOA0 High-Drive PA1 PWM1 TIOB0 High-Drive PA2 PWM2 SCK0 High-Drive PA3 TWD NPCS3 High-Drive PA4 TWCK TCLK0 PA5 RXD0 NPCS3 PA6 TXD0 PCK0 PA7 RTS0 PWM3 PA8 CTS0 ADTRG PA9 DRXD NPCS1 PA10 DTXD NPCS2 PA11 NPCS0 PWM0 PA12 MISO PWM1 PA13 MOSI PWM2 PA14 SPCK PWM3 PA15 TF TIOA1 PA16 TK TIOB1 PA17 TD PCK1 AD0 PA18 RD PCK2 AD1 PA19 RK FIQ AD2 PA20 PA21 RXD1 PCK1 PA22 TXD1 NPCS3 PA23 SCK1 PWM0 PA24 RTS1 PWM1 PA25 CTS1 PWM2 PA26 DCD1 TIOA2 PA27 DTR1 TIOB2 PA28 DSR1 TCLK1 PA29 RI1 TCLK2 PA30 IRQ1 NPCS2

RF IRQ0 AD3

PA31 NPCS1 PCK2

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Table 10-4. Multiplexing on PIO Controller A (SAM7S32/16)

PIO Controller A Application Usage

I/O Line Peripheral A Peripheral B Comments Function Comments

RF IRQ0 AD3

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10.5 Serial Peripheral Interface

 Supports communication with external serial devices

 Four chip selects with external decoder allow communication with up to 15 peripherals  Serial memories, such as DataFlash  Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors  External co-processors

 Master or slave serial peripheral bus interface

 8- to 16-bit programmable data length per chip select  Programmable phase and polarity per chip select  Programmable transfer delays between consecutive transfers and between clock and data per chip select  Programmable delay between consecutive transfers  Selectable mode fault detection  Maximum frequency at up to Master Clock

10.6 Two-wire Interface

 Master Mode only (SAM7S512/256/128/64/321/32)  Master, Multi-Master and Slave Mode support (SAM7S161/16)  General Call supported in Slave Mode (SAM7S161/16)  Compatibility with I  One, two or three bytes internal address registers for easy Serial Memory access  7-bit or 10-bit slave addressing  Sequential read/write operations

C compatible devices (refer to the TWI sections of the datasheet)

and 3-wire EEPROMs

10.7 USART

 Programmable Baud Rate Generator  5- to 9-bit full-duplex synchronous or asynchronous serial communications

 RS485 with driver control signal  ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

 IrDA modulation and demodulation

 Test Modes

 1, 1.5 or 2 stop bits in Asynchronous Mode  1 or 2 stop bits in Synchronous Mode  Parity generation and error detection  Framing error detection, overrun error detection  MSB or LSB first  Optional break generation and detection  By 8 or by 16 over-sampling receiver frequency  Hardware handshaking RTS - CTS  Modem Signals Management DTR-DSR-DCD-RI on USART1 (not present on SAM7S32/16)  Receiver time-out and transmitter timeguard  Multi-drop Mode with address generation and detection

 NACK handling, error counter with repetition and iteration limit

 Communication at up to 115.2 Kbps

 Remote Loopback, Local Loopback, Automatic Echo

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10.8 Serial Synchronous Controller

 Provides serial synchronous communication links used in audio and telecom applications  Contains an independent receiver and transmitter and a common clock divider  Offers a configurable frame sync and data length  Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame

sync signal

 Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal

10.9 Timer Counter

 Three 16-bit Timer Counter Channels

 Two output compare or one input capture per channel (except for SAM7S32/16 which have only two

channels connected to the PIO)

 Wide range of functions including:

 Frequency measurement  Event counting  Interval measurement  Pulse generation  Delay timing  Pulse Width Modulation  Up/down capabilities

 Each channel is user-configurable and contains:

 Three external clock inputs (The SAM7S32/16 have one)  Five internal clock inputs, as defined in Table 10-5

Table 10-5. Timer Counter Clocks Assignment

TC Clock Input Clock

TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 MCK/1024

 Two multi-purpose input/output signals  Two global registers that act on all three TC channels

10.10 PWM Controller

 Four channels, one 16-bit counter per channel  Common clock generator, providing thirteen different clocks

 One Modulo n counter providing eleven clocks  Two independent linear dividers working on modulo n counter outputs

 Independent channel programming

 Independent enable/disable commands  Independent clock selection  Independent period and duty cycle, with double buffering  Programmable selection of the output waveform polarity

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 Programmable center or left aligned output waveform

10.11 USB Device Port (Does not pertain to SAM7S32/16)

 USB V2.0 full-speed compliant, 12 Mbits per second.  Embedded USB V2.0 full-speed transceiver  Embedded 328-byte dual-port RAM for endpoints  Four endpoints

 Endpoint 0: 8 bytes  Endpoint 1 and 2: 64 bytes ping-pong  Endpoint 3: 64 bytes  Ping-pong Mode (two memory banks) for isochronous and bulk endpoints

 Suspend/resume logic

10.12 Analog-to-digital Converter

 8-channel ADC  10-bit 384 Ksamples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register ADC  ±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity  Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs  External voltage reference for better accuracy on low voltage inputs  Individual enable and disable of each channel  Multiple trigger source

 Hardware or software trigger  External trigger pin  Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger

 Sleep Mode and conversion sequencer

 Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels

 Four of eight analog inputs shared with digital signals

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11. ARM7TDMI Processor Overview

11.1 Overview

The ARM7TDMI core executes both the 32-bit ARM® and 16-bit Thumb® instruction sets, allowing the user to trade off between high performance and high code density.The ARM7T DMI processor implements Vo n Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages.

The main features of the ARM7TDMI processor are:

• ARM7TDMI Based on ARMv4T Architecture

• Two Instruction Sets –ARM –Thumb

• Three-Stage Pipeline Architecture – Instruction Fetch (F) – Instruction – Execute (E)

High-performance 32-bit Instru ctio n Set

High Code Density 16-bit Instruction Set

Decode (D)

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11.2 ARM7TDMI Processor

For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B)

11.2.1 Instruction Type

Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB stat e).

11.2.2 Data Type

ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to fourbyte boundaries and half words to two-byte boundaries.

Unaligned data access behavior depends on which instruction is used where.

11.2.3 ARM7TDMI Operating Mode

The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes:

User: The normal ARM program execution state FIQ: Designed to support high-speed data transfer or channel process IRQ: Used for general-purpose interrupt handling Supervisor: Protected mode for the operating system Abort mode: Implements virtual memory and/or memory pr otection System: A privileged user mode for the operating system Undefined: Supports software emulation of hardware coprocessors

Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application pr ograms execute in User mode. The non-user mo des, or privileged modes, are entered in order to service interrupts or except ions, or to access protected resources.

11.2.4 ARM7TDMI Registers

The ARM7TDMI processor has a total of 37registers:

• 31 general-purpose 32-bit registers

• 6 status registers

These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer.

At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing.

Register 15 is the Program Counter (PC) and can be used in all instruction s to reference data relative to the current instruction.

R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer.

Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-bit physical register in all processor modes. They ar e ge ne r al- pu rp o se re gis ter s, with no special uses managed by th e ar ch ite ctu re , and can be used wherever an instruction allows a general-purpose register to be specified.

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Table 11-1. ARM7TDMI ARM Modes and Registers Layout

User and System Mode

R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R11 R11 R11 R11 R11 R12 R12 R12 R12 R12 R12_FIQ R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ PC PC PC PC PC PC

Supervisor Mode Abort Mode

Undefined Mode

Interrupt Mode

Fast Interrupt Mode

R8_FIQ

R10_FIQ R11_FIQ

CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ

Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor.

11.2.4.1 Modes and Exception Handling

All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used to return after the

exception is processed, as well as to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save

these registers. A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers.

System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions.

11.2.4.2 Status Registers

All other processor states are held in status registers. The current ope ratin g pr ocessor sta tu s is in the Current Program Status Register (CPSR). The CPSR holds:

Mode-specific banked registers

• four ALU flags (Negative, Zero, Carry, and Overflow)

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• two interrupt disable bits (one for each type of interrupt)

• one bit to indicate ARM or Thumb execution

• five bits to encode the current processor mode

All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception.

11.2.4.3 Exception Types

The ARM7TDMI supports five types of exception and a privileged processing mode for each type. The types of

exceptions are:

• fast interrupt (FIQ )

• normal interrupt (IRQ)

• memory aborts (used to implement memory protection or virtual memory)

• attempted execution of an undefined instruction

• software interrupts (SWIs)

Exceptions are generated by internal and external sources. More than one exception can occur in the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save

state. To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be

done in two ways:

• by using a data-processing instruction with the S-bit set, and the PC as the destination

• by using the Load Multiple with Restore CPSR instruction (LDM)

11.2.5 ARM Instruction Set Overview

The ARM instruction set is divided into:

• Branch instructions

• Data processing instructions

• Status register transfer instructions

• Load and Store instructions

• Coprocessor instructions

• Exception-generating instructions

ARM instructions can be executed conditionally. Every instruction cont ains a 4-bit condition code field (bit[31:28]).

Table 11-2 gives the ARM instruction mnemonic list.

Table 11-2. ARM Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

MOV Move CDP Coprocessor Data Processing ADD Add MVN Move Not SUB Subtract ADC Add with Carry RSB Reverse Subtract SBC Subtract with Carry CMP Compare RSC Reverse Subtract with Carry TST Test CMN Compare Negated

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Table 11-2. ARM Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

AND Logical AND TEQ Test Equivalence EOR Logical Exclusive OR BIC Bit Clear MUL Multiply ORR Logical (inclusive) OR SMULL Sign Long Multiply MLA Multiply Accumulate SMLAL Signed Long Multiply Accumulate UMULL Unsigned Long Multiply MSR Move to Status Register UMLAL Unsigned Long Multiply Accumulate B Branch MRS Move From Status Register BX Branch and Exchange BL Branch and Link LDR Load Word SWI Software Interrupt LDRSH Load Signed Halfword STR Store Word LDRSB Load Signed Byte STRH Store Half Word LDRH Load Half Word STRB Store Byte LDRB Load Byte STRBT Store Register Byte with Translation LDRBT Load Register Byte with Translation STRT Store Register with Translation LDRT Load Register with Translation STM Store Multiple LDM Load Multiple SWPB Swap Byte SWP Swap Word MRC Move From Coprocessor MCR Move To Coprocessor STC Store From Coprocessor LDC Load To Coprocessor

11.2.6 Thumb Instruction Set Overview

The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into:

• Branch instructions

• Data processing instructions

• Load and Store instructions

• Load and Store Multiple instructions

• Exception-generating instruction

In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15.

Table 11-3 gives the Thumb instruction mnemonic list.

Table 11-3. Thumb Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry

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Table 11-3. Thumb Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

CMP Compare CMN Compare Negated TST Test NEG Negate AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR LSL Logical Shift Left LSR Logical Shift Right ASR Arithmetic Shift Right ROR Rotate Right MUL Multiply B Branch BL Branch and Link BX Branch and Exchange SWI Software Interrupt LDR Load Word STR Store Word LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRSH Load Signed Halfword LDRSB Load Signed Byte LDMIA Load Multiple STMIA Store Multiple PUSH Push Register to stack POP Pop Register from stack

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12. Debug and Test Features

ICE

PDC

DBGU

PIO

DRXD

DTXD

TST

TMS

TCK

TDI

JTAGSEL

TDO

Boundary

TAP

ICE/JTAG

TAP

ARM7TDMI

Reset

and Test

POR

12.1 Description

The SAM7S Series Microcontrollers feature a number of complementary debug and test capabilities. A common JTAG/ICE (EmbeddedICE) port is used for standard debugging functions, such as downloading code and singlestepping through programs. The Debug Unit provide s a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal CO MMTX and COMMRX signals that trace the activity of the Debug Communication Channel.

A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.

12.2 Block Diagram

Figure 12-1. Debug and Test Block Diagram

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12.3 Application Examples

12.3.1 Debug Environment

Figure 12-2 on page 48 shows a complete debug environment example. The ICE/JTAG interface is used for stan-

dard debugging functions, such as downloading code and single-stepping through the program.

Figure 12-2. Application Debug Environment Example

Host Debugger

ICE/JTAG

Interface

ICE/JTAG

Connector

SAM7S

SAM7S-based Application Board

RS232

Connector

Terminal

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12.3.2 Test Environment

Figure 12-3 on page 49 shows a test environment example. Test vectors are sent and interpreted by the tester. In

this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain.

Figure 12-3. Application Test Environment Example

Test Adaptor

JTAG

Interface

ICE/JTAG

Connector

SAM7S

SAM7S-based Application Board In Test

Chip 2Chip n

Chip 1

Tester

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12.4 Debug and Test Pin Description

Table 12-1. Debug and Test Pin List

Pin Name Function Type Active Level

NRST Microcontroller Reset Input/Output Low TST Test Mode Select Input High

TCK Test Clock Input TDI Test Data In Input TDO Test Data Out Output TMS Test Mode Select Input JTAGSEL JTAG Selection Input

DRXD Debug Receive Data Input DTXD Debug Transmit Data Output

Reset/Test

ICE and JTAG

Debug Unit

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12.5 Functional Description

12.5.1 Test Pin

One dedicated pin, TST, is used to d ef ine t he de vice op era ti ng mod e. Th e use r must ma ke sur e t hat t his pin is t ied at low level to ensure normal operating conditions. Other values associated with th is pin are reserved f or manuf acturing test.

12.5.2 EmbeddedICE

The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is examined through an ICE/JTAG port.

The ARM7TDMI processor contains hardware exte nsions for advanced debugging features:

• In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of

the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system.

• In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor

program running on the ARM7TDMI processor.

There are three scan chains inside the ARM7TDMI processo r that su pport test ing, debu gging, and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port.

EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch dir ectly bet wee n ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.

For further details on the EmbeddedICE, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).

12.5.3 Debug Unit

The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum.

The Debug Unit also manages the interrupt handling of the COMMT X and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Ch an nel.Th e De bug Unit allo ws blo ckage of ac ce ss to the system through the ICE interface.

™

(Embedded In-circuit Emulator)

A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration.

Table 12-2. SAM7S Series Debug Unit Chip ID

Chip Name Chip ID

AT91SAM7S16 Rev A 0x27050240 AT91SAM7S161 Rev A 0x27050241 AT91SAM7S32 Rev A 0x27080340 AT91SAM7S32 Rev B 0x27080341 AT91SAM7S321 Rev A 0x27080342 AT91SAM7S64 Rev A 0x27090540 AT91SAM7S64 Rev B 0x27090543 AT91SAM7S64 Rev C 0x27090544 AT91SAM7S128 Rev A 0x270C0740

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Table 12-2. SAM7S Series Debug Unit Chip ID (Continued)

AT91SAM7S128 Rev B 0x270A0741 AT91SAM7S128 Rev C 0x270A0742 AT91SAM7S128 Rev D 0x270A0743 AT91SAM7S256 Rev A 0x270D0940 AT91SAM7S256 Rev B 0x270B0941 AT91SAM7S256 Rev C 0x270B0942 AT91SAM7S256 Rev D 0x270B0943 AT91SAM7S512 Rev A 0x270B0A40 AT91SAM7S512 Rev B 0x270B0A4F

For further details on the Debug Unit, see the Debug Unit section.

12.5.4 IEEE 1149.1 JTAG Boundary Scan

IEEE 1149.1 JTAG Boundary Scan allows pin-level access indepe ndent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS func-

tions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.

It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed.

A Boundary-scan Descriptor Language (BSDL) file is provided to set up testing.

12.5.4.1 JTAG Boundary-scan Register

The Boundary-scan Register (BSR) contains 96 bits that correspond to active pins and associated control signals. Each SAM7Sxx input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that

can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad.

Table 12-3. SAM7Sxx JTAG Boundary Scan Register

Bit Number Pin Name Pin Type

96 95 OUTPUT 94 CONTROL 93 92 OUTPUT 91 CONTROL 90 89 OUTPUT 88 CONTROL

PA17/PGMD5/AD0 IN/OUT

PA18/PGMD6/AD1 IN/OUT

PA21/PGMD9* IN/OUT*

Associated BSR

Cells

INPUT

(1)

INPUT

(1)

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Table 12-3. SAM7Sxx JTAG Boundary Scan Register (Continued)

Bit Number Pin Name Pin Type

Associated BSR

Cells

INPUT 86 OUTPUT 85 CONTROL 84 83 OUTPUT 82 CONTROL 81 80 OUTPUT 79 CONTROL 78 77 OUTPUT 76 CONTROL 75 74 OUTPUT 73 CONTROL 72 71 OUTPUT 70 CONTROL 69 68 OUTPUT 67 CONTROL 66 65 OUTPUT 64 CONTROL 63 62 OUTPUT 61 CONTROL

PA19/PGMD7/AD2 IN/OUT

PA20/PGMD8/AD3 IN/OUT

PA16/PGMD4 IN/OUT

PA15/PGM3 IN/OUT

PA14/PGMD2 IN/OUT

PA13/PGMD1 IN/OUT

PA22/PGMD10* IN/OUT*

PA23/PGMD11* IN/OUT*

PA24/PGMD12* IN/OUT*

INPUT

(1)

60 59 OUTPUT 58 CONTROL 57 56 OUTPUT 55 CONTROL 54 53 OUTPUT 52 CONTROL

PA12/PGMD0 IN/OUT

PA11/PGMM3 IN/OUT

PA10/PGMM2 IN/OUT

INPUT

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Table 12-3. SAM7Sxx JTAG Boundary Scan Register (Continued)

Bit Number Pin Name Pin Type

Associated BSR

Cells

INPUT 50 OUTPUT

PA9/PGMM1 IN/OUT 49 CONTROL 48 47 OUTPUT

PA8/PGMM0 IN/OUT

INPUT

46 CONTROL 45 44 OUTPUT

PA7/PGMNVALID IN/OUT

INPUT

43 CONTROL 42 41 OUTPUT

PA6/PGMNOE IN/OUT

INPUT

40 CONTROL 39 38 OUTPUT

PA5/PGMRDY IN/OUT

INPUT

37 CONTROL 36 35 OUTPUT

PA4/PGMNCMD IN/OUT

INPUT

34 CONTROL 33 32 OUTPUT

PA25/PGMD13 IN/OUT

INPUT

(1)

31 CONTROL 30 29 OUTPUT

PA26/PGMD14 IN/OUT

INPUT

(1)

28 CONTROL 27 26 OUTPUT

PA27/PGMD15 IN/OUT

INPUT

(1)

25 CONTROL 24 23 OUTPUT

PA28 IN/OUT

INPUT

(1)

22 CONTROL

(1)

21 20 OUTPUT

PA3 IN/OUT

INPUT

19 CONTROL 18 17 OUTPUT

PA2 IN/OUT

INPUT

16 CONTROL

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Table 12-3. SAM7Sxx JTAG Boundary Scan Register (Continued)

Bit Number Pin Name Pin Type

Associated BSR

Cells

INPUT 14 OUTPUT 13 CONTROL 12 11 OUTPUT 10 CONTROL

9 8 OUTPUT 7 CONTROL 6 5 OUTPUT 4 CONTROL 3 2 OUTPUT 1 CONTROL 0 ERASE IN INPUT

Note: 1. Does not pertain to SAM7S32.

PA1/PGMEN1 IN/OUT

PA0/PGMEN0 IN/OUT

PA29 IN/OUT

PA30 IN/OUT

PA31 IN/OUT

INPUT

(1)

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12.5.5 ID Code Register

Access: Read-only

31 30 29 28 27 26 25 24

VERSION PART NUMBER

23 22 21 20 19 18 17 16

PART NUMBER

15 14 13 12 11 10 9 8

PART NUMBER MANUFACTURER IDENTITY

76543210

MANUF ACTURER IDENTITY 1

The JTAG D is used in the IEEE 1149.1 JTAG Boundary Scan.

• VERSION[31:28]: Product Version Number

Set to 0x0.

• PART NUMBER[27:12]: Product Part Number

Chip Name Chip ID

AT91SAM7S16 0x5B22 AT91SAM7S161 0x5B1F AT91SAM7S32 0x5B07 AT91SAM7S321 0x5B12 AT91SAM7S64 0x5B06 AT91SAM7S128 0x5B09 AT91SAM7S256 0x5B0A AT91SAM7S512 0x5B1A

• MANUFACTURER IDENTITY[11:1]

Set to 0x01F.

• Bit[0] Required by IEEE Std. 1149.1.

Set to 0x1.

Chip Name JTAG ID Code

AT91SAM7S16 05B2_203F AT91SAM7S161 05B1_F03F AT91SAM7S32 05B0_703F AT91SAM7S321 05B1_203F AT91SAM7S64 05B0_603F AT91SAM7S128 05B0_A03F AT91SAM7S256 05B0_903F AT91SAM7S512 05B1_A03F

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13. Reset Controller (RSTC)

NRST

Startup

Counter

proc_nreset

wd_fault

periph_nreset

SLCK

Reset

State

Manager

Reset Controller

brown_out

bod_rst_en

rstc_irq

NRST

Manager

exter_nreset

nrst_out

Main Supply

POR

WDRPROC

user_reset

Brownout

Manager

bod_reset

13.1 Overview

The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last.

The Reset Controller also drives independently or simultaneously t he external r eset and the periphe ral and pr ocessor resets.

A brownout detection is also available to prevent the processor from falling into an unpredictable state.

13.2 Block Diagram

Figure 13-1. Reset Controller Block Diagram

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13.3 Functional Description

External Reset Timer

URSTS

URSTEN

ERSTL

exter_nreset

URSTIEN

RSTC_MR

RSTC_SR

NRSTL

nrst_out

NRST

rstc_irq

Other

interrupt

sources

user_reset

13.3.1 Reset Controller Overview

The Reset Controller is made up of an NRST Manager, a Brownou t Manager , a Start up Counte r and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:

• proc_nreset: Processor reset line. It also resets the Watchdog Timer.

• periph_nreset: Affects the whole set of embedded peripherals.

• nrst_out: Drives the NRST pin.

These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generat ion of reset sig nals and pro vides a sig nal to the NRST Mana ger when an assertion of the NRST pin is required.

The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.

The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation.

13.3.2 NRS T Ma nage r

The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager.

Figure 13-2. NRST Manager

13.3.2.1 NRST Signal or Interrupt

The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager.

However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.

The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as th e pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.

The Reset Controller can also be programmed to ge ner at e a n inte rr upt in stea d o f g ene ra ting a re se t. To do so, t he bit URSTIEN in RSTC_MR must be written at 1.

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13.3.2.2 NRST External Reset Contro l

rstc_irq

brown_out

bod_reset

bod_rst_en

BODIEN

RSTC_MR

BODSTS

RSTC_SR

Other

interrupt

sources

The Reset State Manager asserts the signal ext_nreset to assert the NRST pin . When this occurs, the “nrst_ out” signal is driven low by the NRST Manager for a ti me pr ogrammed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2 duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.

This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset.

13.3.3 Brownout Manager

Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brow nout threshold, t he browno ut m anager r eq uests a br owno ut reset by asserting the bod_reset signal.

The programmer can disable the brownout reset by setting low the bo d_rst_ en input sig nal, i.e .; by lockin g th e corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read.

The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR. At factory, the brownout reset is disabled.

Figure 13-3. Brownout Manager

(ERSTL+1)

Slow Clock cycles. This gives the approximate

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13.3.4 Reset States

SLCK

periph_nreset

proc_nreset

Main Supply

POR output

NRST

(nrst_out)

EXTERNAL RESET LENGTH

= 2 cycles

Startup Time

MCK

Processor Startup

= 3 cycles

Any

Freq.

The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released.

13.3.4.1 Power-up Reset

When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the device.

The startup time, as shown in Figure 13-4, is hardcoded to comply with the Slow Clock Oscillator startup time. After the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset.

When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately.

Figure 13-4. Power-up Reset

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13.3.4.2 User Reset

SLCK

periph_nreset

proc_nreset

NRST

(nrst_out)

>= EXTERNAL RESET LENGTH

MCK

Processor Startup

= 3 cycles

Any

Freq.

Resynch.

2 cycles

RSTTYP

Any XXX

Resynch.

2 cycles

0x4 = User Reset

The User Reset is entered when a low level is detected on t he NRST pin and t he bi t URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.

The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted.

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset.

The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.

Figure 13-5. User Reset State

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13.3.4.3 Brownout Reset

SLCK

periph_nreset

proc_nreset

brown_out

or bod_reset

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x5 = Brownout Reset

Resynch.

2 cycles

When the brown_out/bod_reset signal is asserted, the Re set State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted.

The Brownout Reset is left Y Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered.

When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset.

Figure 13-6. Brownout Reset State

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13.3.4.4 Software Reset

SLCK

periph_nreset

if PERRST=1

proc_nreset

if PR

OCRST=1

ite RSTC_CR

NRST

(nrst_out)

if EXTRST=1

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x3 = Software Reset

Resynch.

1 cycle

SRCMP in RSTC_SR

The Reset Controller offers several commands used to assert the different reset signals. These commands ar e performed by writing the Control Register (RSTC_CR) with the following bits at 1:

• PROCRST: Writing PROCRST at 1 resets the processor and the watchdo g timer.

• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously.)

• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR).

The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts Y Slow Clock cycles.

The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.

If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.

If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.

As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as so on as the so ft war e re set is le ft. N o o th er so ftware reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.

Figure 13-7. Software Reset

13.3.4.5 Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts Y Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:

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• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted,

Only if

WDRPROC = 0

SLCK

periph_nreset

proc_nreset

wd_fault

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any XXX

0x2 = Watchdog Reset

depending on the programming of the field ERSTL. However , the resulting lo w level on NRST does not re sult in a User Reset state.

• If WDRPROC = 1, only the processor reset is asserted.

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum.

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset contro ller.

Figure 13-8. Watchdog Reset

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13.3.5 Reset State Priorities

The Reset State Manager manages the following priorities between the different reset sources, given in descending order:

•Power-up Reset

•Brownout Reset

• Watchdog Reset

• Software Reset

• User Reset

Particular cases are listed below:

• When in User Reset:

– A watchdog ev ent is impo ssible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated.

• When in Software Reset:

– A watchdog event has priority over the current state. – The NRST has no effect.

• When in Watchdog Reset:

– The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered.

13.3.6 Reset Controller Status Register

The Reset Controller status register (RSTC_SR) provides several status fields:

• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.

• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.

• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.

• URSTS bit : A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR re gis ter. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 13-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.

• BODST S bit: T his bit indicate s a br ownout de te ctio n wh en the brownout rese t is disa bled (bod_rst _e n = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt.

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Figure 13-9. Reset Controller Status and Interrupt

MCK

NRST

NRSTL

2 cycle

resynchronization

2 cycle

resynchronization

URSTS

read

RSTC_SR

Peripheral Access

rstc_irq

if (URSTEN = 0) and

(URSTIEN = 1)

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13.4 Reset Controller (RSTC) User Interface

Table 13-1. Register Mapping

Offset Register Name Access Reset

0x00 Control Register RSTC_CR Wr ite-only 0x04 Status Register RSTC_SR Read-only 0x0000_0000 0x08 Mode Register RSTC_MR Read-write 0x0000_0000

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13.4.1 Reset Controller Control Register Register Name: RSTC_CR

Access Type: Write-only

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 ––––EXTRSTPERRST–PROCRST

• PROCRST: Processor Reset

0 = No effect. 1 = If KEY is correct, resets the processor.

• PERRST: Peripheral Reset

0 = No effect. 1 = If KEY is correct, resets the peripherals.

• EXTRST: External Reset

0 = No effect. 1 = If KEY is correct, asserts the NRST pin.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

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13.4.2 Reset Controller Status Register Register Name: RSTC_SR

Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––SRCMPNRSTL

15 14 13 12 11 10 9 8

––––– RSTTYP

76543210 ––––––BODSTSURSTS

• URSTS: User Reset Status

0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.

• BODSTS: Brownout Detection Status

0 = No brownout high-to-low transition happened since the last read of RSTC_SR. 1 = A brownout high-to-low transition has been detected since the last read of RSTC_SR.

• RSTTYP: Reset Type

Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.

RSTTYP Reset Type Comments

0 0 0 Power-up Reset VDDCORE rising 0 1 0 Watchdog Reset Watchdog fault occurred 0 1 1 Software Reset Processor reset required by the software 1 0 0 User Reset NRST pin detected low 1 0 1 Brownout Reset BrownOut reset occurred

• NRSTL: NRST Pin Level

Registers the NRST Pin Level at Master Clock (MCK).

• SRCMP: Software Reset Command in Progress

0 = No software command is being performed by the reset controller. The reset controller is read y for a software command. 1 = A software reset command is being performed by the reset co ntroller. The reset controller is busy.

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13.4.3 Reset Controller Mode Register Register Name: RSTC_MR

Access Type: Read/Write

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

–––––––BODIEN

15 14 13 12 11 10 9 8

–––– ERSTL

76543210 –––URSTIEN–––URSTEN

• URSTEN: User Reset Enable

0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.

• URSTIEN: User Reset Interrupt Enable

0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.

• BODIEN: Brownout Detection Interrupt Enable

0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq.

• ERSTL: External Reset Length

This field defines the external reset le ngth. The external re set is asserted during a t ime of 2 allows assertion duration to be programmed between 60 µs and 2 seconds.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

(ERSTL+1)

Slow Clock cycles. This

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14. Real-time Timer (RTT)

SLCK

RTPRES

RTTINC

ALMS

16-bit

Divider

32-bit

Counter

ALMV

CRTV

RTT_MR

RTT_VR

RTT_AR

RTT_SR

RTTINCIEN

RTT_MR

ALMIEN

rtt_int

RTT_MR

set

RTT_SR

read

RTT_SR

reset

RTT_MR

reload

rtt_alarm

RTTRST

RTT_MR

RTTRST

14.1 Overview

The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value.

14.2 Block Diagram

Figure 14-1. Real-time Timer

14.3 Functional Description

The Real-time Timer is used to count elapsed seconds. It is built arou nd a 32-bit counte r fed by Slow Clock divided by a programmable 16-bit value. The value can be pro grammed in the fi eld RTPRES o f the Rea l-time Mode Register (RTT_MR).

Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 2 roll over to 0.

The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared t wo Slow Clock cycles after read. T hus if the RTT is conf igured to tr igger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler a nd re-enabled when the status register is clear.

The Real-time Timer value (CRTV) can be read at any t ime in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value.

seconds, corresponding to more than 136 years, then

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The current value of the counter is compared with the valu e writ ten in t he al arm re gist er RT T_AR (Rea l-t ime Alarm

Prescaler

ALMVALMV-10 ALMV+1

RTPRES - 1

RTT

APB cycle

read RTT_SR

ALMS (RTT_SR)

APB Interface

MCK

RTTINC (RTT_SR)

ALMV+2 ALMV+3

...

APB cycle

Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset.

The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz.

Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed

value. This also resets the 32-bit counter.

Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):

1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register.

2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register).

Figure 14-2. RTT Counting

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14.4 Real-time Timer (RTT) User Interface

Table 14-1. Register Mapping

Offset Register Name Access Reset

0x00 Mode Register RTT_MR Read-write 0x0000_8000 0x04 Alarm Register RTT_AR Read-write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000

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14.4.1 Real-time Timer Mode Register Register Name: RTT_MR

Access Type: Read-write

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––RTTRSTRTTINCIENALMIEN

15 14 13 12 11 10 9 8

RTPRES

76543210

RTPRES

• RTPRES: Real-time Timer Prescaler Value

Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows:

RTPRES = 0: The Prescaler Period is equal to 2 RTPRES ≠ 0: The Prescaler Period is equal to RTPRES.

• ALMIEN: Alarm Interrupt Enable

0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt.

• RTTINCIEN: Real-time Timer Increment Interrupt Enable

0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt.

• RTTRST: Real-time Timer Restart

1 = Reloads and restarts the clock divider with the new programmed value. This also re sets the 32-bit counter.

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14.4.2 Real-time Timer Alarm Register Register Name: RTT_AR

Access Type: Read-write

31 30 29 28 27 26 25 24

ALMV

23 22 21 20 19 18 17 16

ALMV

15 14 13 12 11 10 9 8

ALMV

76543210

ALMV

• ALMV: Alarm Value

Defines the alarm value (ALMV+1) compared with the Real-time Timer.

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14.4.3 Real-time Timer Value Register Register Name: RTT_VR

Access Type: Read-only

31 30 29 28 27 26 25 24

CRTV

23 22 21 20 19 18 17 16

CRTV

15 14 13 12 11 10 9 8

CRTV

76543210

CRTV

• CRTV: Current Real-time Value

Returns the current value of the Real-time Timer.

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14.4.4 Real-time Timer Status Register Register Name: RTT_SR

Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 ––––––RTTINCALMS

• ALMS: Real-time Alarm Status

0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.

• RTTINC: Real-time Timer Increment

0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RT T_SR.

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15. Periodic Interval Timer (PIT)

20-bit

Counter

MCK/16

PIV

PIT_MR

CPIV

PIT_PIVR

PICNT

12-bit

Adder

read PIT_PIVR

CPIV PICNT

PIT_PIIR

PITS

PIT_SR

set

reset

PITIEN

PIT_MR

pit_irq

MCK

Prescaler

= ?

15.1 Overview

The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems wit h long response time.

15.2 Block Diagram

Figure 15-1. Periodic Interval Timer

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15.3 Functional Description

MCK Prescaler

PIVPIV - 10

PITEN

CPIV

restarts MCK Prescaler

APB cycle

read PIT_PIVR

PICNT

PITS (PIT_SR)

MCK

APB Interface

APB cycle

The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a

20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the

Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR).

Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PI VR), the ov er-

flow counter (PICNT) is reset and the PITS is clea re d, thu s acknowledging the interrupt. The value of PICNT give s the number of periodic intervals elapsed since the last read of PIT_PIVR.

When CPIV and PICNT values are obtained by reading the Peri odic Interval I mage Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.

The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disab led on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again.

Figure 15-2. Enabling/Disabling PIT with PITEN

The PIT is stopped when the core enters debug state.

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15.4 Periodic Interval Timer (PIT) User Interface

Table 15-1. Register Mapping

Offset Register Name Access Reset

0x00 Mode Register PIT_MR Read-write 0x000F_FFFF 0x04 Status Register PIT_SR Read-only 0x0000_0000 0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000 0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000

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15.4.1 Periodic Interval Timer Mode Register Register Name: PIT_MR

Access Type: Read-write

31 30 29 28 27 26 25 24

––––––PITIENPITEN

23 22 21 20 19 18 17 16

–––– PIV

15 14 13 12 11 10 9 8

PIV

76543210

PIV

• PIV: Periodic Interval Value

Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).

• PITEN: Period Interval Timer Enabled

0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled.

• PITIEN: Periodic Interval Timer Interrupt Enable

0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt.

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15.4.2 Periodic Interval Timer Status Register Register Name: PIT_SR

Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––––––PITS

• PITS: Periodic Interval Timer Status

0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since th e last rea d of PIT_ PIVR .

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15.4.3 Periodic Interval Timer Value Register Register Name: PIT_PIVR

Access Type: Read-only

31 30 29 28 27 26 25 24

PICNT

23 22 21 20 19 18 17 16

PICNT CPIV

15 14 13 12 11 10 9 8

CPIV

76543210

CPIV

Reading this register clears PITS in PIT_SR.

• CPIV: Current Periodic Interval Value

Returns the current value of the periodic interval timer.

• PICNT: Periodic Interval Counter

Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.

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15.4.4 Periodic Interval Timer Image Register Register Name: PIT_PIIR

Access Type: Read-only

31 30 29 28 27 26 25 24

PICNT

23 22 21 20 19 18 17 16

PICNT CPIV

15 14 13 12 11 10 9 8

CPIV

76543210

CPIV

• CPIV: Current Periodic Interval Value

Returns the current value of the periodic interval timer.

• PICNT: Periodic Interval Counter

Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.

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16. Watchdog Timer (WDT)

set

reset

read WDT_SR or reset

wdt_fault

(to Reset Controller)

set

reset

WDFIEN

wdt_int

WDT_MR

SLCK

1/128

12-bit Down

Counter

Current

Value

WDD

WDT_MR

<= WDD

WDV

WDRSTT

WDT_MR

WDT_CR

reload

WDUNF

WDERR

reload

write WDT_MR

WDT_MR

WDRSTEN

16.1 Overview

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debu g mode or idle mode.

16.2 Block Diagram

Figure 16-1. Watchdog Timer Block Diagram

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16.3 Functional Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trappe d in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset.

The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).

After a Processor Reset, the value of WDV is 0xF FF, co rres pond ing to th e m aximu m v alue of th e co unter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires.

If the watchdog is restarted by writing into WDT_CR register, the WDT_MR register must not be programmed during a period of time of 3 slow clock period following the WDT_CR write access. In any case, programming a new value in WDT_MR automatically initiates a restart instruction.

The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters.

In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, an d t he Slow Clock 128 divider is reset and restarted. The WDT_CR r egi ster is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR).

To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register WDT_MR.

Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault” signal to the Reset Controller is asserted.

Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal).

The status bits WDUNF (Watchdog Underflow) an d WDERR ( Watchdog Error) tr igger an inte rrup t, pr ovided th e bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controlle r causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.

If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted.

Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value pro-

grammed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.

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Figure 16-2. Watchdog Behavior

WDV

WDD

WDT_CR = WDRSTT

Watchdog

Fault

Normal behavior

Watchdog Error

Watchdog Underflow

FFF

if WDRSTEN is 1

if WDRSTEN is 0

Forbidden

Window

Permitted

Window

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16.4 Watchdog Timer (WDT) User Interface

Table 16-1. Register Mapping

Offset Register Name Access Reset

0x00 Control Register WDT_CR Write-only 0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000

16.4.1 Watchdog Timer Control Register Register Name: WDT_CR

Access Type: Write-only

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––––––WDRSTT

• WDRSTT: Watchdog Restart

0: No effect. 1: Restarts the Watchdog.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

KEY

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16.4.2 Watchdog Timer Mode Register Register Name: WDT_MR

Access Type: Read-write Once

31 30 29 28 27 26 25 24

– – WDIDLEHLT WDDBGHLT WDD

23 22 21 20 19 18 17 16

WDD

15 14 13 12 11 10 9 8

WDDIS

76543210

• WDV: Watchdog Counter Value

Defines the value loaded in the 12-bit Watch dog Counter.

• WDFIEN: Watchdog Fault Interrupt Enable

0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt .

WDRPROC WDRSTEN WDFIEN WDV

WDV

• WDRSTEN: Watchdog Reset Enable

0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a Watchdog reset.

• WDRPROC: W atchdog Reset Processor

0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.

• WDD: Watchdog Delta Value

Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.

• WDDBGHLT: Watchdog Debug Halt

0: The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state.

• WDIDLEHLT: Watchdog Idle Halt

0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state.

• WDDIS: Watchdog Disable

0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer.

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16.4.3 Watchdog Timer Status Register Register Name: WDT_SR

Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 ––––––WDERRWDUNF

• WDUNF: Watchdog Underflow

0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.

• WDERR: Watchdog Error

0: No Watchdog error occurred since the last read of WDT_SR. 1: At least one Watchdog error occurred since the last read of WDT_SR. Note:The WDD and WDV values mu st not be mo dified within a per iod of time of 3 slow c lock peri ods followin g a re start o f

the watchdog performed by means of a write access in the WDT_CR register, else the watchdog may trigger an end of period earlier than expected.

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17. Voltage Regulator Mode Controller (VREG)

17.1 Overview

The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset.

This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake up the Voltage Regulator in Normal Mode.

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17.2 Voltage Regulator Power Controller (VREG) User Interface

Table 17-1. Register Mapping

Offset Register Name Access Reset

0x60 Voltage Regulator Mode Register VREG_MR Read-write 0x0

17.2.1 Voltage Regulator Mode Register Register Name: VREG_MR

Access Type: Read-write

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––––––PSTDBY

• PSTDBY: Periodic Interval Value

0 = Voltage regulator in normal mode. 1 = Voltage regulator in standby mode (low-p ower mode).

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18. Memory Controller (MC)

ARM7TDMI

Processor

Bus

Arbiter

Peripheral

DMA

Controller

Memory Controller

Abort

ASB

Abort

Status

Address

Decoder

User

Interface

Peripheral 0

Peripheral 1

Internal

RAM

APB

Bridge

Misalignment

Detector

From Master

to Slave

Peripheral N

Embedded

Flash

Controller

Internal

Flash

18.1 Overview

The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It f eat ur es a simple bus arbit er, an address decod er, an abort status, a misalignment detector and an Embedded Flash Controller.

18.2 Block Diagram

Figure 18-1. Memory Controller Block Diagram

18.3 Functional Description

The Memory Controller handles the internal ASB bus and arbitrates the accesses of both masters.

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It is made up of:

0x0000 0000

0x0FFF FFFF

0x1000 0000

0xEFFF FFFF

0xF000 0000

0xFFFF FFFF

256M Bytes

14 x 256MBytes

3,584 Mbytes

Internal Memories

Undefined

(Abort)

Peripherals

• A bus arbiter

• An address decoder

• An abort status

• A misalignment detector

• An Embedded Flash Controller

The MC handles only little-endian mode accesses. The masters work in little-endian mode only.

18.3.1 Bus Arbiter

The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the two masters. The Peripheral DMA Controller has the highest priority; the ARM processor has the lowest one.

18.3.2 Address Decoder

The Memory Controller features an Address Decoder that first decodes the four highest bits of the 32-bit address bus and defines three separate areas:

• One 256-Mbyte address space for the internal memories

• One 256-Mbyte address space reserved for th e embedded peripherals

• An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if accessed

Figure 18-2 shows the assignment of the 256-Mbyte memory areas.

Figure 18-2. Memory Areas

18.3.2.1 Internal Memory Mapping

Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eigh t more address bits to allocate 1-Mbyte address spaces for the embedded memories.

The allocated memories are accessed all along the 1-Mbyte address space and so are repeat ed n times within t his address space, n equaling 1M bytes divided by the size of the memory.

When the address of the access is undefined within the internal memory area, the Address Decoder returns an Abort to the master.

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If an access is done in the address area 0x0030 000 to 0x003F FFFF, no abort is generated.

256M Bytes

Internal Memory Area 0

Undefined Areas

(Abort)

0x0000 0000

0x000F FFFF

0x0010 0000

0x001F FFFF

0x0020 0000

0x002F FFFF

0x0FFF FFFF

1M Bytes

253M bytes

Internal Memory Area 1

Internal Flash

Internal Memory Area 2

Internal SRAM

0x0030 0000

Figure 18-3. Internal Memory Mapping

18.3.2.2 Internal Memory Area 0

The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in particular, the Reset Vector at address 0x0.

Before execution of the remap command, the on-chip Flash is mapped into Internal Memory Area 0, so that the ARM7TDMI reaches an executable instruction contained in Flash. After th e remap command, t he internal SRAM at address 0x0020 0000 is mapped into Internal Memory Are a 0. The memory mapp ed into Inter nal Memory Area 0 is accessible in both its original location and at address 0x0.

18.3.3 Remap Command

After execution, the Remap Command causes the Internal SRAM to be accessed through the Internal Memory Area 0.

As the ARM vectors (Reset, Abort, Data Abor t, Pr e fetch Ab or t, U nd efi ned In str uc tion, In ter ru p t, an d Fa st I nter rupt ) are mapped from address 0x0 to address 0x20, the Remap Command allows the user to redefine dynamically these vectors under software control.

The Remap Command is accessible through the Memory Controller User Interface by writing the MC_RCR (Remap Control Register) RCB field to one.

The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset.

18.3.4 Abort Status

There are three reasons for an abort to occur:

• access to an undefined address

• an access to a misaligned address.

When an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access. However, only the ARM7TDMI can take an abort signal into account, and only under the condition that it was generating an access. The Peripheral DMA Controller does not handle the abort input signal. Note that the connection is not represented in Figure 18-1.

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To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status register set.

The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in MC_ASR and include:

• the size of the request (field ABTSZ)

• the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)

• whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned add ress (bit MISADD)

• the source of the access leading to the last abort (bits MST0 and MST1)

• whether or not an abort occurred for each master since the last read of the register (bit SVMST0 and SVMST1 ) unless this information is loaded in MST bits

In the case of a Data Abort from the processor, the address of the data access is stored. This is useful, as searching for which address generated the abort would require disassembling the instructions and full knowledge of the processor context.

In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipelined in the ARM processor. The ARM processor takes the prefetch abort into account only if the read instruction is executed and it is probable that several aborts have occurred during t his time. Thus, in t his case, it is p refe rable t o use the con te nt of the Abort Link register of the ARM processor.

18.3.5 Embedded Flash Controller

The Embedded Flash Controller is added to the Memory Controller and ensures the interface of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages with the programming, erasing, locking and unlocking sequences thanks to a full se t of commands.

18.3.6 Misalignment Detector

The Memory Controller features a Misalignment Detector that checks the consistency of the accesses. For each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are

checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a halfword (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. Note that the accesses of the ARM processor when it is fetching instructio ns ar e no t ch eck ed .

The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particularly difficult to detect in the debug phase.

As the requested address is saved in the Abort Status Register and the address of the instruction generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bug is simplified.

18.4 Memory Controller (MC) User Interface

Base Address: 0xFFFFFF00 Table 18-1. Register Mapping

Offset Register Name Access Reset

0x00 MC Remap Control Register MC_RCR Write-only 0x04 MC Abort Status Register MC_ASR Read-only 0x0 0x08 MC Abort Address Status Register MC_AASR Read-only 0x0

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

100